src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/texstore.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_state.h"
  44 #include "brw_defines.h"
  45 #include "brw_wm.h"
  46
  47 static GLuint translate_tex_target( GLenum target )
  48 {
  49    switch (target) {
  50    case GL_TEXTURE_1D:
  51       return BRW_SURFACE_1D;
  52
  53    case GL_TEXTURE_RECTANGLE_NV:
  54       return BRW_SURFACE_2D;
  55
  56    case GL_TEXTURE_2D:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_3D:
  60       return BRW_SURFACE_3D;
  61
  62    case GL_TEXTURE_CUBE_MAP:
  63       return BRW_SURFACE_CUBE;
  64
  65    default:
  66       assert(0);
  67       return 0;
  68    }
  69 }
  70
  71 static uint32_t brw_format_for_mesa_format[MESA_FORMAT_COUNT] =
  72 {
  73    [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
  74    [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
  75    [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
  76    [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
  77    [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
  78    [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
  79    [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
  80    [MESA_FORMAT_RG88] = BRW_SURFACEFORMAT_R8G8_UNORM,
  81    [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
  82    [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
  83    [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
  84    [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
  85    [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
  86    [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
  87    [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
  88    [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
  89    [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
  90    [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
  91    [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
  92    [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
  93    [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
  94    [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
  95    [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
  96    [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
  97    [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
  98    [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
  99    [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 100    [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 101    [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 102    [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 103    [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 104 };
 105
 106 bool
 107 brw_render_target_supported(gl_format format)
 108 {
 109    if (format == MESA_FORMAT_S8_Z24 ||
 110        format == MESA_FORMAT_X8_Z24 ||
 111        format == MESA_FORMAT_Z16) {
 112       return true;
 113    }
 114
 115    /* Not exactly true, as some of those formats are not renderable.
 116     * But at least we know how to translate them.
 117     */
 118    return brw_format_for_mesa_format[format] != 0;
 119 }
 120
 121 static GLuint translate_tex_format( gl_format mesa_format,
 122                                     GLenum internal_format,
 123                                     GLenum depth_mode,
 124                                     GLenum srgb_decode )
 125 {
 126    switch( mesa_format ) {
 127
 128    case MESA_FORMAT_Z16:
 129       if (depth_mode == GL_INTENSITY)
 130           return BRW_SURFACEFORMAT_I16_UNORM;
 131       else if (depth_mode == GL_ALPHA)
 132           return BRW_SURFACEFORMAT_A16_UNORM;
 133       else if (depth_mode == GL_RED)
 134           return BRW_SURFACEFORMAT_R16_UNORM;
 135       else
 136           return BRW_SURFACEFORMAT_L16_UNORM;
 137
 138    case MESA_FORMAT_S8_Z24:
 139       /* XXX: these different surface formats don't seem to
 140        * make any difference for shadow sampler/compares.
 141        */
 142       if (depth_mode == GL_INTENSITY)
 143          return BRW_SURFACEFORMAT_I24X8_UNORM;
 144       else if (depth_mode == GL_ALPHA)
 145          return BRW_SURFACEFORMAT_A24X8_UNORM;
 146       else if (depth_mode == GL_RED)
 147          return BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS;
 148       else
 149          return BRW_SURFACEFORMAT_L24X8_UNORM;
 150
 151    case MESA_FORMAT_SARGB8:
 152    case MESA_FORMAT_SLA8:
 153    case MESA_FORMAT_SL8:
 154       if (srgb_decode == GL_DECODE_EXT)
 155          return brw_format_for_mesa_format[mesa_format];
 156       else if (srgb_decode == GL_SKIP_DECODE_EXT)
 157          return brw_format_for_mesa_format[_mesa_get_srgb_format_linear(mesa_format)];
 158    default:
 159       assert(brw_format_for_mesa_format[mesa_format] != 0);
 160       return brw_format_for_mesa_format[mesa_format];
 161    }
 162 }
 163
 164 static void
 165 brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
 166 {
 167    switch (tiling) {
 168    case I915_TILING_NONE:
 169       surf->ss3.tiled_surface = 0;
 170       surf->ss3.tile_walk = 0;
 171       break;
 172    case I915_TILING_X:
 173       surf->ss3.tiled_surface = 1;
 174       surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
 175       break;
 176    case I915_TILING_Y:
 177       surf->ss3.tiled_surface = 1;
 178       surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
 179       break;
 180    }
 181 }
 182
 183 static void
 184 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 185 {
 186    struct brw_context *brw = brw_context(ctx);
 187    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 188    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 189    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 190    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 191    struct brw_surface_state surf;
 192    void *map;
 193
 194    memset(&surf, 0, sizeof(surf));
 195
 196    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 197    surf.ss0.surface_type = translate_tex_target(tObj->Target);
 198    surf.ss0.surface_format = translate_tex_format(firstImage->TexFormat,
 199                                                   firstImage->InternalFormat,
 200                                                   tObj->DepthMode, tObj->sRGBDecode);
 201
 202    /* This is ok for all textures with channel width 8bit or less:
 203     */
 204 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
 205    surf.ss1.base_addr = intelObj->mt->region->buffer->offset; /* reloc */
 206
 207    surf.ss2.mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
 208    surf.ss2.width = firstImage->Width - 1;
 209    surf.ss2.height = firstImage->Height - 1;
 210    brw_set_surface_tiling(&surf, intelObj->mt->region->tiling);
 211    surf.ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1;
 212    surf.ss3.depth = firstImage->Depth - 1;
 213
 214    surf.ss4.min_lod = 0;
 215
 216    if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
 217       surf.ss0.cube_pos_x = 1;
 218       surf.ss0.cube_pos_y = 1;
 219       surf.ss0.cube_pos_z = 1;
 220       surf.ss0.cube_neg_x = 1;
 221       surf.ss0.cube_neg_y = 1;
 222       surf.ss0.cube_neg_z = 1;
 223    }
 224
 225    map = brw_state_batch(brw, sizeof(surf), 32,
 226                          &brw->wm.surf_bo[surf_index],
 227                          &brw->wm.surf_offset[surf_index]);
 228    memcpy(map, &surf, sizeof(surf));
 229
 230    /* Emit relocation to surface contents */
 231    drm_intel_bo_emit_reloc(brw->wm.surf_bo[surf_index],
 232                            brw->wm.surf_offset[surf_index] +
 233                            offsetof(struct brw_surface_state, ss1),
 234                            intelObj->mt->region->buffer, 0,
 235                            I915_GEM_DOMAIN_SAMPLER, 0);
 236 }
 237
 238 /**
 239  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 240  * read from this buffer with Data Port Read instructions/messages.
 241  */
 242 void
 243 brw_create_constant_surface(struct brw_context *brw,
 244                             drm_intel_bo *bo,
 245                             int width,
 246                             drm_intel_bo **out_bo,
 247                             uint32_t *out_offset)
 248 {
 249    struct intel_context *intel = &brw->intel;
 250    const GLint w = width - 1;
 251    struct brw_surface_state surf;
 252    void *map;
 253
 254    memset(&surf, 0, sizeof(surf));
 255
 256    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 257    surf.ss0.surface_type = BRW_SURFACE_BUFFER;
 258    surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 259
 260    if (intel->gen >= 6)
 261       surf.ss0.render_cache_read_write = 1;
 262
 263    assert(bo);
 264    surf.ss1.base_addr = bo->offset; /* reloc */
 265
 266    surf.ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
 267    surf.ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
 268    surf.ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
 269    surf.ss3.pitch = (width * 16) - 1; /* ignored?? */
 270    brw_set_surface_tiling(&surf, I915_TILING_NONE); /* tiling now allowed */
 271
 272    map = brw_state_batch(brw, sizeof(surf), 32, out_bo, out_offset);
 273    memcpy(map, &surf, sizeof(surf));
 274
 275    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 276     * bspec ("Data Cache") says that the data cache does not exist as
 277     * a separate cache and is just the sampler cache.
 278     */
 279    drm_intel_bo_emit_reloc(*out_bo, (*out_offset +
 280                                      offsetof(struct brw_surface_state, ss1)),
 281                            bo, 0,
 282                            I915_GEM_DOMAIN_SAMPLER, 0);
 283 }
 284
 285 /* Creates a new WM constant buffer reflecting the current fragment program's
 286  * constants, if needed by the fragment program.
 287  *
 288  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 289  * state atom.
 290  */
 291 static void
 292 prepare_wm_constants(struct brw_context *brw)
 293 {
 294    struct gl_context *ctx = &brw->intel.ctx;
 295    struct intel_context *intel = &brw->intel;
 296    struct brw_fragment_program *fp =
 297       (struct brw_fragment_program *) brw->fragment_program;
 298    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 299    float *constants;
 300    unsigned int i;
 301
 302    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
 303
 304    /* BRW_NEW_FRAGMENT_PROGRAM */
 305    if (brw->wm.prog_data->nr_pull_params == 0) {
 306       if (brw->wm.const_bo) {
 307          drm_intel_bo_unreference(brw->wm.const_bo);
 308          brw->wm.const_bo = NULL;
 309          brw->state.dirty.brw |= BRW_NEW_WM_CONSTBUF;
 310       }
 311       return;
 312    }
 313
 314    drm_intel_bo_unreference(brw->wm.const_bo);
 315    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
 316                                          size, 64);
 317
 318    /* _NEW_PROGRAM_CONSTANTS */
 319    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
 320    constants = brw->wm.const_bo->virtual;
 321    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 322       constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
 323                                    *brw->wm.prog_data->pull_param[i]);
 324    }
 325    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 326
 327    brw->state.dirty.brw |= BRW_NEW_WM_CONSTBUF;
 328 }
 329
 330 const struct brw_tracked_state brw_wm_constants = {
 331    .dirty = {
 332       .mesa = (_NEW_PROGRAM_CONSTANTS),
 333       .brw = (BRW_NEW_FRAGMENT_PROGRAM),
 334       .cache = 0
 335    },
 336    .prepare = prepare_wm_constants,
 337 };
 338
 339 /**
 340  * Updates surface / buffer for fragment shader constant buffer, if
 341  * one is required.
 342  *
 343  * This consumes the state updates for the constant buffer, and produces
 344  * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
 345  * inclusion in the binding table.
 346  */
 347 static void upload_wm_constant_surface(struct brw_context *brw )
 348 {
 349    GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
 350    struct brw_fragment_program *fp =
 351       (struct brw_fragment_program *) brw->fragment_program;
 352    const struct gl_program_parameter_list *params =
 353       fp->program.Base.Parameters;
 354
 355    /* If there's no constant buffer, then no surface BO is needed to point at
 356     * it.
 357     */
 358    if (brw->wm.const_bo == 0) {
 359       if (brw->wm.surf_bo[surf] != NULL) {
 360          drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 361          brw->wm.surf_bo[surf] = NULL;
 362          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 363       }
 364       return;
 365    }
 366
 367    brw_create_constant_surface(brw, brw->wm.const_bo, params->NumParameters,
 368                                &brw->wm.surf_bo[surf],
 369                                &brw->wm.surf_offset[surf]);
 370    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 371 }
 372
 373 const struct brw_tracked_state brw_wm_constant_surface = {
 374    .dirty = {
 375       .mesa = 0,
 376       .brw = (BRW_NEW_WM_CONSTBUF |
 377               BRW_NEW_BATCH),
 378       .cache = 0
 379    },
 380    .emit = upload_wm_constant_surface,
 381 };
 382
 383 static void
 384 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 385 {
 386    struct intel_context *intel = &brw->intel;
 387    struct brw_surface_state surf;
 388    void *map;
 389
 390    memset(&surf, 0, sizeof(surf));
 391
 392    surf.ss0.surface_type = BRW_SURFACE_NULL;
 393    surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 394    surf.ss1.base_addr = 0;
 395
 396    surf.ss2.width = 0;
 397    surf.ss2.height = 0;
 398    brw_set_surface_tiling(&surf, I915_TILING_NONE);
 399    surf.ss3.pitch = 0;
 400
 401    if (intel->gen < 6) {
 402       /* _NEW_COLOR */
 403       surf.ss0.color_blend = 0;
 404       surf.ss0.writedisable_red =   1;
 405       surf.ss0.writedisable_green = 1;
 406       surf.ss0.writedisable_blue =  1;
 407       surf.ss0.writedisable_alpha = 1;
 408    }
 409
 410    map = brw_state_batch(brw, sizeof(surf), 32,
 411                          &brw->wm.surf_bo[unit],
 412                          &brw->wm.surf_offset[unit]);
 413    memcpy(map, &surf, sizeof(surf));
 414 }
 415
 416 /**
 417  * Sets up a surface state structure to point at the given region.
 418  * While it is only used for the front/back buffer currently, it should be
 419  * usable for further buffers when doing ARB_draw_buffer support.
 420  */
 421 static void
 422 brw_update_renderbuffer_surface(struct brw_context *brw,
 423                                 struct gl_renderbuffer *rb,
 424                                 unsigned int unit)
 425 {
 426    struct intel_context *intel = &brw->intel;
 427    struct gl_context *ctx = &intel->ctx;
 428    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 429    struct intel_region *region = irb->region;
 430    struct brw_surface_state surf;
 431    void *map;
 432
 433    memset(&surf, 0, sizeof(surf));
 434
 435    switch (irb->Base.Format) {
 436    case MESA_FORMAT_XRGB8888:
 437       /* XRGB is handled as ARGB because the chips in this family
 438        * cannot render to XRGB targets.  This means that we have to
 439        * mask writes to alpha (ala glColorMask) and reconfigure the
 440        * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 441        * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 442        * used.
 443        */
 444       surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 445       break;
 446    case MESA_FORMAT_SARGB8:
 447       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 448          surfaces to the blend/update as sRGB */
 449       if (ctx->Color.sRGBEnabled)
 450          surf.ss0.surface_format = brw_format_for_mesa_format[irb->Base.Format];
 451       else
 452          surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 453       break;
 454    default:
 455       surf.ss0.surface_format = brw_format_for_mesa_format[irb->Base.Format];
 456       assert(surf.ss0.surface_format != 0);
 457    }
 458
 459    surf.ss0.surface_type = BRW_SURFACE_2D;
 460    if (region->tiling == I915_TILING_NONE) {
 461       surf.ss1.base_addr = (region->draw_x +
 462                             region->draw_y * region->pitch) * region->cpp;
 463    } else {
 464       uint32_t tile_base, tile_x, tile_y;
 465       uint32_t pitch = region->pitch * region->cpp;
 466
 467       if (region->tiling == I915_TILING_X) {
 468          tile_x = region->draw_x % (512 / region->cpp);
 469          tile_y = region->draw_y % 8;
 470          tile_base = ((region->draw_y / 8) * (8 * pitch));
 471          tile_base += (region->draw_x - tile_x) / (512 / region->cpp) * 4096;
 472       } else {
 473          /* Y */
 474          tile_x = region->draw_x % (128 / region->cpp);
 475          tile_y = region->draw_y % 32;
 476          tile_base = ((region->draw_y / 32) * (32 * pitch));
 477          tile_base += (region->draw_x - tile_x) / (128 / region->cpp) * 4096;
 478       }
 479       assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 480       assert(tile_x % 4 == 0);
 481       assert(tile_y % 2 == 0);
 482       /* Note that the low bits of these fields are missing, so
 483        * there's the possibility of getting in trouble.
 484        */
 485       surf.ss1.base_addr = tile_base;
 486       surf.ss5.x_offset = tile_x / 4;
 487       surf.ss5.y_offset = tile_y / 2;
 488    }
 489    surf.ss1.base_addr += region->buffer->offset; /* reloc */
 490
 491    surf.ss2.width = rb->Width - 1;
 492    surf.ss2.height = rb->Height - 1;
 493    brw_set_surface_tiling(&surf, region->tiling);
 494    surf.ss3.pitch = (region->pitch * region->cpp) - 1;
 495
 496    if (intel->gen < 6) {
 497       /* _NEW_COLOR */
 498       surf.ss0.color_blend = (!ctx->Color._LogicOpEnabled &&
 499                               (ctx->Color.BlendEnabled & (1 << unit)));
 500       surf.ss0.writedisable_red =   !ctx->Color.ColorMask[unit][0];
 501       surf.ss0.writedisable_green = !ctx->Color.ColorMask[unit][1];
 502       surf.ss0.writedisable_blue =  !ctx->Color.ColorMask[unit][2];
 503       /* As mentioned above, disable writes to the alpha component when the
 504        * renderbuffer is XRGB.
 505        */
 506       if (ctx->DrawBuffer->Visual.alphaBits == 0)
 507          surf.ss0.writedisable_alpha = 1;
 508       else
 509          surf.ss0.writedisable_alpha = !ctx->Color.ColorMask[unit][3];
 510    }
 511
 512    map = brw_state_batch(brw, sizeof(surf), 32,
 513                          &brw->wm.surf_bo[unit],
 514                          &brw->wm.surf_offset[unit]);
 515    memcpy(map, &surf, sizeof(surf));
 516
 517    drm_intel_bo_emit_reloc(brw->wm.surf_bo[unit],
 518                            brw->wm.surf_offset[unit] +
 519                            offsetof(struct brw_surface_state, ss1),
 520                            region->buffer,
 521                            surf.ss1.base_addr - region->buffer->offset,
 522                            I915_GEM_DOMAIN_RENDER,
 523                            I915_GEM_DOMAIN_RENDER);
 524 }
 525
 526 static void
 527 prepare_wm_surfaces(struct brw_context *brw)
 528 {
 529    struct gl_context *ctx = &brw->intel.ctx;
 530    int i;
 531    int nr_surfaces = 0;
 532
 533    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 534       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 535          struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
 536          struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 537          struct intel_region *region = irb ? irb->region : NULL;
 538
 539          brw_add_validated_bo(brw, region->buffer);
 540          nr_surfaces = SURF_INDEX_DRAW(i) + 1;
 541       }
 542    }
 543
 544    if (brw->wm.const_bo) {
 545       brw_add_validated_bo(brw, brw->wm.const_bo);
 546       nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
 547    }
 548
 549    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 550       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 551       struct gl_texture_object *tObj = texUnit->_Current;
 552       struct intel_texture_object *intelObj = intel_texture_object(tObj);
 553
 554       if (texUnit->_ReallyEnabled) {
 555          brw_add_validated_bo(brw, intelObj->mt->region->buffer);
 556          nr_surfaces = SURF_INDEX_TEXTURE(i) + 1;
 557       }
 558    }
 559
 560    /* Have to update this in our prepare, since the unit's prepare
 561     * relies on it.
 562     */
 563    if (brw->wm.nr_surfaces != nr_surfaces) {
 564       brw->wm.nr_surfaces = nr_surfaces;
 565       brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
 566    }
 567 }
 568
 569 /**
 570  * Constructs the set of surface state objects pointed to by the
 571  * binding table.
 572  */
 573 static void
 574 upload_wm_surfaces(struct brw_context *brw)
 575 {
 576    struct gl_context *ctx = &brw->intel.ctx;
 577    GLuint i;
 578
 579    /* _NEW_BUFFERS | _NEW_COLOR */
 580    /* Update surfaces for drawing buffers */
 581    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 582       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 583          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
 584             brw_update_renderbuffer_surface(brw,
 585                                             ctx->DrawBuffer->_ColorDrawBuffers[i],
 586                                             i);
 587          } else {
 588             brw_update_null_renderbuffer_surface(brw, i);
 589          }
 590       }
 591    } else {
 592       brw_update_null_renderbuffer_surface(brw, 0);
 593    }
 594
 595    /* Update surfaces for textures */
 596    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 597       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 598       const GLuint surf = SURF_INDEX_TEXTURE(i);
 599
 600       /* _NEW_TEXTURE */
 601       if (texUnit->_ReallyEnabled) {
 602          brw_update_texture_surface(ctx, i);
 603       } else {
 604          drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 605          brw->wm.surf_bo[surf] = NULL;
 606       }
 607    }
 608
 609    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 610 }
 611
 612 const struct brw_tracked_state brw_wm_surfaces = {
 613    .dirty = {
 614       .mesa = (_NEW_COLOR |
 615                _NEW_TEXTURE |
 616                _NEW_BUFFERS),
 617       .brw = (BRW_NEW_BATCH),
 618       .cache = 0
 619    },
 620    .prepare = prepare_wm_surfaces,
 621    .emit = upload_wm_surfaces,
 622 };
 623
 624 /**
 625  * Constructs the binding table for the WM surface state, which maps unit
 626  * numbers to surface state objects.
 627  */
 628 static void
 629 brw_wm_upload_binding_table(struct brw_context *brw)
 630 {
 631    uint32_t *bind;
 632    int i;
 633
 634    /* Might want to calculate nr_surfaces first, to avoid taking up so much
 635     * space for the binding table.
 636     */
 637    bind = brw_state_batch(brw, sizeof(uint32_t) * BRW_WM_MAX_SURF,
 638                           32, &brw->wm.bind_bo, &brw->wm.bind_bo_offset);
 639
 640    for (i = 0; i < BRW_WM_MAX_SURF; i++) {
 641       /* BRW_NEW_WM_SURFACES */
 642       bind[i] = brw->wm.surf_offset[i];
 643       if (brw->wm.surf_bo[i]) {
 644          bind[i] = brw->wm.surf_offset[i];
 645       } else {
 646          bind[i] = 0;
 647       }
 648    }
 649
 650    brw->state.dirty.brw |= BRW_NEW_BINDING_TABLE;
 651 }
 652
 653 const struct brw_tracked_state brw_wm_binding_table = {
 654    .dirty = {
 655       .mesa = 0,
 656       .brw = (BRW_NEW_BATCH |
 657               BRW_NEW_WM_SURFACES),
 658       .cache = 0
 659    },
 660    .emit = brw_wm_upload_binding_table,
 661 };