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i965: Rename BRW_NEW_WM_SURFACES to BRW_NEW_SURFACES.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_surface_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/mtypes.h"
34 #include "main/samplerobj.h"
35 #include "program/prog_parameter.h"
36
37 #include "intel_mipmap_tree.h"
38 #include "intel_batchbuffer.h"
39 #include "intel_tex.h"
40 #include "intel_fbo.h"
41 #include "intel_buffer_objects.h"
42
43 #include "brw_context.h"
44 #include "brw_state.h"
45 #include "brw_defines.h"
46 #include "brw_wm.h"
47
48 GLuint
49 translate_tex_target(GLenum target)
50 {
51 switch (target) {
52 case GL_TEXTURE_1D:
53 case GL_TEXTURE_1D_ARRAY_EXT:
54 return BRW_SURFACE_1D;
55
56 case GL_TEXTURE_RECTANGLE_NV:
57 return BRW_SURFACE_2D;
58
59 case GL_TEXTURE_2D:
60 case GL_TEXTURE_2D_ARRAY_EXT:
61 return BRW_SURFACE_2D;
62
63 case GL_TEXTURE_3D:
64 return BRW_SURFACE_3D;
65
66 case GL_TEXTURE_CUBE_MAP:
67 return BRW_SURFACE_CUBE;
68
69 default:
70 assert(0);
71 return 0;
72 }
73 }
74
75 struct surface_format_info {
76 bool exists;
77 int sampling;
78 int filtering;
79 int shadow_compare;
80 int chroma_key;
81 int render_target;
82 int alpha_blend;
83 int input_vb;
84 int streamed_output_vb;
85 int color_processing;
86 };
87
88 /* This macro allows us to write the table almost as it appears in the PRM,
89 * while restructuring it to turn it into the C code we want.
90 */
91 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
92 [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
93
94 #define Y 0
95 #define x 999
96 /**
97 * This is the table of support for surface (texture, renderbuffer, and vertex
98 * buffer, but not depthbuffer) formats across the various hardware generations.
99 *
100 * The table is formatted to match the documentation, except that the docs have
101 * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever". To put
102 * it in our table, here's the mapping:
103 *
104 * Y*: 45
105 * Y+: 45 (g45/gm45)
106 * Y~: 50 (gen5)
107 * Y^: 60 (gen6)
108 * Y#: 70 (gen7)
109 *
110 * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
111 */
112 const struct surface_format_info surface_formats[] = {
113 /* smpl filt shad CK RT AB VB SO color */
114 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
115 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
116 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
117 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
118 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
119 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64_FLOAT)
120 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
121 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
122 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
123 SF( Y, 50, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
124 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_SINT)
125 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_UINT)
126 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
127 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
128 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
129 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
130 SF( Y, Y, x, x, Y, 45, Y, x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
131 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
132 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
133 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
134 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
135 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32_FLOAT)
136 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_SINT)
137 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_UINT)
138 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
139 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
140 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32A32_FLOAT)
141 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_UNORM)
142 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SNORM)
143 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64_FLOAT)
144 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
145 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
146 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32X32_FLOAT)
147 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32X32_FLOAT)
148 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32X32_FLOAT)
149 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
150 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
151 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SSCALED)
152 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_USCALED)
153 SF( Y, Y, x, Y, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
154 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
155 /* smpl filt shad CK RT AB VB SO color */
156 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
157 SF( Y, Y, x, x, x, x, x, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
158 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
159 SF( Y, Y, x, x, x, Y, Y, x, x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
160 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
161 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
162 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
163 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
164 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
165 SF( Y, Y, x, x, Y, 45, Y, x, x, BRW_SURFACEFORMAT_R16G16_UNORM)
166 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16_SNORM)
167 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SINT)
168 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_UINT)
169 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16_FLOAT)
170 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
171 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
172 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
173 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_SINT)
174 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_UINT)
175 SF( Y, 50, Y, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32_FLOAT)
176 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
177 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
178 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_UNORM)
179 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I24X8_UNORM)
180 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L24X8_UNORM)
181 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A24X8_UNORM)
182 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32_FLOAT)
183 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32_FLOAT)
184 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32_FLOAT)
185 SF( Y, Y, x, Y, x, x, x, x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
186 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
187 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
188 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
189 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
190 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
191 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_FLOAT)
192 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_UNORM)
193 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SNORM)
194 /* smpl filt shad CK RT AB VB SO color */
195 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
196 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
197 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
198 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SSCALED)
199 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_USCALED)
200 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SSCALED)
201 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_USCALED)
202 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
203 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
204 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
205 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
206 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
207 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
208 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8G8_UNORM)
209 SF( Y, Y, x, Y, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8_SNORM)
210 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SINT)
211 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_UINT)
212 SF( Y, Y, Y, x, Y, 45, Y, x, 70, BRW_SURFACEFORMAT_R16_UNORM)
213 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16_SNORM)
214 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_SINT)
215 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_UINT)
216 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16_FLOAT)
217 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_UNORM)
218 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_UNORM)
219 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_UNORM)
220 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM)
221 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_FLOAT)
222 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_FLOAT)
223 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_FLOAT)
224 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
225 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
226 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
227 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
228 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SSCALED)
229 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_USCALED)
230 /* smpl filt shad CK RT AB VB SO color */
231 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_SSCALED)
232 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_USCALED)
233 SF( Y, Y, x, 45, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8_UNORM)
234 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8_SNORM)
235 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_SINT)
236 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_UINT)
237 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_A8_UNORM)
238 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_UNORM)
239 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM)
240 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P4A4_UNORM)
241 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4P4_UNORM)
242 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_SSCALED)
243 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_USCALED)
244 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
245 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
246 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R1_UINT)
247 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
248 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
249 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM)
250 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM)
251 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM)
252 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_UNORM)
253 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_UNORM)
254 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
255 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
256 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
257 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_MONO8)
258 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
259 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
260 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB)
261 /* smpl filt shad CK RT AB VB SO color */
262 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_FXT1)
263 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
264 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
265 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
266 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
267 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
268 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
269 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_SNORM)
270 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_SNORM)
271 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
272 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
273 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
274 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
275 };
276 #undef x
277 #undef Y
278
279 uint32_t
280 brw_format_for_mesa_format(gl_format mesa_format)
281 {
282 /* This table is ordered according to the enum ordering in formats.h. We do
283 * expect that enum to be extended without our explicit initialization
284 * staying in sync, so we initialize to 0 even though
285 * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
286 */
287 static const uint32_t table[MESA_FORMAT_COUNT] =
288 {
289 [MESA_FORMAT_RGBA8888] = 0,
290 [MESA_FORMAT_RGBA8888_REV] = 0,
291 [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
292 [MESA_FORMAT_ARGB8888_REV] = 0,
293 [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
294 [MESA_FORMAT_XRGB8888_REV] = 0,
295 [MESA_FORMAT_RGB888] = 0,
296 [MESA_FORMAT_BGR888] = 0,
297 [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
298 [MESA_FORMAT_RGB565_REV] = 0,
299 [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
300 [MESA_FORMAT_ARGB4444_REV] = 0,
301 [MESA_FORMAT_RGBA5551] = 0,
302 [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
303 [MESA_FORMAT_ARGB1555_REV] = 0,
304 [MESA_FORMAT_AL44] = 0,
305 [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
306 [MESA_FORMAT_AL88_REV] = 0,
307 [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
308 [MESA_FORMAT_AL1616_REV] = 0,
309 [MESA_FORMAT_RGB332] = 0,
310 [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
311 [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
312 [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
313 [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
314 [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
315 [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
316 [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
317 [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
318 [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
319 [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
320 [MESA_FORMAT_RG88] = 0,
321 [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
322 [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
323 [MESA_FORMAT_RG1616_REV] = 0,
324 [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
325 [MESA_FORMAT_Z24_S8] = 0,
326 [MESA_FORMAT_S8_Z24] = 0,
327 [MESA_FORMAT_Z16] = 0,
328 [MESA_FORMAT_X8_Z24] = 0,
329 [MESA_FORMAT_Z24_S8] = 0,
330 [MESA_FORMAT_Z32] = 0,
331 [MESA_FORMAT_S8] = 0,
332
333 [MESA_FORMAT_SRGB8] = 0,
334 [MESA_FORMAT_SRGBA8] = 0,
335 [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
336 [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
337 [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
338 [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
339 [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
340 [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
341 [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
342
343 [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
344 [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
345 [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
346 [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
347 [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
348 [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
349
350 [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
351 [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
352 [MESA_FORMAT_RGB_FLOAT32] = 0,
353 [MESA_FORMAT_RGB_FLOAT16] = 0,
354 [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
355 [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
356 [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
357 [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
358 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
359 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
360 [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
361 [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
362 [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
363 [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
364 [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
365 [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
366
367 [MESA_FORMAT_ALPHA_UINT8] = 0,
368 [MESA_FORMAT_ALPHA_UINT16] = 0,
369 [MESA_FORMAT_ALPHA_UINT32] = 0,
370 [MESA_FORMAT_ALPHA_INT8] = 0,
371 [MESA_FORMAT_ALPHA_INT16] = 0,
372 [MESA_FORMAT_ALPHA_INT32] = 0,
373
374 [MESA_FORMAT_INTENSITY_UINT8] = 0,
375 [MESA_FORMAT_INTENSITY_UINT16] = 0,
376 [MESA_FORMAT_INTENSITY_UINT32] = 0,
377 [MESA_FORMAT_INTENSITY_INT8] = 0,
378 [MESA_FORMAT_INTENSITY_INT16] = 0,
379 [MESA_FORMAT_INTENSITY_INT32] = 0,
380
381 [MESA_FORMAT_LUMINANCE_UINT8] = 0,
382 [MESA_FORMAT_LUMINANCE_UINT16] = 0,
383 [MESA_FORMAT_LUMINANCE_UINT32] = 0,
384 [MESA_FORMAT_LUMINANCE_INT8] = 0,
385 [MESA_FORMAT_LUMINANCE_INT16] = 0,
386 [MESA_FORMAT_LUMINANCE_INT32] = 0,
387
388 [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
389 [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
390 [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
391 [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
392 [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
393 [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
394
395 [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
396 [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
397 [MESA_FORMAT_RGB_INT8] = 0,
398 [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
399 [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
400 [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
401 [MESA_FORMAT_RGB_INT16] = 0,
402 [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
403 [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
404 [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
405 [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
406 [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
407
408 [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
409 [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
410 [MESA_FORMAT_RGB_UINT8] = 0,
411 [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
412 [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
413 [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
414 [MESA_FORMAT_RGB_UINT16] = 0,
415 [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
416 [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
417 [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
418 [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
419 [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
420
421 [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
422 [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
423 [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
424 [MESA_FORMAT_SIGNED_RGBX8888] = 0,
425 [MESA_FORMAT_SIGNED_RGBA8888] = 0,
426 [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
427 [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
428 [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
429 [MESA_FORMAT_SIGNED_RGB_16] = 0,
430 [MESA_FORMAT_SIGNED_RGBA_16] = 0,
431 [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
432
433 [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
434 [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
435 [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
436 [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
437
438 [MESA_FORMAT_L_LATC1] = 0,
439 [MESA_FORMAT_SIGNED_L_LATC1] = 0,
440 [MESA_FORMAT_LA_LATC2] = 0,
441 [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
442
443 [MESA_FORMAT_SIGNED_A8] = 0,
444 [MESA_FORMAT_SIGNED_L8] = 0,
445 [MESA_FORMAT_SIGNED_AL88] = 0,
446 [MESA_FORMAT_SIGNED_I8] = 0,
447 [MESA_FORMAT_SIGNED_A16] = 0,
448 [MESA_FORMAT_SIGNED_L16] = 0,
449 [MESA_FORMAT_SIGNED_AL1616] = 0,
450 [MESA_FORMAT_SIGNED_I16] = 0,
451
452 [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
453 [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
454
455 [MESA_FORMAT_Z32_FLOAT] = 0,
456 [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
457 };
458 assert(mesa_format < MESA_FORMAT_COUNT);
459 return table[mesa_format];
460 }
461
462 void
463 brw_init_surface_formats(struct brw_context *brw)
464 {
465 struct intel_context *intel = &brw->intel;
466 struct gl_context *ctx = &intel->ctx;
467 int gen;
468 gl_format format;
469
470 gen = intel->gen * 10;
471 if (intel->is_g4x)
472 gen += 5;
473
474 for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
475 uint32_t texture, render;
476 const struct surface_format_info *rinfo, *tinfo;
477 bool is_integer = _mesa_is_format_integer_color(format);
478
479 render = texture = brw_format_for_mesa_format(format);
480 tinfo = &surface_formats[texture];
481
482 /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
483 * it.
484 */
485 if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
486 continue;
487
488 if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
489 ctx->TextureFormatSupported[format] = true;
490
491 /* Re-map some render target formats to make them supported when they
492 * wouldn't be using their format for texturing.
493 */
494 switch (render) {
495 /* For these formats, we just need to read/write the first
496 * channel into R, which is to say that we just treat them as
497 * GL_RED.
498 */
499 case BRW_SURFACEFORMAT_I32_FLOAT:
500 case BRW_SURFACEFORMAT_L32_FLOAT:
501 render = BRW_SURFACEFORMAT_R32_FLOAT;
502 break;
503 case BRW_SURFACEFORMAT_I16_FLOAT:
504 case BRW_SURFACEFORMAT_L16_FLOAT:
505 render = BRW_SURFACEFORMAT_R16_FLOAT;
506 break;
507 case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
508 /* XRGB is handled as ARGB because the chips in this family
509 * cannot render to XRGB targets. This means that we have to
510 * mask writes to alpha (ala glColorMask) and reconfigure the
511 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
512 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
513 * used.
514 */
515 render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
516 break;
517 }
518
519 rinfo = &surface_formats[render];
520
521 /* Note that GL_EXT_texture_integer says that blending doesn't occur for
522 * integer, so we don't need hardware support for blending on it. Other
523 * than that, GL in general requires alpha blending for render targets,
524 * even though we don't support it for some formats.
525 *
526 * We don't currently support rendering to SNORM textures because some of
527 * the ARB_color_buffer_float clamping is broken for it
528 * (piglit arb_color_buffer_float-drawpixels GL_RGBA8_SNORM).
529 */
530 if (gen >= rinfo->render_target &&
531 (gen >= rinfo->alpha_blend || is_integer) &&
532 _mesa_get_format_datatype(format) != GL_SIGNED_NORMALIZED) {
533 brw->render_target_format[format] = render;
534 brw->format_supported_as_render_target[format] = true;
535 }
536 }
537
538 /* We will check this table for FBO completeness, but the surface format
539 * table above only covered color rendering.
540 */
541 brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
542 brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
543 brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
544 brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
545 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
546 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
547
548 /* We remap depth formats to a supported texturing format in
549 * translate_tex_format().
550 */
551 ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
552 ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
553 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
554 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
555 }
556
557 bool
558 brw_render_target_supported(struct intel_context *intel, gl_format format)
559 {
560 struct brw_context *brw = brw_context(&intel->ctx);
561 /* Not exactly true, as some of those formats are not renderable.
562 * But at least we know how to translate them.
563 */
564 return brw->format_supported_as_render_target[format];
565 }
566
567 GLuint
568 translate_tex_format(gl_format mesa_format,
569 GLenum internal_format,
570 GLenum depth_mode,
571 GLenum srgb_decode)
572 {
573 switch( mesa_format ) {
574
575 case MESA_FORMAT_Z16:
576 return BRW_SURFACEFORMAT_I16_UNORM;
577
578 case MESA_FORMAT_S8_Z24:
579 case MESA_FORMAT_X8_Z24:
580 return BRW_SURFACEFORMAT_I24X8_UNORM;
581
582 case MESA_FORMAT_Z32_FLOAT:
583 return BRW_SURFACEFORMAT_I32_FLOAT;
584
585 case MESA_FORMAT_Z32_FLOAT_X24S8:
586 return BRW_SURFACEFORMAT_R32G32_FLOAT;
587
588 case MESA_FORMAT_SARGB8:
589 case MESA_FORMAT_SLA8:
590 case MESA_FORMAT_SL8:
591 if (srgb_decode == GL_DECODE_EXT)
592 return brw_format_for_mesa_format(mesa_format);
593 else if (srgb_decode == GL_SKIP_DECODE_EXT)
594 return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
595
596 case MESA_FORMAT_RGBA8888_REV:
597 /* This format is not renderable? */
598 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
599
600 case MESA_FORMAT_RGBA_FLOAT32:
601 /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
602 * assertion below.
603 */
604 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
605
606 default:
607 assert(brw_format_for_mesa_format(mesa_format) != 0);
608 return brw_format_for_mesa_format(mesa_format);
609 }
610 }
611
612 static uint32_t
613 brw_get_surface_tiling_bits(uint32_t tiling)
614 {
615 switch (tiling) {
616 case I915_TILING_X:
617 return BRW_SURFACE_TILED;
618 case I915_TILING_Y:
619 return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
620 default:
621 return 0;
622 }
623 }
624
625 static void
626 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
627 {
628 struct brw_context *brw = brw_context(ctx);
629 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
630 struct intel_texture_object *intelObj = intel_texture_object(tObj);
631 struct intel_mipmap_tree *mt = intelObj->mt;
632 struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
633 struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
634 const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
635 uint32_t *surf;
636 int width, height, depth;
637
638 intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
639
640 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
641 6 * 4, 32, &brw->bind.surf_offset[surf_index]);
642
643 surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
644 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
645 BRW_SURFACE_CUBEFACE_ENABLES |
646 (translate_tex_format(mt->format,
647 firstImage->InternalFormat,
648 sampler->DepthMode,
649 sampler->sRGBDecode) <<
650 BRW_SURFACE_FORMAT_SHIFT));
651
652 surf[1] = intelObj->mt->region->bo->offset; /* reloc */
653
654 surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
655 (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
656 (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
657
658 surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
659 (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
660 ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
661 BRW_SURFACE_PITCH_SHIFT);
662
663 surf[4] = 0;
664
665 surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
666
667 /* Emit relocation to surface contents */
668 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
669 brw->bind.surf_offset[surf_index] + 4,
670 intelObj->mt->region->bo, 0,
671 I915_GEM_DOMAIN_SAMPLER, 0);
672 }
673
674 /**
675 * Create the constant buffer surface. Vertex/fragment shader constants will be
676 * read from this buffer with Data Port Read instructions/messages.
677 */
678 void
679 brw_create_constant_surface(struct brw_context *brw,
680 drm_intel_bo *bo,
681 int width,
682 uint32_t *out_offset)
683 {
684 struct intel_context *intel = &brw->intel;
685 const GLint w = width - 1;
686 uint32_t *surf;
687
688 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
689 6 * 4, 32, out_offset);
690
691 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
692 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
693 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
694
695 if (intel->gen >= 6)
696 surf[0] |= BRW_SURFACE_RC_READ_WRITE;
697
698 surf[1] = bo->offset; /* reloc */
699
700 surf[2] = (((w & 0x7f) - 1) << BRW_SURFACE_WIDTH_SHIFT |
701 (((w >> 7) & 0x1fff) - 1) << BRW_SURFACE_HEIGHT_SHIFT);
702
703 surf[3] = ((((w >> 20) & 0x7f) - 1) << BRW_SURFACE_DEPTH_SHIFT |
704 (width * 16 - 1) << BRW_SURFACE_PITCH_SHIFT);
705
706 surf[4] = 0;
707 surf[5] = 0;
708
709 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
710 * bspec ("Data Cache") says that the data cache does not exist as
711 * a separate cache and is just the sampler cache.
712 */
713 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
714 *out_offset + 4,
715 bo, 0,
716 I915_GEM_DOMAIN_SAMPLER, 0);
717 }
718
719 /**
720 * Set up a binding table entry for use by stream output logic (transform
721 * feedback).
722 *
723 * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
724 */
725 void
726 brw_update_sol_surface(struct brw_context *brw,
727 struct gl_buffer_object *buffer_obj,
728 uint32_t *out_offset, unsigned num_vector_components,
729 unsigned stride_dwords, unsigned offset_dwords)
730 {
731 drm_intel_bo *bo = intel_buffer_object(buffer_obj)->buffer;
732 uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
733 out_offset);
734 uint32_t pitch_minus_1 = 4*stride_dwords - 1;
735 uint32_t offset_bytes = 4 * offset_dwords;
736 size_t size_dwords = buffer_obj->Size / 4;
737 uint32_t buffer_size_minus_1, width, height, depth, surface_format;
738
739 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
740 * too big to map using a single binding table entry?
741 */
742 assert((size_dwords - offset_dwords) / stride_dwords
743 <= BRW_MAX_NUM_BUFFER_ENTRIES);
744
745 if (size_dwords > offset_dwords + num_vector_components) {
746 /* There is room for at least 1 transform feedback output in the buffer.
747 * Compute the number of additional transform feedback outputs the
748 * buffer has room for.
749 */
750 buffer_size_minus_1 =
751 (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
752 } else {
753 /* There isn't even room for a single transform feedback output in the
754 * buffer. We can't configure the binding table entry to prevent output
755 * entirely; we'll have to rely on the geometry shader to detect
756 * overflow. But to minimize the damage in case of a bug, set up the
757 * binding table entry to just allow a single output.
758 */
759 buffer_size_minus_1 = 0;
760 }
761 width = buffer_size_minus_1 & 0x7f;
762 height = (buffer_size_minus_1 & 0xfff80) >> 7;
763 depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
764
765 switch (num_vector_components) {
766 case 1:
767 surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
768 break;
769 case 2:
770 surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
771 break;
772 case 3:
773 surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
774 break;
775 case 4:
776 surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
777 break;
778 default:
779 assert(!"Invalid vector size for transform feedback output");
780 surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
781 break;
782 }
783
784 surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
785 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
786 surface_format << BRW_SURFACE_FORMAT_SHIFT |
787 BRW_SURFACE_RC_READ_WRITE;
788 surf[1] = bo->offset + offset_bytes; /* reloc */
789 surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
790 height << BRW_SURFACE_HEIGHT_SHIFT);
791 surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
792 pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
793 surf[4] = 0;
794 surf[5] = 0;
795
796 /* Emit relocation to surface contents. */
797 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
798 *out_offset + 4,
799 bo, offset_bytes,
800 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
801 }
802
803 /* Creates a new WM constant buffer reflecting the current fragment program's
804 * constants, if needed by the fragment program.
805 *
806 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
807 * state atom.
808 */
809 static void
810 brw_upload_wm_pull_constants(struct brw_context *brw)
811 {
812 struct gl_context *ctx = &brw->intel.ctx;
813 struct intel_context *intel = &brw->intel;
814 /* BRW_NEW_FRAGMENT_PROGRAM */
815 struct brw_fragment_program *fp =
816 (struct brw_fragment_program *) brw->fragment_program;
817 struct gl_program_parameter_list *params = fp->program.Base.Parameters;
818 const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
819 const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
820 float *constants;
821 unsigned int i;
822
823 _mesa_load_state_parameters(ctx, params);
824
825 /* CACHE_NEW_WM_PROG */
826 if (brw->wm.prog_data->nr_pull_params == 0) {
827 if (brw->wm.const_bo) {
828 drm_intel_bo_unreference(brw->wm.const_bo);
829 brw->wm.const_bo = NULL;
830 brw->bind.surf_offset[surf_index] = 0;
831 brw->state.dirty.brw |= BRW_NEW_SURFACES;
832 }
833 return;
834 }
835
836 drm_intel_bo_unreference(brw->wm.const_bo);
837 brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
838 size, 64);
839
840 /* _NEW_PROGRAM_CONSTANTS */
841 drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
842 constants = brw->wm.const_bo->virtual;
843 for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
844 constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
845 brw->wm.prog_data->pull_param[i]);
846 }
847 drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
848
849 intel->vtbl.create_constant_surface(brw, brw->wm.const_bo,
850 params->NumParameters,
851 &brw->bind.surf_offset[surf_index]);
852
853 brw->state.dirty.brw |= BRW_NEW_SURFACES;
854 }
855
856 const struct brw_tracked_state brw_wm_pull_constants = {
857 .dirty = {
858 .mesa = (_NEW_PROGRAM_CONSTANTS),
859 .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
860 .cache = CACHE_NEW_WM_PROG,
861 },
862 .emit = brw_upload_wm_pull_constants,
863 };
864
865 static void
866 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
867 {
868 struct intel_context *intel = &brw->intel;
869 uint32_t *surf;
870
871 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
872 6 * 4, 32, &brw->bind.surf_offset[unit]);
873
874 surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
875 BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
876 if (intel->gen < 6) {
877 surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
878 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
879 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
880 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
881 }
882 surf[1] = 0;
883 surf[2] = 0;
884 surf[3] = 0;
885 surf[4] = 0;
886 surf[5] = 0;
887 }
888
889 /**
890 * Sets up a surface state structure to point at the given region.
891 * While it is only used for the front/back buffer currently, it should be
892 * usable for further buffers when doing ARB_draw_buffer support.
893 */
894 static void
895 brw_update_renderbuffer_surface(struct brw_context *brw,
896 struct gl_renderbuffer *rb,
897 unsigned int unit)
898 {
899 struct intel_context *intel = &brw->intel;
900 struct gl_context *ctx = &intel->ctx;
901 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
902 struct intel_mipmap_tree *mt = irb->mt;
903 struct intel_region *region = irb->mt->region;
904 uint32_t *surf;
905 uint32_t tile_x, tile_y;
906 uint32_t format = 0;
907
908 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
909 6 * 4, 32, &brw->bind.surf_offset[unit]);
910
911 switch (irb->Base.Format) {
912 case MESA_FORMAT_SARGB8:
913 /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
914 surfaces to the blend/update as sRGB */
915 if (ctx->Color.sRGBEnabled)
916 format = brw_format_for_mesa_format(irb->Base.Format);
917 else
918 format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
919 break;
920 default:
921 format = brw->render_target_format[irb->Base.Format];
922 if (unlikely(!brw->format_supported_as_render_target[irb->Base.Format])) {
923 _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
924 __FUNCTION__, _mesa_get_format_name(irb->Base.Format));
925 }
926 break;
927 }
928
929 surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
930 format << BRW_SURFACE_FORMAT_SHIFT);
931
932 /* reloc */
933 surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
934 region->bo->offset);
935
936 surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
937 (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
938
939 surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
940 ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
941
942 surf[4] = 0;
943
944 assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
945 /* Note that the low bits of these fields are missing, so
946 * there's the possibility of getting in trouble.
947 */
948 assert(tile_x % 4 == 0);
949 assert(tile_y % 2 == 0);
950 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
951 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
952 (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
953
954 if (intel->gen < 6) {
955 /* _NEW_COLOR */
956 if (!ctx->Color.ColorLogicOpEnabled &&
957 (ctx->Color.BlendEnabled & (1 << unit)))
958 surf[0] |= BRW_SURFACE_BLEND_ENABLED;
959
960 if (!ctx->Color.ColorMask[unit][0])
961 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
962 if (!ctx->Color.ColorMask[unit][1])
963 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
964 if (!ctx->Color.ColorMask[unit][2])
965 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
966
967 /* As mentioned above, disable writes to the alpha component when the
968 * renderbuffer is XRGB.
969 */
970 if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
971 !ctx->Color.ColorMask[unit][3]) {
972 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
973 }
974 }
975
976 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
977 brw->bind.surf_offset[unit] + 4,
978 region->bo,
979 surf[1] - region->bo->offset,
980 I915_GEM_DOMAIN_RENDER,
981 I915_GEM_DOMAIN_RENDER);
982 }
983
984 /**
985 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
986 */
987 static void
988 brw_update_renderbuffer_surfaces(struct brw_context *brw)
989 {
990 struct intel_context *intel = &brw->intel;
991 struct gl_context *ctx = &brw->intel.ctx;
992 GLuint i;
993
994 /* _NEW_BUFFERS | _NEW_COLOR */
995 /* Update surfaces for drawing buffers */
996 if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
997 for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
998 if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
999 intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1000 } else {
1001 intel->vtbl.update_null_renderbuffer_surface(brw, i);
1002 }
1003 }
1004 } else {
1005 intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1006 }
1007 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1008 }
1009
1010 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1011 .dirty = {
1012 .mesa = (_NEW_COLOR |
1013 _NEW_BUFFERS),
1014 .brw = BRW_NEW_BATCH,
1015 .cache = 0
1016 },
1017 .emit = brw_update_renderbuffer_surfaces,
1018 };
1019
1020 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1021 .dirty = {
1022 .mesa = _NEW_BUFFERS,
1023 .brw = BRW_NEW_BATCH,
1024 .cache = 0
1025 },
1026 .emit = brw_update_renderbuffer_surfaces,
1027 };
1028
1029 /**
1030 * Construct SURFACE_STATE objects for enabled textures.
1031 */
1032 static void
1033 brw_update_texture_surfaces(struct brw_context *brw)
1034 {
1035 struct gl_context *ctx = &brw->intel.ctx;
1036
1037 for (unsigned i = 0; i < BRW_MAX_TEX_UNIT; i++) {
1038 const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
1039 const GLuint surf = SURF_INDEX_TEXTURE(i);
1040
1041 /* _NEW_TEXTURE */
1042 if (texUnit->_ReallyEnabled) {
1043 brw->intel.vtbl.update_texture_surface(ctx, i);
1044 } else {
1045 brw->bind.surf_offset[surf] = 0;
1046 }
1047 }
1048
1049 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1050 }
1051
1052 const struct brw_tracked_state brw_texture_surfaces = {
1053 .dirty = {
1054 .mesa = _NEW_TEXTURE,
1055 .brw = BRW_NEW_BATCH,
1056 .cache = 0
1057 },
1058 .emit = brw_update_texture_surfaces,
1059 };
1060
1061 /**
1062 * Constructs the binding table for the WM surface state, which maps unit
1063 * numbers to surface state objects.
1064 */
1065 static void
1066 brw_upload_binding_table(struct brw_context *brw)
1067 {
1068 uint32_t *bind;
1069 int i;
1070
1071 /* Might want to calculate nr_surfaces first, to avoid taking up so much
1072 * space for the binding table.
1073 */
1074 bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1075 sizeof(uint32_t) * BRW_MAX_SURFACES,
1076 32, &brw->bind.bo_offset);
1077
1078 /* BRW_NEW_SURFACES and BRW_NEW_VS_CONSTBUF */
1079 for (i = 0; i < BRW_MAX_SURFACES; i++) {
1080 bind[i] = brw->bind.surf_offset[i];
1081 }
1082
1083 brw->state.dirty.brw |= BRW_NEW_VS_BINDING_TABLE;
1084 brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1085 }
1086
1087 const struct brw_tracked_state brw_binding_table = {
1088 .dirty = {
1089 .mesa = 0,
1090 .brw = (BRW_NEW_BATCH |
1091 BRW_NEW_VS_CONSTBUF |
1092 BRW_NEW_SURFACES),
1093 .cache = 0
1094 },
1095 .emit = brw_upload_binding_table,
1096 };
1097
1098 void
1099 gen4_init_vtable_surface_functions(struct brw_context *brw)
1100 {
1101 struct intel_context *intel = &brw->intel;
1102
1103 intel->vtbl.update_texture_surface = brw_update_texture_surface;
1104 intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1105 intel->vtbl.update_null_renderbuffer_surface =
1106 brw_update_null_renderbuffer_surface;
1107 intel->vtbl.create_constant_surface = brw_create_constant_surface;
1108 }