2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "main/context.h"
34 #include "main/blend.h"
35 #include "main/mtypes.h"
36 #include "main/samplerobj.h"
37 #include "program/prog_parameter.h"
39 #include "intel_mipmap_tree.h"
40 #include "intel_batchbuffer.h"
41 #include "intel_tex.h"
42 #include "intel_fbo.h"
43 #include "intel_buffer_objects.h"
45 #include "brw_context.h"
46 #include "brw_state.h"
47 #include "brw_defines.h"
51 translate_tex_target(GLenum target
)
55 case GL_TEXTURE_1D_ARRAY_EXT
:
56 return BRW_SURFACE_1D
;
58 case GL_TEXTURE_RECTANGLE_NV
:
59 return BRW_SURFACE_2D
;
62 case GL_TEXTURE_2D_ARRAY_EXT
:
63 case GL_TEXTURE_EXTERNAL_OES
:
64 case GL_TEXTURE_2D_MULTISAMPLE
:
65 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
66 return BRW_SURFACE_2D
;
69 return BRW_SURFACE_3D
;
71 case GL_TEXTURE_CUBE_MAP
:
72 case GL_TEXTURE_CUBE_MAP_ARRAY
:
73 return BRW_SURFACE_CUBE
;
82 brw_get_surface_tiling_bits(uint32_t tiling
)
86 return BRW_SURFACE_TILED
;
88 return BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
;
96 brw_get_surface_num_multisamples(unsigned num_samples
)
99 return BRW_SURFACE_MULTISAMPLECOUNT_4
;
101 return BRW_SURFACE_MULTISAMPLECOUNT_1
;
106 * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
110 brw_get_texture_swizzle(const struct gl_context
*ctx
,
111 const struct gl_texture_object
*t
)
113 const struct gl_texture_image
*img
= t
->Image
[0][t
->BaseLevel
];
115 int swizzles
[SWIZZLE_NIL
+ 1] = {
125 if (img
->_BaseFormat
== GL_DEPTH_COMPONENT
||
126 img
->_BaseFormat
== GL_DEPTH_STENCIL
) {
127 GLenum depth_mode
= t
->DepthMode
;
129 /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
130 * with depth component data specified with a sized internal format.
131 * Otherwise, it's left at the old default, GL_LUMINANCE.
133 if (_mesa_is_gles3(ctx
) &&
134 img
->InternalFormat
!= GL_DEPTH_COMPONENT
&&
135 img
->InternalFormat
!= GL_DEPTH_STENCIL
) {
139 switch (depth_mode
) {
141 swizzles
[0] = SWIZZLE_ZERO
;
142 swizzles
[1] = SWIZZLE_ZERO
;
143 swizzles
[2] = SWIZZLE_ZERO
;
144 swizzles
[3] = SWIZZLE_X
;
147 swizzles
[0] = SWIZZLE_X
;
148 swizzles
[1] = SWIZZLE_X
;
149 swizzles
[2] = SWIZZLE_X
;
150 swizzles
[3] = SWIZZLE_ONE
;
153 swizzles
[0] = SWIZZLE_X
;
154 swizzles
[1] = SWIZZLE_X
;
155 swizzles
[2] = SWIZZLE_X
;
156 swizzles
[3] = SWIZZLE_X
;
159 swizzles
[0] = SWIZZLE_X
;
160 swizzles
[1] = SWIZZLE_ZERO
;
161 swizzles
[2] = SWIZZLE_ZERO
;
162 swizzles
[3] = SWIZZLE_ONE
;
167 /* If the texture's format is alpha-only, force R, G, and B to
168 * 0.0. Similarly, if the texture's format has no alpha channel,
169 * force the alpha value read to 1.0. This allows for the
170 * implementation to use an RGBA texture for any of these formats
171 * without leaking any unexpected values.
173 switch (img
->_BaseFormat
) {
175 swizzles
[0] = SWIZZLE_ZERO
;
176 swizzles
[1] = SWIZZLE_ZERO
;
177 swizzles
[2] = SWIZZLE_ZERO
;
182 if (_mesa_get_format_bits(img
->TexFormat
, GL_ALPHA_BITS
) > 0)
183 swizzles
[3] = SWIZZLE_ONE
;
187 return MAKE_SWIZZLE4(swizzles
[GET_SWZ(t
->_Swizzle
, 0)],
188 swizzles
[GET_SWZ(t
->_Swizzle
, 1)],
189 swizzles
[GET_SWZ(t
->_Swizzle
, 2)],
190 swizzles
[GET_SWZ(t
->_Swizzle
, 3)]);
194 gen4_emit_buffer_surface_state(struct brw_context
*brw
,
195 uint32_t *out_offset
,
197 unsigned buffer_offset
,
198 unsigned surface_format
,
199 unsigned buffer_size
,
204 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
205 6 * 4, 32, out_offset
);
206 memset(surf
, 0, 6 * 4);
208 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
209 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
210 (brw
->gen
>= 6 ? BRW_SURFACE_RC_READ_WRITE
: 0);
211 surf
[1] = (bo
? bo
->offset64
: 0) + buffer_offset
; /* reloc */
212 surf
[2] = (buffer_size
& 0x7f) << BRW_SURFACE_WIDTH_SHIFT
|
213 ((buffer_size
>> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT
;
214 surf
[3] = ((buffer_size
>> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT
|
215 (pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
;
217 /* Emit relocation to surface contents. The 965 PRM, Volume 4, section
218 * 5.1.2 "Data Cache" says: "the data cache does not exist as a separate
219 * physical cache. It is mapped in hardware to the sampler cache."
222 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *out_offset
+ 4,
224 I915_GEM_DOMAIN_SAMPLER
,
225 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
230 brw_update_buffer_texture_surface(struct gl_context
*ctx
,
232 uint32_t *surf_offset
)
234 struct brw_context
*brw
= brw_context(ctx
);
235 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
236 struct intel_buffer_object
*intel_obj
=
237 intel_buffer_object(tObj
->BufferObject
);
238 uint32_t size
= tObj
->BufferSize
;
239 drm_intel_bo
*bo
= NULL
;
240 mesa_format format
= tObj
->_BufferObjectFormat
;
241 uint32_t brw_format
= brw_format_for_mesa_format(format
);
242 int texel_size
= _mesa_get_format_bytes(format
);
245 size
= MIN2(size
, intel_obj
->Base
.Size
);
246 bo
= intel_bufferobj_buffer(brw
, intel_obj
, tObj
->BufferOffset
, size
);
249 if (brw_format
== 0 && format
!= MESA_FORMAT_RGBA_FLOAT32
) {
250 _mesa_problem(NULL
, "bad format %s for texture buffer\n",
251 _mesa_get_format_name(format
));
254 brw
->vtbl
.emit_buffer_surface_state(brw
, surf_offset
, bo
,
264 brw_update_texture_surface(struct gl_context
*ctx
,
266 uint32_t *surf_offset
,
269 struct brw_context
*brw
= brw_context(ctx
);
270 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
271 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
272 struct intel_mipmap_tree
*mt
= intelObj
->mt
;
273 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
276 /* BRW_NEW_UNIFORM_BUFFER */
277 if (tObj
->Target
== GL_TEXTURE_BUFFER
) {
278 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
282 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
283 6 * 4, 32, surf_offset
);
285 uint32_t tex_format
= translate_tex_format(brw
, mt
->format
,
286 sampler
->sRGBDecode
);
289 /* Sandybridge's gather4 message is broken for integer formats.
290 * To work around this, we pretend the surface is UNORM for
291 * 8 or 16-bit formats, and emit shader instructions to recover
292 * the real INT/UINT value. For 32-bit formats, we pretend
293 * the surface is FLOAT, and simply reinterpret the resulting
296 switch (tex_format
) {
297 case BRW_SURFACEFORMAT_R8_SINT
:
298 case BRW_SURFACEFORMAT_R8_UINT
:
299 tex_format
= BRW_SURFACEFORMAT_R8_UNORM
;
302 case BRW_SURFACEFORMAT_R16_SINT
:
303 case BRW_SURFACEFORMAT_R16_UINT
:
304 tex_format
= BRW_SURFACEFORMAT_R16_UNORM
;
307 case BRW_SURFACEFORMAT_R32_SINT
:
308 case BRW_SURFACEFORMAT_R32_UINT
:
309 tex_format
= BRW_SURFACEFORMAT_R32_FLOAT
;
317 surf
[0] = (translate_tex_target(tObj
->Target
) << BRW_SURFACE_TYPE_SHIFT
|
318 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
319 BRW_SURFACE_CUBEFACE_ENABLES
|
320 tex_format
<< BRW_SURFACE_FORMAT_SHIFT
);
322 surf
[1] = intelObj
->mt
->region
->bo
->offset64
+ intelObj
->mt
->offset
; /* reloc */
324 surf
[2] = ((intelObj
->_MaxLevel
- tObj
->BaseLevel
) << BRW_SURFACE_LOD_SHIFT
|
325 (mt
->logical_width0
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
326 (mt
->logical_height0
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
328 surf
[3] = (brw_get_surface_tiling_bits(intelObj
->mt
->region
->tiling
) |
329 (mt
->logical_depth0
- 1) << BRW_SURFACE_DEPTH_SHIFT
|
330 (intelObj
->mt
->region
->pitch
- 1) <<
331 BRW_SURFACE_PITCH_SHIFT
);
333 surf
[4] = (brw_get_surface_num_multisamples(intelObj
->mt
->num_samples
) |
334 SET_FIELD(tObj
->BaseLevel
- mt
->first_level
, BRW_SURFACE_MIN_LOD
));
336 surf
[5] = mt
->align_h
== 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0;
338 /* Emit relocation to surface contents */
339 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
341 intelObj
->mt
->region
->bo
,
342 surf
[1] - intelObj
->mt
->region
->bo
->offset64
,
343 I915_GEM_DOMAIN_SAMPLER
, 0);
347 * Create the constant buffer surface. Vertex/fragment shader constants will be
348 * read from this buffer with Data Port Read instructions/messages.
351 brw_create_constant_surface(struct brw_context
*brw
,
355 uint32_t *out_offset
,
358 uint32_t stride
= dword_pitch
? 4 : 16;
359 uint32_t elements
= ALIGN(size
, stride
) / stride
;
361 brw
->vtbl
.emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
362 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
,
363 elements
, stride
, 0, false);
367 * Set up a binding table entry for use by stream output logic (transform
370 * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
373 brw_update_sol_surface(struct brw_context
*brw
,
374 struct gl_buffer_object
*buffer_obj
,
375 uint32_t *out_offset
, unsigned num_vector_components
,
376 unsigned stride_dwords
, unsigned offset_dwords
)
378 struct intel_buffer_object
*intel_bo
= intel_buffer_object(buffer_obj
);
379 uint32_t offset_bytes
= 4 * offset_dwords
;
380 drm_intel_bo
*bo
= intel_bufferobj_buffer(brw
, intel_bo
,
382 buffer_obj
->Size
- offset_bytes
);
383 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
385 uint32_t pitch_minus_1
= 4*stride_dwords
- 1;
386 size_t size_dwords
= buffer_obj
->Size
/ 4;
387 uint32_t buffer_size_minus_1
, width
, height
, depth
, surface_format
;
389 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
390 * too big to map using a single binding table entry?
392 assert((size_dwords
- offset_dwords
) / stride_dwords
393 <= BRW_MAX_NUM_BUFFER_ENTRIES
);
395 if (size_dwords
> offset_dwords
+ num_vector_components
) {
396 /* There is room for at least 1 transform feedback output in the buffer.
397 * Compute the number of additional transform feedback outputs the
398 * buffer has room for.
400 buffer_size_minus_1
=
401 (size_dwords
- offset_dwords
- num_vector_components
) / stride_dwords
;
403 /* There isn't even room for a single transform feedback output in the
404 * buffer. We can't configure the binding table entry to prevent output
405 * entirely; we'll have to rely on the geometry shader to detect
406 * overflow. But to minimize the damage in case of a bug, set up the
407 * binding table entry to just allow a single output.
409 buffer_size_minus_1
= 0;
411 width
= buffer_size_minus_1
& 0x7f;
412 height
= (buffer_size_minus_1
& 0xfff80) >> 7;
413 depth
= (buffer_size_minus_1
& 0x7f00000) >> 20;
415 switch (num_vector_components
) {
417 surface_format
= BRW_SURFACEFORMAT_R32_FLOAT
;
420 surface_format
= BRW_SURFACEFORMAT_R32G32_FLOAT
;
423 surface_format
= BRW_SURFACEFORMAT_R32G32B32_FLOAT
;
426 surface_format
= BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
429 assert(!"Invalid vector size for transform feedback output");
430 surface_format
= BRW_SURFACEFORMAT_R32_FLOAT
;
434 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
435 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
436 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
437 BRW_SURFACE_RC_READ_WRITE
;
438 surf
[1] = bo
->offset64
+ offset_bytes
; /* reloc */
439 surf
[2] = (width
<< BRW_SURFACE_WIDTH_SHIFT
|
440 height
<< BRW_SURFACE_HEIGHT_SHIFT
);
441 surf
[3] = (depth
<< BRW_SURFACE_DEPTH_SHIFT
|
442 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
446 /* Emit relocation to surface contents. */
447 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
450 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
453 /* Creates a new WM constant buffer reflecting the current fragment program's
454 * constants, if needed by the fragment program.
456 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
460 brw_upload_wm_pull_constants(struct brw_context
*brw
)
462 struct gl_context
*ctx
= &brw
->ctx
;
463 /* BRW_NEW_FRAGMENT_PROGRAM */
464 struct brw_fragment_program
*fp
=
465 (struct brw_fragment_program
*) brw
->fragment_program
;
466 struct gl_program_parameter_list
*params
= fp
->program
.Base
.Parameters
;
467 const int size
= brw
->wm
.prog_data
->base
.nr_pull_params
* sizeof(float);
468 const int surf_index
=
469 brw
->wm
.prog_data
->base
.binding_table
.pull_constants_start
;
473 _mesa_load_state_parameters(ctx
, params
);
475 /* CACHE_NEW_WM_PROG */
476 if (brw
->wm
.prog_data
->base
.nr_pull_params
== 0) {
477 if (brw
->wm
.base
.const_bo
) {
478 drm_intel_bo_unreference(brw
->wm
.base
.const_bo
);
479 brw
->wm
.base
.const_bo
= NULL
;
480 brw
->wm
.base
.surf_offset
[surf_index
] = 0;
481 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
486 drm_intel_bo_unreference(brw
->wm
.base
.const_bo
);
487 brw
->wm
.base
.const_bo
= drm_intel_bo_alloc(brw
->bufmgr
, "WM const bo",
490 /* _NEW_PROGRAM_CONSTANTS */
491 drm_intel_gem_bo_map_gtt(brw
->wm
.base
.const_bo
);
492 constants
= brw
->wm
.base
.const_bo
->virtual;
493 for (i
= 0; i
< brw
->wm
.prog_data
->base
.nr_pull_params
; i
++) {
494 constants
[i
] = *brw
->wm
.prog_data
->base
.pull_param
[i
];
496 drm_intel_gem_bo_unmap_gtt(brw
->wm
.base
.const_bo
);
498 brw_create_constant_surface(brw
, brw
->wm
.base
.const_bo
, 0, size
,
499 &brw
->wm
.base
.surf_offset
[surf_index
],
502 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
505 const struct brw_tracked_state brw_wm_pull_constants
= {
507 .mesa
= (_NEW_PROGRAM_CONSTANTS
),
508 .brw
= (BRW_NEW_BATCH
| BRW_NEW_FRAGMENT_PROGRAM
),
509 .cache
= CACHE_NEW_WM_PROG
,
511 .emit
= brw_upload_wm_pull_constants
,
515 brw_update_null_renderbuffer_surface(struct brw_context
*brw
, unsigned int unit
)
517 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
520 * A null surface will be used in instances where an actual surface is
521 * not bound. When a write message is generated to a null surface, no
522 * actual surface is written to. When a read message (including any
523 * sampling engine message) is generated to a null surface, the result
524 * is all zeros. Note that a null surface type is allowed to be used
525 * with all messages, even if it is not specificially indicated as
526 * supported. All of the remaining fields in surface state are ignored
527 * for null surfaces, with the following exceptions:
529 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
530 * depth buffer’s corresponding state for all render target surfaces,
533 * - Surface Format must be R8G8B8A8_UNORM.
535 struct gl_context
*ctx
= &brw
->ctx
;
537 unsigned surface_type
= BRW_SURFACE_NULL
;
538 drm_intel_bo
*bo
= NULL
;
539 unsigned pitch_minus_1
= 0;
540 uint32_t multisampling_state
= 0;
541 uint32_t surf_index
=
542 brw
->wm
.prog_data
->binding_table
.render_target_start
+ unit
;
545 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
547 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
548 &brw
->wm
.base
.surf_offset
[surf_index
]);
550 if (fb
->Visual
.samples
> 1) {
551 /* On Gen6, null render targets seem to cause GPU hangs when
552 * multisampling. So work around this problem by rendering into dummy
555 * To decrease the amount of memory needed by the workaround buffer, we
556 * set its pitch to 128 bytes (the width of a Y tile). This means that
557 * the amount of memory needed for the workaround buffer is
558 * (width_in_tiles + height_in_tiles - 1) tiles.
560 * Note that since the workaround buffer will be interpreted by the
561 * hardware as an interleaved multisampled buffer, we need to compute
562 * width_in_tiles and height_in_tiles by dividing the width and height
563 * by 16 rather than the normal Y-tile size of 32.
565 unsigned width_in_tiles
= ALIGN(fb
->Width
, 16) / 16;
566 unsigned height_in_tiles
= ALIGN(fb
->Height
, 16) / 16;
567 unsigned size_needed
= (width_in_tiles
+ height_in_tiles
- 1) * 4096;
568 brw_get_scratch_bo(brw
, &brw
->wm
.multisampled_null_render_target_bo
,
570 bo
= brw
->wm
.multisampled_null_render_target_bo
;
571 surface_type
= BRW_SURFACE_2D
;
573 multisampling_state
=
574 brw_get_surface_num_multisamples(fb
->Visual
.samples
);
577 surf
[0] = (surface_type
<< BRW_SURFACE_TYPE_SHIFT
|
578 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
);
580 surf
[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
|
581 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
|
582 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
|
583 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
);
585 surf
[1] = bo
? bo
->offset64
: 0;
586 surf
[2] = ((fb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
587 (fb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
589 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
592 * If Surface Type is SURFTYPE_NULL, this field must be TRUE
594 surf
[3] = (BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
|
595 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
596 surf
[4] = multisampling_state
;
600 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
601 brw
->wm
.base
.surf_offset
[surf_index
] + 4,
603 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
608 * Sets up a surface state structure to point at the given region.
609 * While it is only used for the front/back buffer currently, it should be
610 * usable for further buffers when doing ARB_draw_buffer support.
613 brw_update_renderbuffer_surface(struct brw_context
*brw
,
614 struct gl_renderbuffer
*rb
,
618 struct gl_context
*ctx
= &brw
->ctx
;
619 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
620 struct intel_mipmap_tree
*mt
= irb
->mt
;
621 struct intel_region
*region
;
623 uint32_t tile_x
, tile_y
;
626 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
627 uint32_t surf_index
=
628 brw
->wm
.prog_data
->binding_table
.render_target_start
+ unit
;
632 if (rb
->TexImage
&& !brw
->has_surface_tile_offset
) {
633 intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
);
635 if (tile_x
!= 0 || tile_y
!= 0) {
636 /* Original gen4 hardware couldn't draw to a non-tile-aligned
637 * destination in a miptree unless you actually setup your renderbuffer
638 * as a miptree and used the fragile lod/array_index/etc. controls to
639 * select the image. So, instead, we just make a new single-level
640 * miptree and render into that.
642 intel_renderbuffer_move_to_temp(brw
, irb
, false);
647 intel_miptree_used_for_rendering(irb
->mt
);
649 region
= irb
->mt
->region
;
651 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
652 &brw
->wm
.base
.surf_offset
[surf_index
]);
654 format
= brw
->render_target_format
[rb_format
];
655 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
])) {
656 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
657 __FUNCTION__
, _mesa_get_format_name(rb_format
));
660 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
661 format
<< BRW_SURFACE_FORMAT_SHIFT
);
664 surf
[1] = (intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
) +
665 region
->bo
->offset64
);
667 surf
[2] = ((rb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
668 (rb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
670 surf
[3] = (brw_get_surface_tiling_bits(region
->tiling
) |
671 (region
->pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
);
673 surf
[4] = brw_get_surface_num_multisamples(mt
->num_samples
);
675 assert(brw
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
676 /* Note that the low bits of these fields are missing, so
677 * there's the possibility of getting in trouble.
679 assert(tile_x
% 4 == 0);
680 assert(tile_y
% 2 == 0);
681 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
682 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
683 (mt
->align_h
== 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
687 if (!ctx
->Color
.ColorLogicOpEnabled
&&
688 (ctx
->Color
.BlendEnabled
& (1 << unit
)))
689 surf
[0] |= BRW_SURFACE_BLEND_ENABLED
;
691 if (!ctx
->Color
.ColorMask
[unit
][0])
692 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
;
693 if (!ctx
->Color
.ColorMask
[unit
][1])
694 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
;
695 if (!ctx
->Color
.ColorMask
[unit
][2])
696 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
;
698 /* As mentioned above, disable writes to the alpha component when the
699 * renderbuffer is XRGB.
701 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0 ||
702 !ctx
->Color
.ColorMask
[unit
][3]) {
703 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
;
707 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
708 brw
->wm
.base
.surf_offset
[surf_index
] + 4,
710 surf
[1] - region
->bo
->offset64
,
711 I915_GEM_DOMAIN_RENDER
,
712 I915_GEM_DOMAIN_RENDER
);
716 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
719 brw_update_renderbuffer_surfaces(struct brw_context
*brw
)
721 struct gl_context
*ctx
= &brw
->ctx
;
724 /* _NEW_BUFFERS | _NEW_COLOR */
725 /* Update surfaces for drawing buffers */
726 if (ctx
->DrawBuffer
->_NumColorDrawBuffers
>= 1) {
727 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
728 if (intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
])) {
729 brw
->vtbl
.update_renderbuffer_surface(brw
, ctx
->DrawBuffer
->_ColorDrawBuffers
[i
],
730 ctx
->DrawBuffer
->MaxNumLayers
> 0, i
);
732 brw
->vtbl
.update_null_renderbuffer_surface(brw
, i
);
736 brw
->vtbl
.update_null_renderbuffer_surface(brw
, 0);
738 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
741 const struct brw_tracked_state brw_renderbuffer_surfaces
= {
743 .mesa
= (_NEW_COLOR
|
745 .brw
= BRW_NEW_BATCH
,
748 .emit
= brw_update_renderbuffer_surfaces
,
751 const struct brw_tracked_state gen6_renderbuffer_surfaces
= {
753 .mesa
= _NEW_BUFFERS
,
754 .brw
= BRW_NEW_BATCH
,
757 .emit
= brw_update_renderbuffer_surfaces
,
762 update_stage_texture_surfaces(struct brw_context
*brw
,
763 const struct gl_program
*prog
,
764 struct brw_stage_state
*stage_state
,
770 struct gl_context
*ctx
= &brw
->ctx
;
772 uint32_t *surf_offset
= stage_state
->surf_offset
;
774 surf_offset
+= stage_state
->prog_data
->binding_table
.gather_texture_start
;
776 surf_offset
+= stage_state
->prog_data
->binding_table
.texture_start
;
778 unsigned num_samplers
= _mesa_fls(prog
->SamplersUsed
);
779 for (unsigned s
= 0; s
< num_samplers
; s
++) {
782 if (prog
->SamplersUsed
& (1 << s
)) {
783 const unsigned unit
= prog
->SamplerUnits
[s
];
786 if (ctx
->Texture
.Unit
[unit
]._ReallyEnabled
) {
787 brw
->vtbl
.update_texture_surface(ctx
, unit
, surf_offset
+ s
, for_gather
);
795 * Construct SURFACE_STATE objects for enabled textures.
798 brw_update_texture_surfaces(struct brw_context
*brw
)
800 /* BRW_NEW_VERTEX_PROGRAM */
801 struct gl_program
*vs
= (struct gl_program
*) brw
->vertex_program
;
803 /* BRW_NEW_GEOMETRY_PROGRAM */
804 struct gl_program
*gs
= (struct gl_program
*) brw
->geometry_program
;
806 /* BRW_NEW_FRAGMENT_PROGRAM */
807 struct gl_program
*fs
= (struct gl_program
*) brw
->fragment_program
;
810 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, false);
811 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, false);
812 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false);
814 /* emit alternate set of surface state for gather. this
815 * allows the surface format to be overriden for only the
816 * gather4 messages. */
817 if (vs
&& vs
->UsesGather
)
818 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, true);
819 if (gs
&& gs
->UsesGather
)
820 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, true);
821 if (fs
&& fs
->UsesGather
)
822 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, true);
824 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
827 const struct brw_tracked_state brw_texture_surfaces
= {
829 .mesa
= _NEW_TEXTURE
,
830 .brw
= BRW_NEW_BATCH
|
831 BRW_NEW_UNIFORM_BUFFER
|
832 BRW_NEW_VERTEX_PROGRAM
|
833 BRW_NEW_GEOMETRY_PROGRAM
|
834 BRW_NEW_FRAGMENT_PROGRAM
,
837 .emit
= brw_update_texture_surfaces
,
841 brw_upload_ubo_surfaces(struct brw_context
*brw
,
842 struct gl_shader
*shader
,
843 struct brw_stage_state
*stage_state
,
844 struct brw_stage_prog_data
*prog_data
)
846 struct gl_context
*ctx
= &brw
->ctx
;
851 uint32_t *surf_offsets
=
852 &stage_state
->surf_offset
[prog_data
->binding_table
.ubo_start
];
854 for (int i
= 0; i
< shader
->NumUniformBlocks
; i
++) {
855 struct gl_uniform_buffer_binding
*binding
;
856 struct intel_buffer_object
*intel_bo
;
858 binding
= &ctx
->UniformBufferBindings
[shader
->UniformBlocks
[i
].Binding
];
859 intel_bo
= intel_buffer_object(binding
->BufferObject
);
861 intel_bufferobj_buffer(brw
, intel_bo
,
863 binding
->BufferObject
->Size
- binding
->Offset
);
865 /* Because behavior for referencing outside of the binding's size in the
866 * glBindBufferRange case is undefined, we can just bind the whole buffer
867 * glBindBufferBase wants and be a correct implementation.
869 brw_create_constant_surface(brw
, bo
, binding
->Offset
,
870 bo
->size
- binding
->Offset
,
872 shader
->Stage
== MESA_SHADER_FRAGMENT
);
875 if (shader
->NumUniformBlocks
)
876 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
880 brw_upload_wm_ubo_surfaces(struct brw_context
*brw
)
882 struct gl_context
*ctx
= &brw
->ctx
;
884 struct gl_shader_program
*prog
= ctx
->Shader
._CurrentFragmentProgram
;
889 /* CACHE_NEW_WM_PROG */
890 brw_upload_ubo_surfaces(brw
, prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
],
891 &brw
->wm
.base
, &brw
->wm
.prog_data
->base
);
894 const struct brw_tracked_state brw_wm_ubo_surfaces
= {
896 .mesa
= _NEW_PROGRAM
,
897 .brw
= BRW_NEW_BATCH
| BRW_NEW_UNIFORM_BUFFER
,
898 .cache
= CACHE_NEW_WM_PROG
,
900 .emit
= brw_upload_wm_ubo_surfaces
,
904 brw_upload_abo_surfaces(struct brw_context
*brw
,
905 struct gl_shader_program
*prog
,
906 struct brw_stage_state
*stage_state
,
907 struct brw_stage_prog_data
*prog_data
)
909 struct gl_context
*ctx
= &brw
->ctx
;
910 uint32_t *surf_offsets
=
911 &stage_state
->surf_offset
[prog_data
->binding_table
.abo_start
];
913 for (int i
= 0; i
< prog
->NumAtomicBuffers
; i
++) {
914 struct gl_atomic_buffer_binding
*binding
=
915 &ctx
->AtomicBufferBindings
[prog
->AtomicBuffers
[i
].Binding
];
916 struct intel_buffer_object
*intel_bo
=
917 intel_buffer_object(binding
->BufferObject
);
918 drm_intel_bo
*bo
= intel_bufferobj_buffer(
919 brw
, intel_bo
, binding
->Offset
, intel_bo
->Base
.Size
- binding
->Offset
);
921 brw
->vtbl
.create_raw_surface(brw
, bo
, binding
->Offset
,
922 bo
->size
- binding
->Offset
,
923 &surf_offsets
[i
], true);
926 if (prog
->NumUniformBlocks
)
927 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
931 brw_upload_wm_abo_surfaces(struct brw_context
*brw
)
933 struct gl_context
*ctx
= &brw
->ctx
;
935 struct gl_shader_program
*prog
= ctx
->Shader
._CurrentFragmentProgram
;
938 /* CACHE_NEW_WM_PROG */
939 brw_upload_abo_surfaces(brw
, prog
, &brw
->wm
.base
,
940 &brw
->wm
.prog_data
->base
);
944 const struct brw_tracked_state brw_wm_abo_surfaces
= {
946 .mesa
= _NEW_PROGRAM
,
947 .brw
= BRW_NEW_BATCH
| BRW_NEW_ATOMIC_BUFFER
,
948 .cache
= CACHE_NEW_WM_PROG
,
950 .emit
= brw_upload_wm_abo_surfaces
,
954 gen4_init_vtable_surface_functions(struct brw_context
*brw
)
956 brw
->vtbl
.update_texture_surface
= brw_update_texture_surface
;
957 brw
->vtbl
.update_renderbuffer_surface
= brw_update_renderbuffer_surface
;
958 brw
->vtbl
.update_null_renderbuffer_surface
=
959 brw_update_null_renderbuffer_surface
;
960 brw
->vtbl
.emit_buffer_surface_state
= gen4_emit_buffer_surface_state
;