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mesa: rename MESA_FORMAT_RG88_REV to MESA_FORMAT_RG88
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_surface_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/mtypes.h"
34 #include "main/samplerobj.h"
35 #include "program/prog_parameter.h"
36
37 #include "intel_mipmap_tree.h"
38 #include "intel_batchbuffer.h"
39 #include "intel_tex.h"
40 #include "intel_fbo.h"
41
42 #include "brw_context.h"
43 #include "brw_state.h"
44 #include "brw_defines.h"
45 #include "brw_wm.h"
46
47 GLuint
48 translate_tex_target(GLenum target)
49 {
50 switch (target) {
51 case GL_TEXTURE_1D:
52 case GL_TEXTURE_1D_ARRAY_EXT:
53 return BRW_SURFACE_1D;
54
55 case GL_TEXTURE_RECTANGLE_NV:
56 return BRW_SURFACE_2D;
57
58 case GL_TEXTURE_2D:
59 case GL_TEXTURE_2D_ARRAY_EXT:
60 return BRW_SURFACE_2D;
61
62 case GL_TEXTURE_3D:
63 return BRW_SURFACE_3D;
64
65 case GL_TEXTURE_CUBE_MAP:
66 return BRW_SURFACE_CUBE;
67
68 default:
69 assert(0);
70 return 0;
71 }
72 }
73
74 struct surface_format_info {
75 bool exists;
76 int sampling;
77 int filtering;
78 int shadow_compare;
79 int chroma_key;
80 int render_target;
81 int alpha_blend;
82 int input_vb;
83 int streamed_output_vb;
84 int color_processing;
85 };
86
87 /* This macro allows us to write the table almost as it appears in the PRM,
88 * while restructuring it to turn it into the C code we want.
89 */
90 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
91 [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
92
93 #define Y 0
94 #define x 999
95 /**
96 * This is the table of support for surface (texture, renderbuffer, and vertex
97 * buffer, but not depthbuffer) formats across the various hardware generations.
98 *
99 * The table is formatted to match the documentation, except that the docs have
100 * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever". To put
101 * it in our table, here's the mapping:
102 *
103 * Y*: 45
104 * Y+: 45 (g45/gm45)
105 * Y~: 50 (gen5)
106 * Y^: 60 (gen6)
107 * Y#: 70 (gen7)
108 *
109 * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
110 */
111 const struct surface_format_info surface_formats[] = {
112 /* smpl filt shad CK RT AB VB SO color */
113 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
114 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
115 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
116 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
117 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
118 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64_FLOAT)
119 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
120 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
121 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
122 SF( Y, 50, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
123 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_SINT)
124 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_UINT)
125 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
126 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
127 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
128 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
129 SF( Y, Y, x, x, Y, 45, Y, x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
130 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
131 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
132 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
133 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
134 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32_FLOAT)
135 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_SINT)
136 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_UINT)
137 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
138 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
139 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32A32_FLOAT)
140 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_UNORM)
141 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SNORM)
142 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64_FLOAT)
143 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
144 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
145 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32X32_FLOAT)
146 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32X32_FLOAT)
147 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32X32_FLOAT)
148 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
149 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
150 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SSCALED)
151 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_USCALED)
152 SF( Y, Y, x, Y, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
153 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
154 /* smpl filt shad CK RT AB VB SO color */
155 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
156 SF( Y, Y, x, x, x, x, x, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
157 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
158 SF( Y, Y, x, x, x, Y, Y, x, x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
159 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
160 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
161 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
162 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
163 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
164 SF( Y, Y, x, x, Y, 45, Y, x, x, BRW_SURFACEFORMAT_R16G16_UNORM)
165 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16_SNORM)
166 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SINT)
167 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_UINT)
168 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16_FLOAT)
169 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
170 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
171 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
172 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_SINT)
173 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_UINT)
174 SF( Y, 50, Y, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32_FLOAT)
175 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
176 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
177 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_UNORM)
178 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I24X8_UNORM)
179 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L24X8_UNORM)
180 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A24X8_UNORM)
181 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32_FLOAT)
182 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32_FLOAT)
183 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32_FLOAT)
184 SF( Y, Y, x, Y, x, x, x, x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
185 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
186 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
187 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
188 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
189 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
190 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_FLOAT)
191 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_UNORM)
192 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SNORM)
193 /* smpl filt shad CK RT AB VB SO color */
194 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
195 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
196 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
197 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SSCALED)
198 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_USCALED)
199 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SSCALED)
200 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_USCALED)
201 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
202 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
203 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
204 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
205 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
206 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
207 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8G8_UNORM)
208 SF( Y, Y, x, Y, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8_SNORM)
209 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SINT)
210 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_UINT)
211 SF( Y, Y, Y, x, Y, 45, Y, x, 70, BRW_SURFACEFORMAT_R16_UNORM)
212 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16_SNORM)
213 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_SINT)
214 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_UINT)
215 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16_FLOAT)
216 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_UNORM)
217 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_UNORM)
218 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_UNORM)
219 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM)
220 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_FLOAT)
221 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_FLOAT)
222 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_FLOAT)
223 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
224 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
225 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
226 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
227 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SSCALED)
228 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_USCALED)
229 /* smpl filt shad CK RT AB VB SO color */
230 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_SSCALED)
231 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_USCALED)
232 SF( Y, Y, x, 45, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8_UNORM)
233 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8_SNORM)
234 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_SINT)
235 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_UINT)
236 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_A8_UNORM)
237 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_UNORM)
238 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM)
239 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P4A4_UNORM)
240 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4P4_UNORM)
241 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_SSCALED)
242 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_USCALED)
243 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
244 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
245 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R1_UINT)
246 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
247 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
248 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM)
249 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM)
250 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM)
251 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_UNORM)
252 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_UNORM)
253 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
254 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
255 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
256 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_MONO8)
257 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
258 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
259 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB)
260 /* smpl filt shad CK RT AB VB SO color */
261 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_FXT1)
262 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
263 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
264 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
265 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
266 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
267 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
268 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_SNORM)
269 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_SNORM)
270 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
271 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
272 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
273 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
274 };
275 #undef x
276 #undef Y
277
278 uint32_t
279 brw_format_for_mesa_format(gl_format mesa_format)
280 {
281 /* This table is ordered according to the enum ordering in formats.h. We do
282 * expect that enum to be extended without our explicit initialization
283 * staying in sync, so we initialize to 0 even though
284 * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
285 */
286 static const uint32_t table[MESA_FORMAT_COUNT] =
287 {
288 [MESA_FORMAT_RGBA8888] = 0,
289 [MESA_FORMAT_RGBA8888_REV] = 0,
290 [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
291 [MESA_FORMAT_ARGB8888_REV] = 0,
292 [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
293 [MESA_FORMAT_XRGB8888_REV] = 0,
294 [MESA_FORMAT_RGB888] = 0,
295 [MESA_FORMAT_BGR888] = 0,
296 [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
297 [MESA_FORMAT_RGB565_REV] = 0,
298 [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
299 [MESA_FORMAT_ARGB4444_REV] = 0,
300 [MESA_FORMAT_RGBA5551] = 0,
301 [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
302 [MESA_FORMAT_ARGB1555_REV] = 0,
303 [MESA_FORMAT_AL44] = 0,
304 [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
305 [MESA_FORMAT_AL88_REV] = 0,
306 [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
307 [MESA_FORMAT_AL1616_REV] = 0,
308 [MESA_FORMAT_RGB332] = 0,
309 [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
310 [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
311 [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
312 [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
313 [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
314 [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
315 [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
316 [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
317 [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
318 [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
319 [MESA_FORMAT_RG88] = 0,
320 [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
321 [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
322 [MESA_FORMAT_RG1616_REV] = 0,
323 [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
324 [MESA_FORMAT_Z24_S8] = 0,
325 [MESA_FORMAT_S8_Z24] = 0,
326 [MESA_FORMAT_Z16] = 0,
327 [MESA_FORMAT_X8_Z24] = 0,
328 [MESA_FORMAT_Z24_S8] = 0,
329 [MESA_FORMAT_Z32] = 0,
330 [MESA_FORMAT_S8] = 0,
331
332 [MESA_FORMAT_SRGB8] = 0,
333 [MESA_FORMAT_SRGBA8] = 0,
334 [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
335 [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
336 [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
337 [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
338 [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
339 [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
340 [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
341
342 [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
343 [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
344 [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
345 [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
346 [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
347 [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
348
349 [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
350 [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
351 [MESA_FORMAT_RGB_FLOAT32] = 0,
352 [MESA_FORMAT_RGB_FLOAT16] = 0,
353 [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
354 [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
355 [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
356 [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
357 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
358 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
359 [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
360 [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
361 [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
362 [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
363 [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
364 [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
365
366 [MESA_FORMAT_ALPHA_UINT8] = 0,
367 [MESA_FORMAT_ALPHA_UINT16] = 0,
368 [MESA_FORMAT_ALPHA_UINT32] = 0,
369 [MESA_FORMAT_ALPHA_INT8] = 0,
370 [MESA_FORMAT_ALPHA_INT16] = 0,
371 [MESA_FORMAT_ALPHA_INT32] = 0,
372
373 [MESA_FORMAT_INTENSITY_UINT8] = 0,
374 [MESA_FORMAT_INTENSITY_UINT16] = 0,
375 [MESA_FORMAT_INTENSITY_UINT32] = 0,
376 [MESA_FORMAT_INTENSITY_INT8] = 0,
377 [MESA_FORMAT_INTENSITY_INT16] = 0,
378 [MESA_FORMAT_INTENSITY_INT32] = 0,
379
380 [MESA_FORMAT_LUMINANCE_UINT8] = 0,
381 [MESA_FORMAT_LUMINANCE_UINT16] = 0,
382 [MESA_FORMAT_LUMINANCE_UINT32] = 0,
383 [MESA_FORMAT_LUMINANCE_INT8] = 0,
384 [MESA_FORMAT_LUMINANCE_INT16] = 0,
385 [MESA_FORMAT_LUMINANCE_INT32] = 0,
386
387 [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
388 [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
389 [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
390 [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
391 [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
392 [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
393
394 [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
395 [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
396 [MESA_FORMAT_RGB_INT8] = 0,
397 [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
398 [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
399 [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
400 [MESA_FORMAT_RGB_INT16] = 0,
401 [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
402 [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
403 [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
404 [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
405 [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
406
407 [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
408 [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
409 [MESA_FORMAT_RGB_UINT8] = 0,
410 [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
411 [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
412 [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
413 [MESA_FORMAT_RGB_UINT16] = 0,
414 [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
415 [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
416 [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
417 [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
418 [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
419
420 [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
421 [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
422 [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
423 [MESA_FORMAT_SIGNED_RGBX8888] = 0,
424 [MESA_FORMAT_SIGNED_RGBA8888] = 0,
425 [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
426 [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
427 [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
428 [MESA_FORMAT_SIGNED_RGB_16] = 0,
429 [MESA_FORMAT_SIGNED_RGBA_16] = 0,
430 [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
431
432 [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
433 [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
434 [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
435 [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
436
437 [MESA_FORMAT_L_LATC1] = 0,
438 [MESA_FORMAT_SIGNED_L_LATC1] = 0,
439 [MESA_FORMAT_LA_LATC2] = 0,
440 [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
441
442 [MESA_FORMAT_SIGNED_A8] = 0,
443 [MESA_FORMAT_SIGNED_L8] = 0,
444 [MESA_FORMAT_SIGNED_AL88] = 0,
445 [MESA_FORMAT_SIGNED_I8] = 0,
446 [MESA_FORMAT_SIGNED_A16] = 0,
447 [MESA_FORMAT_SIGNED_L16] = 0,
448 [MESA_FORMAT_SIGNED_AL1616] = 0,
449 [MESA_FORMAT_SIGNED_I16] = 0,
450
451 [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
452 [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
453
454 [MESA_FORMAT_Z32_FLOAT] = 0,
455 [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
456 };
457 assert(mesa_format < MESA_FORMAT_COUNT);
458 return table[mesa_format];
459 }
460
461 void
462 brw_init_surface_formats(struct brw_context *brw)
463 {
464 struct intel_context *intel = &brw->intel;
465 struct gl_context *ctx = &intel->ctx;
466 int gen;
467 gl_format format;
468
469 gen = intel->gen * 10;
470 if (intel->is_g4x)
471 gen += 5;
472
473 for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
474 uint32_t texture, render;
475 const struct surface_format_info *rinfo, *tinfo;
476 bool is_integer = _mesa_is_format_integer_color(format);
477
478 render = texture = brw_format_for_mesa_format(format);
479 tinfo = &surface_formats[texture];
480
481 /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
482 * it.
483 */
484 if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
485 continue;
486
487 if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
488 ctx->TextureFormatSupported[format] = true;
489
490 /* Re-map some render target formats to make them supported when they
491 * wouldn't be using their format for texturing.
492 */
493 switch (render) {
494 /* For these formats, we just need to read/write the first
495 * channel into R, which is to say that we just treat them as
496 * GL_RED.
497 */
498 case BRW_SURFACEFORMAT_I32_FLOAT:
499 case BRW_SURFACEFORMAT_L32_FLOAT:
500 render = BRW_SURFACEFORMAT_R32_FLOAT;
501 break;
502 case BRW_SURFACEFORMAT_I16_FLOAT:
503 case BRW_SURFACEFORMAT_L16_FLOAT:
504 render = BRW_SURFACEFORMAT_R16_FLOAT;
505 break;
506 case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
507 /* XRGB is handled as ARGB because the chips in this family
508 * cannot render to XRGB targets. This means that we have to
509 * mask writes to alpha (ala glColorMask) and reconfigure the
510 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
511 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
512 * used.
513 */
514 render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
515 break;
516 }
517
518 rinfo = &surface_formats[render];
519
520 /* Note that GL_EXT_texture_integer says that blending doesn't occur for
521 * integer, so we don't need hardware support for blending on it. Other
522 * than that, GL in general requires alpha blending for render targets,
523 * even though we don't support it for some formats.
524 *
525 * We don't currently support rendering to SNORM textures because some of
526 * the ARB_color_buffer_float clamping is broken for it
527 * (piglit arb_color_buffer_float-drawpixels GL_RGBA8_SNORM).
528 */
529 if (gen >= rinfo->render_target &&
530 (gen >= rinfo->alpha_blend || is_integer) &&
531 _mesa_get_format_datatype(format) != GL_SIGNED_NORMALIZED) {
532 brw->render_target_format[format] = render;
533 brw->format_supported_as_render_target[format] = true;
534 }
535 }
536
537 /* We will check this table for FBO completeness, but the surface format
538 * table above only covered color rendering.
539 */
540 brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
541 brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
542 brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
543 brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
544
545 /* We remap depth formats to a supported texturing format in
546 * translate_tex_format().
547 */
548 ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
549 ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
550 }
551
552 bool
553 brw_render_target_supported(struct intel_context *intel, gl_format format)
554 {
555 struct brw_context *brw = brw_context(&intel->ctx);
556 /* Not exactly true, as some of those formats are not renderable.
557 * But at least we know how to translate them.
558 */
559 return brw->format_supported_as_render_target[format];
560 }
561
562 GLuint
563 translate_tex_format(gl_format mesa_format,
564 GLenum internal_format,
565 GLenum depth_mode,
566 GLenum srgb_decode)
567 {
568 switch( mesa_format ) {
569
570 case MESA_FORMAT_Z16:
571 return BRW_SURFACEFORMAT_I16_UNORM;
572
573 case MESA_FORMAT_S8_Z24:
574 case MESA_FORMAT_X8_Z24:
575 return BRW_SURFACEFORMAT_I24X8_UNORM;
576
577 case MESA_FORMAT_SARGB8:
578 case MESA_FORMAT_SLA8:
579 case MESA_FORMAT_SL8:
580 if (srgb_decode == GL_DECODE_EXT)
581 return brw_format_for_mesa_format(mesa_format);
582 else if (srgb_decode == GL_SKIP_DECODE_EXT)
583 return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
584
585 case MESA_FORMAT_RGBA8888_REV:
586 /* This format is not renderable? */
587 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
588
589 case MESA_FORMAT_RGBA_FLOAT32:
590 /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
591 * assertion below.
592 */
593 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
594
595 default:
596 assert(brw_format_for_mesa_format(mesa_format) != 0);
597 return brw_format_for_mesa_format(mesa_format);
598 }
599 }
600
601 static uint32_t
602 brw_get_surface_tiling_bits(uint32_t tiling)
603 {
604 switch (tiling) {
605 case I915_TILING_X:
606 return BRW_SURFACE_TILED;
607 case I915_TILING_Y:
608 return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
609 default:
610 return 0;
611 }
612 }
613
614 static void
615 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
616 {
617 struct brw_context *brw = brw_context(ctx);
618 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
619 struct intel_texture_object *intelObj = intel_texture_object(tObj);
620 struct intel_mipmap_tree *mt = intelObj->mt;
621 struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
622 struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
623 const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
624 uint32_t *surf;
625 int width, height, depth;
626
627 intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
628
629 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
630 6 * 4, 32, &brw->bind.surf_offset[surf_index]);
631
632 surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
633 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
634 BRW_SURFACE_CUBEFACE_ENABLES |
635 (translate_tex_format(firstImage->TexFormat,
636 firstImage->InternalFormat,
637 sampler->DepthMode,
638 sampler->sRGBDecode) <<
639 BRW_SURFACE_FORMAT_SHIFT));
640
641 surf[1] = intelObj->mt->region->bo->offset; /* reloc */
642
643 surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
644 (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
645 (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
646
647 surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
648 (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
649 ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
650 BRW_SURFACE_PITCH_SHIFT);
651
652 surf[4] = 0;
653
654 surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
655
656 /* Emit relocation to surface contents */
657 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
658 brw->bind.surf_offset[surf_index] + 4,
659 intelObj->mt->region->bo, 0,
660 I915_GEM_DOMAIN_SAMPLER, 0);
661 }
662
663 /**
664 * Create the constant buffer surface. Vertex/fragment shader constants will be
665 * read from this buffer with Data Port Read instructions/messages.
666 */
667 void
668 brw_create_constant_surface(struct brw_context *brw,
669 drm_intel_bo *bo,
670 int width,
671 uint32_t *out_offset)
672 {
673 struct intel_context *intel = &brw->intel;
674 const GLint w = width - 1;
675 uint32_t *surf;
676
677 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
678 6 * 4, 32, out_offset);
679
680 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
681 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
682 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
683
684 if (intel->gen >= 6)
685 surf[0] |= BRW_SURFACE_RC_READ_WRITE;
686
687 surf[1] = bo->offset; /* reloc */
688
689 surf[2] = (((w & 0x7f) - 1) << BRW_SURFACE_WIDTH_SHIFT |
690 (((w >> 7) & 0x1fff) - 1) << BRW_SURFACE_HEIGHT_SHIFT);
691
692 surf[3] = ((((w >> 20) & 0x7f) - 1) << BRW_SURFACE_DEPTH_SHIFT |
693 (width * 16 - 1) << BRW_SURFACE_PITCH_SHIFT);
694
695 surf[4] = 0;
696 surf[5] = 0;
697
698 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
699 * bspec ("Data Cache") says that the data cache does not exist as
700 * a separate cache and is just the sampler cache.
701 */
702 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
703 *out_offset + 4,
704 bo, 0,
705 I915_GEM_DOMAIN_SAMPLER, 0);
706 }
707
708 /* Creates a new WM constant buffer reflecting the current fragment program's
709 * constants, if needed by the fragment program.
710 *
711 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
712 * state atom.
713 */
714 static void
715 brw_upload_wm_pull_constants(struct brw_context *brw)
716 {
717 struct gl_context *ctx = &brw->intel.ctx;
718 struct intel_context *intel = &brw->intel;
719 /* BRW_NEW_FRAGMENT_PROGRAM */
720 struct brw_fragment_program *fp =
721 (struct brw_fragment_program *) brw->fragment_program;
722 struct gl_program_parameter_list *params = fp->program.Base.Parameters;
723 const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
724 const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
725 float *constants;
726 unsigned int i;
727
728 _mesa_load_state_parameters(ctx, params);
729
730 /* CACHE_NEW_WM_PROG */
731 if (brw->wm.prog_data->nr_pull_params == 0) {
732 if (brw->wm.const_bo) {
733 drm_intel_bo_unreference(brw->wm.const_bo);
734 brw->wm.const_bo = NULL;
735 brw->bind.surf_offset[surf_index] = 0;
736 brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
737 }
738 return;
739 }
740
741 drm_intel_bo_unreference(brw->wm.const_bo);
742 brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
743 size, 64);
744
745 /* _NEW_PROGRAM_CONSTANTS */
746 drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
747 constants = brw->wm.const_bo->virtual;
748 for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
749 constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
750 brw->wm.prog_data->pull_param[i]);
751 }
752 drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
753
754 intel->vtbl.create_constant_surface(brw, brw->wm.const_bo,
755 params->NumParameters,
756 &brw->bind.surf_offset[surf_index]);
757
758 brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
759 }
760
761 const struct brw_tracked_state brw_wm_pull_constants = {
762 .dirty = {
763 .mesa = (_NEW_PROGRAM_CONSTANTS),
764 .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
765 .cache = CACHE_NEW_WM_PROG,
766 },
767 .emit = brw_upload_wm_pull_constants,
768 };
769
770 static void
771 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
772 {
773 struct intel_context *intel = &brw->intel;
774 uint32_t *surf;
775
776 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
777 6 * 4, 32, &brw->bind.surf_offset[unit]);
778
779 surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
780 BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
781 if (intel->gen < 6) {
782 surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
783 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
784 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
785 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
786 }
787 surf[1] = 0;
788 surf[2] = 0;
789 surf[3] = 0;
790 surf[4] = 0;
791 surf[5] = 0;
792 }
793
794 /**
795 * Sets up a surface state structure to point at the given region.
796 * While it is only used for the front/back buffer currently, it should be
797 * usable for further buffers when doing ARB_draw_buffer support.
798 */
799 static void
800 brw_update_renderbuffer_surface(struct brw_context *brw,
801 struct gl_renderbuffer *rb,
802 unsigned int unit)
803 {
804 struct intel_context *intel = &brw->intel;
805 struct gl_context *ctx = &intel->ctx;
806 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
807 struct intel_mipmap_tree *mt = irb->mt;
808 struct intel_region *region = irb->mt->region;
809 uint32_t *surf;
810 uint32_t tile_x, tile_y;
811 uint32_t format = 0;
812
813 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
814 6 * 4, 32, &brw->bind.surf_offset[unit]);
815
816 switch (irb->Base.Format) {
817 case MESA_FORMAT_SARGB8:
818 /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
819 surfaces to the blend/update as sRGB */
820 if (ctx->Color.sRGBEnabled)
821 format = brw_format_for_mesa_format(irb->Base.Format);
822 else
823 format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
824 break;
825 default:
826 format = brw->render_target_format[irb->Base.Format];
827 if (unlikely(!brw->format_supported_as_render_target[irb->Base.Format])) {
828 _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
829 __FUNCTION__, _mesa_get_format_name(irb->Base.Format));
830 }
831 break;
832 }
833
834 surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
835 format << BRW_SURFACE_FORMAT_SHIFT);
836
837 /* reloc */
838 surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
839 region->bo->offset);
840
841 surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
842 (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
843
844 surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
845 ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
846
847 surf[4] = 0;
848
849 assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
850 /* Note that the low bits of these fields are missing, so
851 * there's the possibility of getting in trouble.
852 */
853 assert(tile_x % 4 == 0);
854 assert(tile_y % 2 == 0);
855 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
856 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
857 (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
858
859 if (intel->gen < 6) {
860 /* _NEW_COLOR */
861 if (!ctx->Color.ColorLogicOpEnabled &&
862 (ctx->Color.BlendEnabled & (1 << unit)))
863 surf[0] |= BRW_SURFACE_BLEND_ENABLED;
864
865 if (!ctx->Color.ColorMask[unit][0])
866 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
867 if (!ctx->Color.ColorMask[unit][1])
868 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
869 if (!ctx->Color.ColorMask[unit][2])
870 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
871
872 /* As mentioned above, disable writes to the alpha component when the
873 * renderbuffer is XRGB.
874 */
875 if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
876 !ctx->Color.ColorMask[unit][3]) {
877 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
878 }
879 }
880
881 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
882 brw->bind.surf_offset[unit] + 4,
883 region->bo,
884 surf[1] - region->bo->offset,
885 I915_GEM_DOMAIN_RENDER,
886 I915_GEM_DOMAIN_RENDER);
887 }
888
889 /**
890 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
891 */
892 static void
893 brw_update_renderbuffer_surfaces(struct brw_context *brw)
894 {
895 struct intel_context *intel = &brw->intel;
896 struct gl_context *ctx = &brw->intel.ctx;
897 GLuint i;
898
899 /* _NEW_BUFFERS | _NEW_COLOR */
900 /* Update surfaces for drawing buffers */
901 if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
902 for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
903 if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
904 intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
905 } else {
906 intel->vtbl.update_null_renderbuffer_surface(brw, i);
907 }
908 }
909 } else {
910 intel->vtbl.update_null_renderbuffer_surface(brw, 0);
911 }
912 brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
913 }
914
915 const struct brw_tracked_state brw_renderbuffer_surfaces = {
916 .dirty = {
917 .mesa = (_NEW_COLOR |
918 _NEW_BUFFERS),
919 .brw = BRW_NEW_BATCH,
920 .cache = 0
921 },
922 .emit = brw_update_renderbuffer_surfaces,
923 };
924
925 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
926 .dirty = {
927 .mesa = _NEW_BUFFERS,
928 .brw = BRW_NEW_BATCH,
929 .cache = 0
930 },
931 .emit = brw_update_renderbuffer_surfaces,
932 };
933
934 /**
935 * Construct SURFACE_STATE objects for enabled textures.
936 */
937 static void
938 brw_update_texture_surfaces(struct brw_context *brw)
939 {
940 struct gl_context *ctx = &brw->intel.ctx;
941
942 for (unsigned i = 0; i < BRW_MAX_TEX_UNIT; i++) {
943 const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
944 const GLuint surf = SURF_INDEX_TEXTURE(i);
945
946 /* _NEW_TEXTURE */
947 if (texUnit->_ReallyEnabled) {
948 brw->intel.vtbl.update_texture_surface(ctx, i);
949 } else {
950 brw->bind.surf_offset[surf] = 0;
951 }
952 }
953
954 brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
955 }
956
957 const struct brw_tracked_state brw_texture_surfaces = {
958 .dirty = {
959 .mesa = _NEW_TEXTURE,
960 .brw = BRW_NEW_BATCH,
961 .cache = 0
962 },
963 .emit = brw_update_texture_surfaces,
964 };
965
966 /**
967 * Constructs the binding table for the WM surface state, which maps unit
968 * numbers to surface state objects.
969 */
970 static void
971 brw_upload_binding_table(struct brw_context *brw)
972 {
973 uint32_t *bind;
974 int i;
975
976 /* Might want to calculate nr_surfaces first, to avoid taking up so much
977 * space for the binding table.
978 */
979 bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
980 sizeof(uint32_t) * BRW_MAX_SURFACES,
981 32, &brw->bind.bo_offset);
982
983 /* BRW_NEW_WM_SURFACES and BRW_NEW_VS_CONSTBUF */
984 for (i = 0; i < BRW_MAX_SURFACES; i++) {
985 bind[i] = brw->bind.surf_offset[i];
986 }
987
988 brw->state.dirty.brw |= BRW_NEW_VS_BINDING_TABLE;
989 brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
990 }
991
992 const struct brw_tracked_state brw_binding_table = {
993 .dirty = {
994 .mesa = 0,
995 .brw = (BRW_NEW_BATCH |
996 BRW_NEW_VS_CONSTBUF |
997 BRW_NEW_WM_SURFACES),
998 .cache = 0
999 },
1000 .emit = brw_upload_binding_table,
1001 };
1002
1003 void
1004 gen4_init_vtable_surface_functions(struct brw_context *brw)
1005 {
1006 struct intel_context *intel = &brw->intel;
1007
1008 intel->vtbl.update_texture_surface = brw_update_texture_surface;
1009 intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1010 intel->vtbl.update_null_renderbuffer_surface =
1011 brw_update_null_renderbuffer_surface;
1012 intel->vtbl.create_constant_surface = brw_create_constant_surface;
1013 }