src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/texformat.h"
  35 #include "main/texstore.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40
  41
  42 #include "brw_context.h"
  43 #include "brw_state.h"
  44 #include "brw_defines.h"
  45
  46
  47 static GLuint translate_tex_target( GLenum target )
  48 {
  49    switch (target) {
  50    case GL_TEXTURE_1D:
  51       return BRW_SURFACE_1D;
  52
  53    case GL_TEXTURE_RECTANGLE_NV:
  54       return BRW_SURFACE_2D;
  55
  56    case GL_TEXTURE_2D:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_3D:
  60       return BRW_SURFACE_3D;
  61
  62    case GL_TEXTURE_CUBE_MAP:
  63       return BRW_SURFACE_CUBE;
  64
  65    default:
  66       assert(0);
  67       return 0;
  68    }
  69 }
  70
  71
  72 static GLuint translate_tex_format( GLuint mesa_format, GLenum depth_mode )
  73 {
  74    switch( mesa_format ) {
  75    case MESA_FORMAT_L8:
  76       return BRW_SURFACEFORMAT_L8_UNORM;
  77
  78    case MESA_FORMAT_I8:
  79       return BRW_SURFACEFORMAT_I8_UNORM;
  80
  81    case MESA_FORMAT_A8:
  82       return BRW_SURFACEFORMAT_A8_UNORM;
  83
  84    case MESA_FORMAT_AL88:
  85       return BRW_SURFACEFORMAT_L8A8_UNORM;
  86
  87    case MESA_FORMAT_RGB888:
  88       assert(0);                /* not supported for sampling */
  89       return BRW_SURFACEFORMAT_R8G8B8_UNORM;
  90
  91    case MESA_FORMAT_ARGB8888:
  92       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
  93
  94    case MESA_FORMAT_RGBA8888_REV:
  95       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
  96
  97    case MESA_FORMAT_RGB565:
  98       return BRW_SURFACEFORMAT_B5G6R5_UNORM;
  99
 100    case MESA_FORMAT_ARGB1555:
 101       return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 102
 103    case MESA_FORMAT_ARGB4444:
 104       return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 105
 106    case MESA_FORMAT_YCBCR_REV:
 107       return BRW_SURFACEFORMAT_YCRCB_NORMAL;
 108
 109    case MESA_FORMAT_YCBCR:
 110       return BRW_SURFACEFORMAT_YCRCB_SWAPUVY;
 111
 112    case MESA_FORMAT_RGB_FXT1:
 113    case MESA_FORMAT_RGBA_FXT1:
 114       return BRW_SURFACEFORMAT_FXT1;
 115
 116    case MESA_FORMAT_Z16:
 117       if (depth_mode == GL_INTENSITY)
 118           return BRW_SURFACEFORMAT_I16_UNORM;
 119       else if (depth_mode == GL_ALPHA)
 120           return BRW_SURFACEFORMAT_A16_UNORM;
 121       else
 122           return BRW_SURFACEFORMAT_L16_UNORM;
 123
 124    case MESA_FORMAT_RGB_DXT1:
 125        return BRW_SURFACEFORMAT_DXT1_RGB;
 126
 127    case MESA_FORMAT_RGBA_DXT1:
 128        return BRW_SURFACEFORMAT_BC1_UNORM;
 129
 130    case MESA_FORMAT_RGBA_DXT3:
 131        return BRW_SURFACEFORMAT_BC2_UNORM;
 132
 133    case MESA_FORMAT_RGBA_DXT5:
 134        return BRW_SURFACEFORMAT_BC3_UNORM;
 135
 136    case MESA_FORMAT_SRGBA8:
 137       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB;
 138    case MESA_FORMAT_SRGB_DXT1:
 139       return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
 140
 141    case MESA_FORMAT_S8_Z24:
 142       return BRW_SURFACEFORMAT_I24X8_UNORM;
 143
 144    default:
 145       assert(0);
 146       return 0;
 147    }
 148 }
 149
 150 struct brw_wm_surface_key {
 151    GLenum target, depthmode;
 152    dri_bo *bo;
 153    GLint format;
 154    GLint first_level, last_level;
 155    GLint width, height, depth;
 156    GLint pitch, cpp;
 157    uint32_t tiling;
 158    GLuint offset;
 159 };
 160
 161 static void
 162 brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
 163 {
 164    switch (tiling) {
 165    case I915_TILING_NONE:
 166       surf->ss3.tiled_surface = 0;
 167       surf->ss3.tile_walk = 0;
 168       break;
 169    case I915_TILING_X:
 170       surf->ss3.tiled_surface = 1;
 171       surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
 172       break;
 173    case I915_TILING_Y:
 174       surf->ss3.tiled_surface = 1;
 175       surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
 176       break;
 177    }
 178 }
 179
 180 static dri_bo *
 181 brw_create_texture_surface( struct brw_context *brw,
 182                             struct brw_wm_surface_key *key )
 183 {
 184    struct brw_surface_state surf;
 185    dri_bo *bo;
 186
 187    memset(&surf, 0, sizeof(surf));
 188
 189    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 190    surf.ss0.surface_type = translate_tex_target(key->target);
 191
 192    if (key->bo)
 193       surf.ss0.surface_format = translate_tex_format(key->format, key->depthmode);
 194    else {
 195       switch (key->depth) {
 196       case 32:
 197          surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 198          break;
 199       default:
 200       case 24:
 201          surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
 202          break;
 203       case 16:
 204          surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 205          break;
 206       }
 207    }
 208
 209    /* This is ok for all textures with channel width 8bit or less:
 210     */
 211 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
 212    if (key->bo)
 213       surf.ss1.base_addr = key->bo->offset; /* reloc */
 214    else
 215       surf.ss1.base_addr = key->offset;
 216
 217    surf.ss2.mip_count = key->last_level - key->first_level;
 218    surf.ss2.width = key->width - 1;
 219    surf.ss2.height = key->height - 1;
 220    brw_set_surface_tiling(&surf, key->tiling);
 221    surf.ss3.pitch = (key->pitch * key->cpp) - 1;
 222    surf.ss3.depth = key->depth - 1;
 223
 224    surf.ss4.min_lod = 0;
 225
 226    if (key->target == GL_TEXTURE_CUBE_MAP) {
 227       surf.ss0.cube_pos_x = 1;
 228       surf.ss0.cube_pos_y = 1;
 229       surf.ss0.cube_pos_z = 1;
 230       surf.ss0.cube_neg_x = 1;
 231       surf.ss0.cube_neg_y = 1;
 232       surf.ss0.cube_neg_z = 1;
 233    }
 234
 235    bo = brw_upload_cache(&brw->cache, BRW_SS_SURFACE,
 236                          key, sizeof(*key),
 237                          &key->bo, key->bo ? 1 : 0,
 238                          &surf, sizeof(surf),
 239                          NULL, NULL);
 240
 241    if (key->bo) {
 242       /* Emit relocation to surface contents */
 243       dri_bo_emit_reloc(bo,
 244                         I915_GEM_DOMAIN_SAMPLER, 0,
 245                         0,
 246                         offsetof(struct brw_surface_state, ss1),
 247                         key->bo);
 248    }
 249    return bo;
 250 }
 251
 252 static void
 253 brw_update_texture_surface( GLcontext *ctx, GLuint unit )
 254 {
 255    struct brw_context *brw = brw_context(ctx);
 256    struct gl_texture_object *tObj = brw->attribs.Texture->Unit[unit]._Current;
 257    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 258    struct gl_texture_image *firstImage = tObj->Image[0][intelObj->firstLevel];
 259    struct brw_wm_surface_key key;
 260
 261    memset(&key, 0, sizeof(key));
 262
 263    if (intelObj->imageOverride) {
 264       key.pitch = intelObj->pitchOverride / intelObj->mt->cpp;
 265       key.depth = intelObj->depthOverride;
 266       key.bo = NULL;
 267       key.offset = intelObj->textureOffset;
 268    } else {
 269       key.format = firstImage->TexFormat->MesaFormat;
 270       key.pitch = intelObj->mt->pitch;
 271       key.depth = firstImage->Depth;
 272       key.bo = intelObj->mt->region->buffer;
 273       key.offset = 0;
 274    }
 275
 276    key.target = tObj->Target;
 277    key.depthmode = tObj->DepthMode;
 278    key.first_level = intelObj->firstLevel;
 279    key.last_level = intelObj->lastLevel;
 280    key.width = firstImage->Width;
 281    key.height = firstImage->Height;
 282    key.cpp = intelObj->mt->cpp;
 283    key.tiling = intelObj->mt->region->tiling;
 284
 285    dri_bo_unreference(brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS]);
 286    brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] = brw_search_cache(&brw->cache, BRW_SS_SURFACE,
 287                                                                &key, sizeof(key),
 288                                                                &key.bo, key.bo ? 1 : 0,
 289                                                                NULL);
 290    if (brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] == NULL) {
 291       brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] = brw_create_texture_surface(brw, &key);
 292    }
 293 }
 294
 295 /**
 296  * Sets up a surface state structure to point at the given region.
 297  * While it is only used for the front/back buffer currently, it should be
 298  * usable for further buffers when doing ARB_draw_buffer support.
 299  */
 300 static void
 301 brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
 302                           unsigned int unit, GLboolean cached)
 303 {
 304    dri_bo *region_bo = NULL;
 305    struct {
 306       unsigned int surface_type;
 307       unsigned int surface_format;
 308       unsigned int width, height, cpp;
 309       GLubyte color_mask[4];
 310       GLboolean color_blend;
 311       uint32_t tiling;
 312    } key;
 313
 314    memset(&key, 0, sizeof(key));
 315
 316    if (region != NULL) {
 317       region_bo = region->buffer;
 318
 319       key.surface_type = BRW_SURFACE_2D;
 320       if (region->cpp == 4)
 321          key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 322       else
 323          key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 324       key.tiling = region->tiling;
 325       key.width = region->pitch; /* XXX: not really! */
 326       key.height = region->height;
 327       key.cpp = region->cpp;
 328    } else {
 329       key.surface_type = BRW_SURFACE_NULL;
 330       key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 331       key.tiling = 0;
 332       key.width = 1;
 333       key.height = 1;
 334       key.cpp = 4;
 335    }
 336    memcpy(key.color_mask, brw->attribs.Color->ColorMask,
 337           sizeof(key.color_mask));
 338    key.color_blend = (!brw->attribs.Color->_LogicOpEnabled &&
 339                       brw->attribs.Color->BlendEnabled);
 340
 341    dri_bo_unreference(brw->wm.surf_bo[unit]);
 342    brw->wm.surf_bo[unit] = NULL;
 343    if (cached)
 344        brw->wm.surf_bo[unit] = brw_search_cache(&brw->cache, BRW_SS_SURFACE,
 345                &key, sizeof(key),
 346                &region_bo, 1,
 347                NULL);
 348
 349    if (brw->wm.surf_bo[unit] == NULL) {
 350       struct brw_surface_state surf;
 351
 352       memset(&surf, 0, sizeof(surf));
 353
 354       surf.ss0.surface_format = key.surface_format;
 355       surf.ss0.surface_type = key.surface_type;
 356       if (region_bo != NULL)
 357          surf.ss1.base_addr = region_bo->offset; /* reloc */
 358
 359       surf.ss2.width = key.width - 1;
 360       surf.ss2.height = key.height - 1;
 361       brw_set_surface_tiling(&surf, key.tiling);
 362       surf.ss3.pitch = (key.width * key.cpp) - 1;
 363
 364       /* _NEW_COLOR */
 365       surf.ss0.color_blend = key.color_blend;
 366       surf.ss0.writedisable_red =   !key.color_mask[0];
 367       surf.ss0.writedisable_green = !key.color_mask[1];
 368       surf.ss0.writedisable_blue =  !key.color_mask[2];
 369       surf.ss0.writedisable_alpha = !key.color_mask[3];
 370
 371       /* Key size will never match key size for textures, so we're safe. */
 372       brw->wm.surf_bo[unit] = brw_upload_cache(&brw->cache, BRW_SS_SURFACE,
 373                                               &key, sizeof(key),
 374                                                &region_bo, 1,
 375                                                &surf, sizeof(surf),
 376                                                NULL, NULL);
 377       if (region_bo != NULL) {
 378          /* We might sample from it, and we might render to it, so flag
 379           * them both.  We might be able to figure out from other state
 380           * a more restrictive relocation to emit.
 381           */
 382          dri_bo_emit_reloc(brw->wm.surf_bo[unit],
 383                            I915_GEM_DOMAIN_RENDER |
 384                            I915_GEM_DOMAIN_SAMPLER,
 385                            I915_GEM_DOMAIN_RENDER,
 386                            0,
 387                            offsetof(struct brw_surface_state, ss1),
 388                            region_bo);
 389       }
 390    }
 391 }
 392
 393
 394 /**
 395  * Constructs the binding table for the WM surface state, which maps unit
 396  * numbers to surface state objects.
 397  */
 398 static dri_bo *
 399 brw_wm_get_binding_table(struct brw_context *brw)
 400 {
 401    dri_bo *bind_bo;
 402
 403    bind_bo = brw_search_cache(&brw->cache, BRW_SS_SURF_BIND,
 404                               NULL, 0,
 405                               brw->wm.surf_bo, brw->wm.nr_surfaces,
 406                               NULL);
 407
 408    if (bind_bo == NULL) {
 409       GLuint data_size = brw->wm.nr_surfaces * sizeof(GLuint);
 410       uint32_t *data = malloc(data_size);
 411       int i;
 412
 413       for (i = 0; i < brw->wm.nr_surfaces; i++)
 414          if (brw->wm.surf_bo[i])
 415             data[i] = brw->wm.surf_bo[i]->offset;
 416          else
 417             data[i] = 0;
 418
 419       bind_bo = brw_upload_cache( &brw->cache, BRW_SS_SURF_BIND,
 420                                   NULL, 0,
 421                                   brw->wm.surf_bo, brw->wm.nr_surfaces,
 422                                   data, data_size,
 423                                   NULL, NULL);
 424
 425       /* Emit binding table relocations to surface state */
 426       for (i = 0; i < BRW_WM_MAX_SURF; i++) {
 427          if (brw->wm.surf_bo[i] != NULL) {
 428             dri_bo_emit_reloc(bind_bo,
 429                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 430                               0,
 431                               i * sizeof(GLuint),
 432                               brw->wm.surf_bo[i]);
 433          }
 434       }
 435
 436       free(data);
 437    }
 438
 439    return bind_bo;
 440 }
 441
 442 static void prepare_wm_surfaces(struct brw_context *brw )
 443 {
 444    GLcontext *ctx = &brw->intel.ctx;
 445    struct intel_context *intel = &brw->intel;
 446    GLuint i;
 447    int old_nr_surfaces;
 448
 449    if (brw->state.nr_draw_regions  > 1) {
 450       for (i = 0; i < brw->state.nr_draw_regions; i++) {
 451          brw_update_region_surface(brw, brw->state.draw_regions[i], i,
 452                                    GL_FALSE);
 453       }
 454    }else {
 455       brw_update_region_surface(brw, brw->state.draw_regions[0], 0, GL_TRUE);
 456    }
 457
 458    old_nr_surfaces = brw->wm.nr_surfaces;
 459    brw->wm.nr_surfaces = MAX_DRAW_BUFFERS;
 460
 461    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 462       struct gl_texture_unit *texUnit = &brw->attribs.Texture->Unit[i];
 463
 464       /* _NEW_TEXTURE, BRW_NEW_TEXDATA */
 465       if(texUnit->_ReallyEnabled) {
 466          if (texUnit->_Current == intel->frame_buffer_texobj) {
 467             dri_bo_unreference(brw->wm.surf_bo[i+MAX_DRAW_BUFFERS]);
 468             brw->wm.surf_bo[i+MAX_DRAW_BUFFERS] = brw->wm.surf_bo[0];
 469             dri_bo_reference(brw->wm.surf_bo[i+MAX_DRAW_BUFFERS]);
 470             brw->wm.nr_surfaces = i + MAX_DRAW_BUFFERS + 1;
 471          } else {
 472             brw_update_texture_surface(ctx, i);
 473             brw->wm.nr_surfaces = i + MAX_DRAW_BUFFERS + 1;
 474          }
 475       } else {
 476          dri_bo_unreference(brw->wm.surf_bo[i+MAX_DRAW_BUFFERS]);
 477          brw->wm.surf_bo[i+MAX_DRAW_BUFFERS] = NULL;
 478       }
 479
 480    }
 481
 482    dri_bo_unreference(brw->wm.bind_bo);
 483    brw->wm.bind_bo = brw_wm_get_binding_table(brw);
 484
 485    if (brw->wm.nr_surfaces != old_nr_surfaces)
 486       brw->state.dirty.brw |= BRW_NEW_NR_SURFACES;
 487 }
 488
 489
 490 const struct brw_tracked_state brw_wm_surfaces = {
 491    .dirty = {
 492       .mesa = _NEW_COLOR | _NEW_TEXTURE | _NEW_BUFFERS,
 493       .brw = BRW_NEW_CONTEXT,
 494       .cache = 0
 495    },
 496    .prepare = prepare_wm_surfaces,
 497 };
 498
 499
 500