Merge remote branch 'origin/master' into radeon-rewrite
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_surface_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/mtypes.h"
34 #include "main/texformat.h"
35 #include "main/texstore.h"
36 #include "shader/prog_parameter.h"
37
38 #include "intel_mipmap_tree.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_tex.h"
41
42
43 #include "brw_context.h"
44 #include "brw_state.h"
45 #include "brw_defines.h"
46
47
48 static GLuint translate_tex_target( GLenum target )
49 {
50 switch (target) {
51 case GL_TEXTURE_1D:
52 return BRW_SURFACE_1D;
53
54 case GL_TEXTURE_RECTANGLE_NV:
55 return BRW_SURFACE_2D;
56
57 case GL_TEXTURE_2D:
58 return BRW_SURFACE_2D;
59
60 case GL_TEXTURE_3D:
61 return BRW_SURFACE_3D;
62
63 case GL_TEXTURE_CUBE_MAP:
64 return BRW_SURFACE_CUBE;
65
66 default:
67 assert(0);
68 return 0;
69 }
70 }
71
72
73 static GLuint translate_tex_format( GLuint mesa_format, GLenum internal_format,
74 GLenum depth_mode )
75 {
76 switch( mesa_format ) {
77 case MESA_FORMAT_L8:
78 return BRW_SURFACEFORMAT_L8_UNORM;
79
80 case MESA_FORMAT_I8:
81 return BRW_SURFACEFORMAT_I8_UNORM;
82
83 case MESA_FORMAT_A8:
84 return BRW_SURFACEFORMAT_A8_UNORM;
85
86 case MESA_FORMAT_AL88:
87 return BRW_SURFACEFORMAT_L8A8_UNORM;
88
89 case MESA_FORMAT_RGB888:
90 assert(0); /* not supported for sampling */
91 return BRW_SURFACEFORMAT_R8G8B8_UNORM;
92
93 case MESA_FORMAT_ARGB8888:
94 if (internal_format == GL_RGB)
95 return BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
96 else
97 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
98
99 case MESA_FORMAT_RGBA8888_REV:
100 if (internal_format == GL_RGB)
101 return BRW_SURFACEFORMAT_R8G8B8X8_UNORM;
102 else
103 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
104
105 case MESA_FORMAT_RGB565:
106 return BRW_SURFACEFORMAT_B5G6R5_UNORM;
107
108 case MESA_FORMAT_ARGB1555:
109 return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
110
111 case MESA_FORMAT_ARGB4444:
112 return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
113
114 case MESA_FORMAT_YCBCR_REV:
115 return BRW_SURFACEFORMAT_YCRCB_NORMAL;
116
117 case MESA_FORMAT_YCBCR:
118 return BRW_SURFACEFORMAT_YCRCB_SWAPUVY;
119
120 case MESA_FORMAT_RGB_FXT1:
121 case MESA_FORMAT_RGBA_FXT1:
122 return BRW_SURFACEFORMAT_FXT1;
123
124 case MESA_FORMAT_Z16:
125 if (depth_mode == GL_INTENSITY)
126 return BRW_SURFACEFORMAT_I16_UNORM;
127 else if (depth_mode == GL_ALPHA)
128 return BRW_SURFACEFORMAT_A16_UNORM;
129 else
130 return BRW_SURFACEFORMAT_L16_UNORM;
131
132 case MESA_FORMAT_RGB_DXT1:
133 return BRW_SURFACEFORMAT_DXT1_RGB;
134
135 case MESA_FORMAT_RGBA_DXT1:
136 return BRW_SURFACEFORMAT_BC1_UNORM;
137
138 case MESA_FORMAT_RGBA_DXT3:
139 return BRW_SURFACEFORMAT_BC2_UNORM;
140
141 case MESA_FORMAT_RGBA_DXT5:
142 return BRW_SURFACEFORMAT_BC3_UNORM;
143
144 case MESA_FORMAT_SARGB8:
145 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB;
146
147 case MESA_FORMAT_SLA8:
148 return BRW_SURFACEFORMAT_L8A8_UNORM_SRGB;
149
150 case MESA_FORMAT_SL8:
151 return BRW_SURFACEFORMAT_L8_UNORM_SRGB;
152
153 case MESA_FORMAT_SRGB_DXT1:
154 return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
155
156 case MESA_FORMAT_S8_Z24:
157 /* XXX: these different surface formats don't seem to
158 * make any difference for shadow sampler/compares.
159 */
160 if (depth_mode == GL_INTENSITY)
161 return BRW_SURFACEFORMAT_I24X8_UNORM;
162 else if (depth_mode == GL_ALPHA)
163 return BRW_SURFACEFORMAT_A24X8_UNORM;
164 else
165 return BRW_SURFACEFORMAT_L24X8_UNORM;
166
167 case MESA_FORMAT_DUDV8:
168 return BRW_SURFACEFORMAT_R8G8_SNORM;
169
170 case MESA_FORMAT_SIGNED_RGBA8888_REV:
171 return BRW_SURFACEFORMAT_R8G8B8A8_SNORM;
172
173 default:
174 assert(0);
175 return 0;
176 }
177 }
178
179 struct brw_wm_surface_key {
180 GLenum target, depthmode;
181 dri_bo *bo;
182 GLint format, internal_format;
183 GLint first_level, last_level;
184 GLint width, height, depth;
185 GLint pitch, cpp;
186 uint32_t tiling;
187 GLuint offset;
188 };
189
190 static void
191 brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
192 {
193 switch (tiling) {
194 case I915_TILING_NONE:
195 surf->ss3.tiled_surface = 0;
196 surf->ss3.tile_walk = 0;
197 break;
198 case I915_TILING_X:
199 surf->ss3.tiled_surface = 1;
200 surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
201 break;
202 case I915_TILING_Y:
203 surf->ss3.tiled_surface = 1;
204 surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
205 break;
206 }
207 }
208
209 static dri_bo *
210 brw_create_texture_surface( struct brw_context *brw,
211 struct brw_wm_surface_key *key )
212 {
213 struct brw_surface_state surf;
214 dri_bo *bo;
215
216 memset(&surf, 0, sizeof(surf));
217
218 surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
219 surf.ss0.surface_type = translate_tex_target(key->target);
220 if (key->bo) {
221 surf.ss0.surface_format = translate_tex_format(key->format,
222 key->internal_format,
223 key->depthmode);
224 }
225 else {
226 switch (key->depth) {
227 case 32:
228 surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
229 break;
230 default:
231 case 24:
232 surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
233 break;
234 case 16:
235 surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
236 break;
237 }
238 }
239
240 /* This is ok for all textures with channel width 8bit or less:
241 */
242 /* surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
243 if (key->bo)
244 surf.ss1.base_addr = key->bo->offset; /* reloc */
245 else
246 surf.ss1.base_addr = key->offset;
247
248 surf.ss2.mip_count = key->last_level - key->first_level;
249 surf.ss2.width = key->width - 1;
250 surf.ss2.height = key->height - 1;
251 brw_set_surface_tiling(&surf, key->tiling);
252 surf.ss3.pitch = (key->pitch * key->cpp) - 1;
253 surf.ss3.depth = key->depth - 1;
254
255 surf.ss4.min_lod = 0;
256
257 if (key->target == GL_TEXTURE_CUBE_MAP) {
258 surf.ss0.cube_pos_x = 1;
259 surf.ss0.cube_pos_y = 1;
260 surf.ss0.cube_pos_z = 1;
261 surf.ss0.cube_neg_x = 1;
262 surf.ss0.cube_neg_y = 1;
263 surf.ss0.cube_neg_z = 1;
264 }
265
266 bo = brw_upload_cache(&brw->cache, BRW_SS_SURFACE,
267 key, sizeof(*key),
268 &key->bo, key->bo ? 1 : 0,
269 &surf, sizeof(surf),
270 NULL, NULL);
271
272 if (key->bo) {
273 /* Emit relocation to surface contents */
274 dri_bo_emit_reloc(bo,
275 I915_GEM_DOMAIN_SAMPLER, 0,
276 0,
277 offsetof(struct brw_surface_state, ss1),
278 key->bo);
279 }
280 return bo;
281 }
282
283 static void
284 brw_update_texture_surface( GLcontext *ctx, GLuint unit )
285 {
286 struct brw_context *brw = brw_context(ctx);
287 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
288 struct intel_texture_object *intelObj = intel_texture_object(tObj);
289 struct gl_texture_image *firstImage = tObj->Image[0][intelObj->firstLevel];
290 struct brw_wm_surface_key key;
291 const GLuint j = MAX_DRAW_BUFFERS + unit;
292
293 memset(&key, 0, sizeof(key));
294
295 if (intelObj->imageOverride) {
296 key.pitch = intelObj->pitchOverride / intelObj->mt->cpp;
297 key.depth = intelObj->depthOverride;
298 key.bo = NULL;
299 key.offset = intelObj->textureOffset;
300 } else {
301 key.format = firstImage->TexFormat->MesaFormat;
302 key.internal_format = firstImage->InternalFormat;
303 key.pitch = intelObj->mt->pitch;
304 key.depth = firstImage->Depth;
305 key.bo = intelObj->mt->region->buffer;
306 key.offset = 0;
307 }
308
309 key.target = tObj->Target;
310 key.depthmode = tObj->DepthMode;
311 key.first_level = intelObj->firstLevel;
312 key.last_level = intelObj->lastLevel;
313 key.width = firstImage->Width;
314 key.height = firstImage->Height;
315 key.cpp = intelObj->mt->cpp;
316 key.tiling = intelObj->mt->region->tiling;
317
318 dri_bo_unreference(brw->wm.surf_bo[j]);
319 brw->wm.surf_bo[j] = brw_search_cache(&brw->cache, BRW_SS_SURFACE,
320 &key, sizeof(key),
321 &key.bo, key.bo ? 1 : 0,
322 NULL);
323 if (brw->wm.surf_bo[j] == NULL) {
324 brw->wm.surf_bo[j] = brw_create_texture_surface(brw, &key);
325 }
326 }
327
328
329
330 /**
331 * Create the constant buffer surface. Fragment shader constanst will be
332 * read from this buffer with Data Port Read instructions/messages.
333 */
334 static dri_bo *
335 brw_create_constant_surface( struct brw_context *brw,
336 struct brw_wm_surface_key *key )
337 {
338 const GLint w = key->width - 1;
339 struct brw_surface_state surf;
340 dri_bo *bo;
341
342 memset(&surf, 0, sizeof(surf));
343
344 surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
345 surf.ss0.surface_type = BRW_SURFACE_BUFFER;
346 surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
347
348 /* This is ok for all textures with channel width 8bit or less:
349 */
350 assert(key->bo);
351 if (key->bo)
352 surf.ss1.base_addr = key->bo->offset; /* reloc */
353 else
354 surf.ss1.base_addr = key->offset;
355
356 surf.ss2.width = w & 0x7f; /* bits 6:0 of size or width */
357 surf.ss2.height = (w >> 7) & 0x1fff; /* bits 19:7 of size or width */
358 surf.ss3.depth = (w >> 20) & 0x7f; /* bits 26:20 of size or width */
359 surf.ss3.pitch = (key->pitch * key->cpp) - 1;
360 brw_set_surface_tiling(&surf, key->tiling);
361
362 bo = brw_upload_cache(&brw->cache, BRW_SS_SURFACE,
363 key, sizeof(*key),
364 &key->bo, key->bo ? 1 : 0,
365 &surf, sizeof(surf),
366 NULL, NULL);
367
368 if (key->bo) {
369 /* Emit relocation to surface contents */
370 dri_bo_emit_reloc(bo,
371 I915_GEM_DOMAIN_SAMPLER, 0,
372 0,
373 offsetof(struct brw_surface_state, ss1),
374 key->bo);
375 }
376
377 return bo;
378 }
379
380
381 /**
382 * Update the constant buffer surface.
383 */
384 static void
385 brw_update_constant_surface( GLcontext *ctx,
386 const struct brw_fragment_program *fp )
387 {
388 struct brw_context *brw = brw_context(ctx);
389 struct brw_wm_surface_key key;
390 const GLuint j = BRW_WM_MAX_SURF - 1;
391 const GLuint numParams = fp->program.Base.Parameters->NumParameters;
392
393 memset(&key, 0, sizeof(key));
394
395 key.format = MESA_FORMAT_RGBA_FLOAT32;
396 key.internal_format = GL_RGBA;
397 key.bo = fp->const_buffer;
398
399 key.depthmode = GL_NONE;
400 key.pitch = numParams;
401 key.width = numParams;
402 key.height = 1;
403 key.depth = 1;
404 key.cpp = 16;
405
406 /*
407 printf("%s:\n", __FUNCTION__);
408 printf(" width %d height %d depth %d cpp %d pitch %d\n",
409 key.width, key.height, key.depth, key.cpp, key.pitch);
410 */
411
412 dri_bo_unreference(brw->wm.surf_bo[j]);
413 brw->wm.surf_bo[j] = brw_search_cache(&brw->cache, BRW_SS_SURFACE,
414 &key, sizeof(key),
415 &key.bo, key.bo ? 1 : 0,
416 NULL);
417 if (brw->wm.surf_bo[j] == NULL) {
418 brw->wm.surf_bo[j] = brw_create_constant_surface(brw, &key);
419 }
420 }
421
422
423 /**
424 * Sets up a surface state structure to point at the given region.
425 * While it is only used for the front/back buffer currently, it should be
426 * usable for further buffers when doing ARB_draw_buffer support.
427 */
428 static void
429 brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
430 unsigned int unit, GLboolean cached)
431 {
432 GLcontext *ctx = &brw->intel.ctx;
433 dri_bo *region_bo = NULL;
434 struct {
435 unsigned int surface_type;
436 unsigned int surface_format;
437 unsigned int width, height, cpp;
438 GLubyte color_mask[4];
439 GLboolean color_blend;
440 uint32_t tiling;
441 } key;
442
443 memset(&key, 0, sizeof(key));
444
445 if (region != NULL) {
446 region_bo = region->buffer;
447
448 key.surface_type = BRW_SURFACE_2D;
449 if (region->cpp == 4)
450 key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
451 else
452 key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
453 key.tiling = region->tiling;
454 key.width = region->pitch; /* XXX: not really! */
455 key.height = region->height;
456 key.cpp = region->cpp;
457 } else {
458 key.surface_type = BRW_SURFACE_NULL;
459 key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
460 key.tiling = 0;
461 key.width = 1;
462 key.height = 1;
463 key.cpp = 4;
464 }
465 memcpy(key.color_mask, ctx->Color.ColorMask,
466 sizeof(key.color_mask));
467 key.color_blend = (!ctx->Color._LogicOpEnabled &&
468 ctx->Color.BlendEnabled);
469
470 dri_bo_unreference(brw->wm.surf_bo[unit]);
471 brw->wm.surf_bo[unit] = NULL;
472 if (cached)
473 brw->wm.surf_bo[unit] = brw_search_cache(&brw->cache, BRW_SS_SURFACE,
474 &key, sizeof(key),
475 &region_bo, 1,
476 NULL);
477
478 if (brw->wm.surf_bo[unit] == NULL) {
479 struct brw_surface_state surf;
480
481 memset(&surf, 0, sizeof(surf));
482
483 surf.ss0.surface_format = key.surface_format;
484 surf.ss0.surface_type = key.surface_type;
485 if (region_bo != NULL)
486 surf.ss1.base_addr = region_bo->offset; /* reloc */
487
488 surf.ss2.width = key.width - 1;
489 surf.ss2.height = key.height - 1;
490 brw_set_surface_tiling(&surf, key.tiling);
491 surf.ss3.pitch = (key.width * key.cpp) - 1;
492
493 /* _NEW_COLOR */
494 surf.ss0.color_blend = key.color_blend;
495 surf.ss0.writedisable_red = !key.color_mask[0];
496 surf.ss0.writedisable_green = !key.color_mask[1];
497 surf.ss0.writedisable_blue = !key.color_mask[2];
498 surf.ss0.writedisable_alpha = !key.color_mask[3];
499
500 /* Key size will never match key size for textures, so we're safe. */
501 brw->wm.surf_bo[unit] = brw_upload_cache(&brw->cache, BRW_SS_SURFACE,
502 &key, sizeof(key),
503 &region_bo, 1,
504 &surf, sizeof(surf),
505 NULL, NULL);
506 if (region_bo != NULL) {
507 /* We might sample from it, and we might render to it, so flag
508 * them both. We might be able to figure out from other state
509 * a more restrictive relocation to emit.
510 */
511 dri_bo_emit_reloc(brw->wm.surf_bo[unit],
512 I915_GEM_DOMAIN_RENDER,
513 I915_GEM_DOMAIN_RENDER,
514 0,
515 offsetof(struct brw_surface_state, ss1),
516 region_bo);
517 }
518 }
519 }
520
521
522 /**
523 * Constructs the binding table for the WM surface state, which maps unit
524 * numbers to surface state objects.
525 */
526 static dri_bo *
527 brw_wm_get_binding_table(struct brw_context *brw)
528 {
529 dri_bo *bind_bo;
530
531 bind_bo = brw_search_cache(&brw->cache, BRW_SS_SURF_BIND,
532 NULL, 0,
533 brw->wm.surf_bo, brw->wm.nr_surfaces,
534 NULL);
535
536 if (bind_bo == NULL) {
537 GLuint data_size = brw->wm.nr_surfaces * sizeof(GLuint);
538 uint32_t *data = malloc(data_size);
539 int i;
540
541 for (i = 0; i < brw->wm.nr_surfaces; i++)
542 if (brw->wm.surf_bo[i])
543 data[i] = brw->wm.surf_bo[i]->offset;
544 else
545 data[i] = 0;
546
547 bind_bo = brw_upload_cache( &brw->cache, BRW_SS_SURF_BIND,
548 NULL, 0,
549 brw->wm.surf_bo, brw->wm.nr_surfaces,
550 data, data_size,
551 NULL, NULL);
552
553 /* Emit binding table relocations to surface state */
554 for (i = 0; i < BRW_WM_MAX_SURF; i++) {
555 if (brw->wm.surf_bo[i] != NULL) {
556 dri_bo_emit_reloc(bind_bo,
557 I915_GEM_DOMAIN_INSTRUCTION, 0,
558 0,
559 i * sizeof(GLuint),
560 brw->wm.surf_bo[i]);
561 }
562 }
563
564 free(data);
565 }
566
567 return bind_bo;
568 }
569
570 static void prepare_wm_surfaces(struct brw_context *brw )
571 {
572 GLcontext *ctx = &brw->intel.ctx;
573 struct intel_context *intel = &brw->intel;
574 GLuint i;
575 int old_nr_surfaces;
576
577 /* Update surfaces for drawing buffers */
578 if (brw->state.nr_color_regions > 1) {
579 for (i = 0; i < brw->state.nr_color_regions; i++) {
580 brw_update_region_surface(brw, brw->state.color_regions[i], i,
581 GL_FALSE);
582 }
583 } else {
584 brw_update_region_surface(brw, brw->state.color_regions[0], 0, GL_TRUE);
585 }
586
587 old_nr_surfaces = brw->wm.nr_surfaces;
588 brw->wm.nr_surfaces = MAX_DRAW_BUFFERS;
589
590 /* Update surfaces for textures */
591 for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
592 const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
593 const GLuint j = MAX_DRAW_BUFFERS + i;
594
595 /* _NEW_TEXTURE, BRW_NEW_TEXDATA */
596 if (texUnit->_ReallyEnabled) {
597 if (texUnit->_Current == intel->frame_buffer_texobj) {
598 /* render to texture */
599 dri_bo_unreference(brw->wm.surf_bo[j]);
600 brw->wm.surf_bo[j] = brw->wm.surf_bo[0];
601 dri_bo_reference(brw->wm.surf_bo[j]);
602 brw->wm.nr_surfaces = j + 1;
603 } else {
604 /* regular texture */
605 brw_update_texture_surface(ctx, i);
606 brw->wm.nr_surfaces = j + 1;
607 }
608 } else {
609 dri_bo_unreference(brw->wm.surf_bo[j]);
610 brw->wm.surf_bo[j] = NULL;
611 }
612 }
613
614 /* Update surface for fragment shader constant buffer */
615 {
616 const GLuint j = BRW_WM_MAX_SURF - 1;
617 const struct brw_fragment_program *fp =
618 brw_fragment_program_const(brw->fragment_program);
619
620 brw_update_constant_surface(ctx, fp);
621 brw->wm.nr_surfaces = j + 1;
622 }
623
624
625 dri_bo_unreference(brw->wm.bind_bo);
626 brw->wm.bind_bo = brw_wm_get_binding_table(brw);
627
628 if (brw->wm.nr_surfaces != old_nr_surfaces)
629 brw->state.dirty.brw |= BRW_NEW_NR_SURFACES;
630 }
631
632
633 const struct brw_tracked_state brw_wm_surfaces = {
634 .dirty = {
635 .mesa = _NEW_COLOR | _NEW_TEXTURE | _NEW_BUFFERS,
636 .brw = BRW_NEW_CONTEXT,
637 .cache = 0
638 },
639 .prepare = prepare_wm_surfaces,
640 };
641
642
643