src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/samplerobj.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_state.h"
  44 #include "brw_defines.h"
  45 #include "brw_wm.h"
  46
  47 GLuint
  48 translate_tex_target(GLenum target)
  49 {
  50    switch (target) {
  51    case GL_TEXTURE_1D:
  52    case GL_TEXTURE_1D_ARRAY_EXT:
  53       return BRW_SURFACE_1D;
  54
  55    case GL_TEXTURE_RECTANGLE_NV:
  56       return BRW_SURFACE_2D;
  57
  58    case GL_TEXTURE_2D:
  59    case GL_TEXTURE_2D_ARRAY_EXT:
  60       return BRW_SURFACE_2D;
  61
  62    case GL_TEXTURE_3D:
  63       return BRW_SURFACE_3D;
  64
  65    case GL_TEXTURE_CUBE_MAP:
  66       return BRW_SURFACE_CUBE;
  67
  68    default:
  69       assert(0);
  70       return 0;
  71    }
  72 }
  73
  74 uint32_t
  75 brw_format_for_mesa_format(gl_format mesa_format)
  76 {
  77    static const uint32_t table[MESA_FORMAT_COUNT] =
  78    {
  79       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
  80       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
  81       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
  82       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
  83       [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
  84       [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
  85       [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
  86       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
  87       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
  88       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
  89       [MESA_FORMAT_RG88] = BRW_SURFACEFORMAT_R8G8_UNORM,
  90       [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
  91       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
  92       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
  93       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
  94       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
  95       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
  96       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
  97       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
  98       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
  99       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
 100       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
 101       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
 102       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 103       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 104       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 105       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 106       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 107       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 108       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 109       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 110       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 111       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 112       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 113       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 114       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 115       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 116       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 117       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 118       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 119       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 120       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 121       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 122       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 123       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 124       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 125       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 126       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 127       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 128       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 129       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 130    };
 131    assert(mesa_format < MESA_FORMAT_COUNT);
 132    return table[mesa_format];
 133 }
 134
 135 bool
 136 brw_render_target_supported(gl_format format)
 137 {
 138    /* These are not color render targets like the table holds, but we
 139     * ask the question for FBO completeness.
 140     */
 141    if (format == MESA_FORMAT_S8_Z24 ||
 142        format == MESA_FORMAT_X8_Z24 ||
 143        format == MESA_FORMAT_S8 ||
 144        format == MESA_FORMAT_Z16) {
 145       return true;
 146    }
 147
 148    /* The value of this BRW_SURFACEFORMAT is 0, so hardcode it.
 149     */
 150    if (format == MESA_FORMAT_RGBA_FLOAT32)
 151       return true;
 152
 153    /* Not exactly true, as some of those formats are not renderable.
 154     * But at least we know how to translate them.
 155     */
 156    return brw_format_for_mesa_format(format) != 0;
 157 }
 158
 159 GLuint
 160 translate_tex_format(gl_format mesa_format,
 161                      GLenum internal_format,
 162                      GLenum depth_mode,
 163                      GLenum srgb_decode)
 164 {
 165    switch( mesa_format ) {
 166
 167    case MESA_FORMAT_Z16:
 168       if (depth_mode == GL_INTENSITY)
 169           return BRW_SURFACEFORMAT_I16_UNORM;
 170       else if (depth_mode == GL_ALPHA)
 171           return BRW_SURFACEFORMAT_A16_UNORM;
 172       else if (depth_mode == GL_RED)
 173           return BRW_SURFACEFORMAT_R16_UNORM;
 174       else
 175           return BRW_SURFACEFORMAT_L16_UNORM;
 176
 177    case MESA_FORMAT_S8_Z24:
 178    case MESA_FORMAT_X8_Z24:
 179       /* XXX: these different surface formats don't seem to
 180        * make any difference for shadow sampler/compares.
 181        */
 182       if (depth_mode == GL_INTENSITY)
 183          return BRW_SURFACEFORMAT_I24X8_UNORM;
 184       else if (depth_mode == GL_ALPHA)
 185          return BRW_SURFACEFORMAT_A24X8_UNORM;
 186       else if (depth_mode == GL_RED)
 187          return BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS;
 188       else
 189          return BRW_SURFACEFORMAT_L24X8_UNORM;
 190
 191    case MESA_FORMAT_SARGB8:
 192    case MESA_FORMAT_SLA8:
 193    case MESA_FORMAT_SL8:
 194       if (srgb_decode == GL_DECODE_EXT)
 195          return brw_format_for_mesa_format(mesa_format);
 196       else if (srgb_decode == GL_SKIP_DECODE_EXT)
 197          return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
 198
 199    case MESA_FORMAT_RGBA8888_REV:
 200       /* This format is not renderable? */
 201       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 202
 203    case MESA_FORMAT_RGBA_FLOAT32:
 204       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 205        * assertion below.
 206        */
 207       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 208
 209    default:
 210       assert(brw_format_for_mesa_format(mesa_format) != 0);
 211       return brw_format_for_mesa_format(mesa_format);
 212    }
 213 }
 214
 215 static uint32_t
 216 brw_get_surface_tiling_bits(uint32_t tiling)
 217 {
 218    switch (tiling) {
 219    case I915_TILING_X:
 220       return BRW_SURFACE_TILED;
 221    case I915_TILING_Y:
 222       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 223    default:
 224       return 0;
 225    }
 226 }
 227
 228 static void
 229 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 230 {
 231    struct brw_context *brw = brw_context(ctx);
 232    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 233    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 234    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 235    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 236    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 237    uint32_t *surf;
 238    int width, height, depth;
 239
 240    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 241
 242    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 243                           6 * 4, 32, &brw->wm.surf_offset[surf_index]);
 244
 245    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 246               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 247               BRW_SURFACE_CUBEFACE_ENABLES |
 248               (translate_tex_format(firstImage->TexFormat,
 249                                     firstImage->InternalFormat,
 250                                     sampler->DepthMode,
 251                                     sampler->sRGBDecode) <<
 252                BRW_SURFACE_FORMAT_SHIFT));
 253
 254    surf[1] = intelObj->mt->region->bo->offset; /* reloc */
 255
 256    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 257               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 258               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 259
 260    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 261               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 262               ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
 263               BRW_SURFACE_PITCH_SHIFT);
 264
 265    surf[4] = 0;
 266    surf[5] = 0;
 267
 268    /* Emit relocation to surface contents */
 269    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 270                            brw->wm.surf_offset[surf_index] + 4,
 271                            intelObj->mt->region->bo, 0,
 272                            I915_GEM_DOMAIN_SAMPLER, 0);
 273 }
 274
 275 /**
 276  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 277  * read from this buffer with Data Port Read instructions/messages.
 278  */
 279 void
 280 brw_create_constant_surface(struct brw_context *brw,
 281                             drm_intel_bo *bo,
 282                             int width,
 283                             uint32_t *out_offset)
 284 {
 285    struct intel_context *intel = &brw->intel;
 286    const GLint w = width - 1;
 287    uint32_t *surf;
 288
 289    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 290                           6 * 4, 32, out_offset);
 291
 292    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 293               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 294               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 295
 296    if (intel->gen >= 6)
 297       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 298
 299    surf[1] = bo->offset; /* reloc */
 300
 301    surf[2] = (((w & 0x7f) - 1) << BRW_SURFACE_WIDTH_SHIFT |
 302               (((w >> 7) & 0x1fff) - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 303
 304    surf[3] = ((((w >> 20) & 0x7f) - 1) << BRW_SURFACE_DEPTH_SHIFT |
 305               (width * 16 - 1) << BRW_SURFACE_PITCH_SHIFT);
 306
 307    surf[4] = 0;
 308    surf[5] = 0;
 309
 310    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 311     * bspec ("Data Cache") says that the data cache does not exist as
 312     * a separate cache and is just the sampler cache.
 313     */
 314    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 315                            *out_offset + 4,
 316                            bo, 0,
 317                            I915_GEM_DOMAIN_SAMPLER, 0);
 318 }
 319
 320 /* Creates a new WM constant buffer reflecting the current fragment program's
 321  * constants, if needed by the fragment program.
 322  *
 323  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 324  * state atom.
 325  */
 326 static void
 327 brw_upload_wm_pull_constants(struct brw_context *brw)
 328 {
 329    struct gl_context *ctx = &brw->intel.ctx;
 330    struct intel_context *intel = &brw->intel;
 331    struct brw_fragment_program *fp =
 332       (struct brw_fragment_program *) brw->fragment_program;
 333    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 334    float *constants;
 335    unsigned int i;
 336
 337    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
 338
 339    /* BRW_NEW_FRAGMENT_PROGRAM */
 340    if (brw->wm.prog_data->nr_pull_params == 0) {
 341       if (brw->wm.const_bo) {
 342          drm_intel_bo_unreference(brw->wm.const_bo);
 343          brw->wm.const_bo = NULL;
 344          brw->state.dirty.brw |= BRW_NEW_WM_CONSTBUF;
 345       }
 346       return;
 347    }
 348
 349    drm_intel_bo_unreference(brw->wm.const_bo);
 350    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
 351                                          size, 64);
 352
 353    /* _NEW_PROGRAM_CONSTANTS */
 354    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
 355    constants = brw->wm.const_bo->virtual;
 356    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 357       constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
 358                                    brw->wm.prog_data->pull_param[i]);
 359    }
 360    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 361
 362    brw->state.dirty.brw |= BRW_NEW_WM_CONSTBUF;
 363 }
 364
 365 const struct brw_tracked_state brw_wm_constants = {
 366    .dirty = {
 367       .mesa = (_NEW_PROGRAM_CONSTANTS),
 368       .brw = (BRW_NEW_FRAGMENT_PROGRAM),
 369       .cache = 0
 370    },
 371    .emit = brw_upload_wm_pull_constants,
 372 };
 373
 374 /**
 375  * Updates surface / buffer for fragment shader constant buffer, if
 376  * one is required.
 377  *
 378  * This consumes the state updates for the constant buffer, and produces
 379  * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
 380  * inclusion in the binding table.
 381  */
 382 static void upload_wm_constant_surface(struct brw_context *brw )
 383 {
 384    GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
 385    struct brw_fragment_program *fp =
 386       (struct brw_fragment_program *) brw->fragment_program;
 387    const struct gl_program_parameter_list *params =
 388       fp->program.Base.Parameters;
 389
 390    /* If there's no constant buffer, then no surface BO is needed to point at
 391     * it.
 392     */
 393    if (brw->wm.const_bo == 0) {
 394       if (brw->wm.surf_offset[surf]) {
 395          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 396          brw->wm.surf_offset[surf] = 0;
 397       }
 398       return;
 399    }
 400
 401    brw_create_constant_surface(brw, brw->wm.const_bo, params->NumParameters,
 402                                &brw->wm.surf_offset[surf]);
 403    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 404 }
 405
 406 const struct brw_tracked_state brw_wm_constant_surface = {
 407    .dirty = {
 408       .mesa = 0,
 409       .brw = (BRW_NEW_WM_CONSTBUF |
 410               BRW_NEW_BATCH),
 411       .cache = 0
 412    },
 413    .emit = upload_wm_constant_surface,
 414 };
 415
 416 static void
 417 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 418 {
 419    struct intel_context *intel = &brw->intel;
 420    uint32_t *surf;
 421
 422    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 423                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 424
 425    surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 426               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
 427    if (intel->gen < 6) {
 428       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
 429                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
 430                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
 431                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
 432    }
 433    surf[1] = 0;
 434    surf[2] = 0;
 435    surf[3] = 0;
 436    surf[4] = 0;
 437    surf[5] = 0;
 438 }
 439
 440 /**
 441  * Sets up a surface state structure to point at the given region.
 442  * While it is only used for the front/back buffer currently, it should be
 443  * usable for further buffers when doing ARB_draw_buffer support.
 444  */
 445 static void
 446 brw_update_renderbuffer_surface(struct brw_context *brw,
 447                                 struct gl_renderbuffer *rb,
 448                                 unsigned int unit)
 449 {
 450    struct intel_context *intel = &brw->intel;
 451    struct gl_context *ctx = &intel->ctx;
 452    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 453    struct intel_region *region = irb->region;
 454    uint32_t *surf;
 455    uint32_t tile_x, tile_y;
 456    uint32_t format = 0;
 457
 458    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 459                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 460
 461    switch (irb->Base.Format) {
 462    case MESA_FORMAT_XRGB8888:
 463       /* XRGB is handled as ARGB because the chips in this family
 464        * cannot render to XRGB targets.  This means that we have to
 465        * mask writes to alpha (ala glColorMask) and reconfigure the
 466        * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 467        * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 468        * used.
 469        */
 470       format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 471       break;
 472    case MESA_FORMAT_INTENSITY_FLOAT32:
 473    case MESA_FORMAT_LUMINANCE_FLOAT32:
 474       /* For these formats, we just need to read/write the first
 475        * channel into R, which is to say that we just treat them as
 476        * GL_RED.
 477        */
 478       format = BRW_SURFACEFORMAT_R32_FLOAT;
 479       break;
 480    case MESA_FORMAT_SARGB8:
 481       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 482          surfaces to the blend/update as sRGB */
 483       if (ctx->Color.sRGBEnabled)
 484          format = brw_format_for_mesa_format(irb->Base.Format);
 485       else
 486          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 487       break;
 488    default:
 489       assert(brw_render_target_supported(irb->Base.Format));
 490       format = brw_format_for_mesa_format(irb->Base.Format);
 491    }
 492
 493    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 494               format << BRW_SURFACE_FORMAT_SHIFT);
 495
 496    /* reloc */
 497    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
 498               region->bo->offset);
 499
 500    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 501               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 502
 503    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
 504               ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
 505
 506    surf[4] = 0;
 507
 508    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 509    /* Note that the low bits of these fields are missing, so
 510     * there's the possibility of getting in trouble.
 511     */
 512    assert(tile_x % 4 == 0);
 513    assert(tile_y % 2 == 0);
 514    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 515               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT);
 516
 517    if (intel->gen < 6) {
 518       /* _NEW_COLOR */
 519       if (!ctx->Color.ColorLogicOpEnabled &&
 520           (ctx->Color.BlendEnabled & (1 << unit)))
 521          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
 522
 523       if (!ctx->Color.ColorMask[unit][0])
 524          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
 525       if (!ctx->Color.ColorMask[unit][1])
 526          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
 527       if (!ctx->Color.ColorMask[unit][2])
 528          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
 529
 530       /* As mentioned above, disable writes to the alpha component when the
 531        * renderbuffer is XRGB.
 532        */
 533       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
 534           !ctx->Color.ColorMask[unit][3]) {
 535          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
 536       }
 537    }
 538
 539    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 540                            brw->wm.surf_offset[unit] + 4,
 541                            region->bo,
 542                            surf[1] - region->bo->offset,
 543                            I915_GEM_DOMAIN_RENDER,
 544                            I915_GEM_DOMAIN_RENDER);
 545 }
 546
 547 /**
 548  * Constructs the set of surface state objects pointed to by the
 549  * binding table.
 550  */
 551 static void
 552 brw_upload_wm_surfaces(struct brw_context *brw)
 553 {
 554    struct gl_context *ctx = &brw->intel.ctx;
 555    GLuint i;
 556    int nr_surfaces = 0;
 557
 558    /* _NEW_BUFFERS | _NEW_COLOR */
 559    /* Update surfaces for drawing buffers */
 560    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 561       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 562          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
 563             brw_update_renderbuffer_surface(brw,
 564                                             ctx->DrawBuffer->_ColorDrawBuffers[i],
 565                                             i);
 566          } else {
 567             brw_update_null_renderbuffer_surface(brw, i);
 568          }
 569       }
 570       nr_surfaces = SURF_INDEX_DRAW(ctx->DrawBuffer->_NumColorDrawBuffers);
 571    } else {
 572       brw_update_null_renderbuffer_surface(brw, 0);
 573       nr_surfaces = SURF_INDEX_DRAW(0) + 1;
 574    }
 575
 576    /* BRW_NEW_WM_CONSTBUF */
 577    if (brw->wm.const_bo) {
 578       nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
 579    }
 580
 581    /* Update surfaces for textures */
 582    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 583       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 584       const GLuint surf = SURF_INDEX_TEXTURE(i);
 585
 586       /* _NEW_TEXTURE */
 587       if (texUnit->_ReallyEnabled) {
 588          brw_update_texture_surface(ctx, i);
 589          nr_surfaces = SURF_INDEX_TEXTURE(i) + 1;
 590       } else {
 591          brw->wm.surf_offset[surf] = 0;
 592       }
 593    }
 594
 595    if (brw->wm.nr_surfaces != nr_surfaces) {
 596       brw->wm.nr_surfaces = nr_surfaces;
 597       brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
 598    }
 599
 600    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 601 }
 602
 603 const struct brw_tracked_state brw_wm_surfaces = {
 604    .dirty = {
 605       .mesa = (_NEW_COLOR |
 606                _NEW_TEXTURE |
 607                _NEW_BUFFERS),
 608       .brw = (BRW_NEW_BATCH |
 609               BRW_NEW_WM_CONSTBUF),
 610       .cache = 0
 611    },
 612    .emit = brw_upload_wm_surfaces,
 613 };
 614
 615 /**
 616  * Constructs the binding table for the WM surface state, which maps unit
 617  * numbers to surface state objects.
 618  */
 619 static void
 620 brw_wm_upload_binding_table(struct brw_context *brw)
 621 {
 622    uint32_t *bind;
 623    int i;
 624
 625    /* Might want to calculate nr_surfaces first, to avoid taking up so much
 626     * space for the binding table.
 627     */
 628    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
 629                           sizeof(uint32_t) * BRW_WM_MAX_SURF,
 630                           32, &brw->wm.bind_bo_offset);
 631
 632    for (i = 0; i < BRW_WM_MAX_SURF; i++) {
 633       /* BRW_NEW_WM_SURFACES */
 634       bind[i] = brw->wm.surf_offset[i];
 635    }
 636
 637    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
 638 }
 639
 640 const struct brw_tracked_state brw_wm_binding_table = {
 641    .dirty = {
 642       .mesa = 0,
 643       .brw = (BRW_NEW_BATCH |
 644               BRW_NEW_WM_SURFACES),
 645       .cache = 0
 646    },
 647    .emit = brw_wm_upload_binding_table,
 648 };