projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
i965: Add support for ARGB2101010 rendering.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_surface_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/mtypes.h"
34 #include "main/samplerobj.h"
35 #include "program/prog_parameter.h"
36
37 #include "intel_mipmap_tree.h"
38 #include "intel_batchbuffer.h"
39 #include "intel_tex.h"
40 #include "intel_fbo.h"
41
42 #include "brw_context.h"
43 #include "brw_state.h"
44 #include "brw_defines.h"
45 #include "brw_wm.h"
46
47 GLuint
48 translate_tex_target(GLenum target)
49 {
50 switch (target) {
51 case GL_TEXTURE_1D:
52 case GL_TEXTURE_1D_ARRAY_EXT:
53 return BRW_SURFACE_1D;
54
55 case GL_TEXTURE_RECTANGLE_NV:
56 return BRW_SURFACE_2D;
57
58 case GL_TEXTURE_2D:
59 case GL_TEXTURE_2D_ARRAY_EXT:
60 return BRW_SURFACE_2D;
61
62 case GL_TEXTURE_3D:
63 return BRW_SURFACE_3D;
64
65 case GL_TEXTURE_CUBE_MAP:
66 return BRW_SURFACE_CUBE;
67
68 default:
69 assert(0);
70 return 0;
71 }
72 }
73
74 struct surface_format_info {
75 bool exists;
76 int sampling;
77 int filtering;
78 int shadow_compare;
79 int chroma_key;
80 int render_target;
81 int alpha_blend;
82 int input_vb;
83 int streamed_output_vb;
84 int color_processing;
85 };
86
87 /* This macro allows us to write the table almost as it appears in the PRM,
88 * while restructuring it to turn it into the C code we want.
89 */
90 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
91 [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
92
93 #define Y 0
94 #define x 999
95 /**
96 * This is the table of support for surface (texture, renderbuffer, and vertex
97 * buffer, but not depthbuffer) formats across the various hardware generations.
98 *
99 * The table is formatted to match the documentation, except that the docs have
100 * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever". To put
101 * it in our table, here's the mapping:
102 *
103 * Y*: 45
104 * Y+: 45 (g45/gm45)
105 * Y~: 50 (gen5)
106 * Y^: 60 (gen6)
107 * Y#: 70 (gen7)
108 *
109 * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
110 */
111 const struct surface_format_info surface_formats[] = {
112 /* smpl filt shad CK RT AB VB SO color */
113 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
114 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
115 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
116 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
117 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
118 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64_FLOAT)
119 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
120 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
121 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
122 SF( Y, 50, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
123 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_SINT)
124 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_UINT)
125 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
126 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
127 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
128 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
129 SF( Y, Y, x, x, Y, 45, Y, x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
130 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
131 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
132 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
133 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
134 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32_FLOAT)
135 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_SINT)
136 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_UINT)
137 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
138 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
139 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32A32_FLOAT)
140 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_UNORM)
141 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SNORM)
142 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64_FLOAT)
143 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
144 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
145 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32X32_FLOAT)
146 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32X32_FLOAT)
147 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32X32_FLOAT)
148 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
149 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
150 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SSCALED)
151 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_USCALED)
152 SF( Y, Y, x, Y, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
153 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
154 /* smpl filt shad CK RT AB VB SO color */
155 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
156 SF( Y, Y, x, x, x, x, x, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
157 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
158 SF( Y, Y, x, x, x, Y, Y, x, x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
159 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
160 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
161 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
162 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
163 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
164 SF( Y, Y, x, x, Y, 45, Y, x, x, BRW_SURFACEFORMAT_R16G16_UNORM)
165 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16_SNORM)
166 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SINT)
167 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_UINT)
168 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16_FLOAT)
169 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
170 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
171 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
172 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_SINT)
173 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_UINT)
174 SF( Y, 50, Y, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32_FLOAT)
175 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
176 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
177 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_UNORM)
178 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I24X8_UNORM)
179 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L24X8_UNORM)
180 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A24X8_UNORM)
181 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32_FLOAT)
182 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32_FLOAT)
183 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32_FLOAT)
184 SF( Y, Y, x, Y, x, x, x, x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
185 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
186 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
187 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
188 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
189 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
190 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_FLOAT)
191 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_UNORM)
192 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SNORM)
193 /* smpl filt shad CK RT AB VB SO color */
194 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
195 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
196 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
197 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SSCALED)
198 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_USCALED)
199 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SSCALED)
200 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_USCALED)
201 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
202 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
203 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
204 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
205 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
206 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
207 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8G8_UNORM)
208 SF( Y, Y, x, Y, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8_SNORM)
209 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SINT)
210 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_UINT)
211 SF( Y, Y, Y, x, Y, 45, Y, x, 70, BRW_SURFACEFORMAT_R16_UNORM)
212 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16_SNORM)
213 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_SINT)
214 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_UINT)
215 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16_FLOAT)
216 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_UNORM)
217 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_UNORM)
218 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_UNORM)
219 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM)
220 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_FLOAT)
221 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_FLOAT)
222 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_FLOAT)
223 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
224 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
225 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
226 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
227 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SSCALED)
228 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_USCALED)
229 /* smpl filt shad CK RT AB VB SO color */
230 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_SSCALED)
231 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_USCALED)
232 SF( Y, Y, x, 45, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8_UNORM)
233 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8_SNORM)
234 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_SINT)
235 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_UINT)
236 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_A8_UNORM)
237 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_UNORM)
238 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM)
239 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P4A4_UNORM)
240 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4P4_UNORM)
241 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_SSCALED)
242 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_USCALED)
243 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
244 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
245 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R1_UINT)
246 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
247 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
248 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM)
249 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM)
250 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM)
251 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_UNORM)
252 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_UNORM)
253 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
254 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
255 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
256 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_MONO8)
257 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
258 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
259 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB)
260 /* smpl filt shad CK RT AB VB SO color */
261 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_FXT1)
262 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
263 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
264 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
265 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
266 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
267 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
268 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_SNORM)
269 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_SNORM)
270 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
271 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
272 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
273 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
274 };
275 #undef x
276 #undef Y
277
278 uint32_t
279 brw_format_for_mesa_format(gl_format mesa_format)
280 {
281 /* This table is ordered according to the enum ordering in formats.h. We do
282 * expect that enum to be extended without our explicit initialization
283 * staying in sync, so we initialize to 0 even though
284 * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
285 */
286 static const uint32_t table[MESA_FORMAT_COUNT] =
287 {
288 [MESA_FORMAT_RGBA8888] = 0,
289 [MESA_FORMAT_RGBA8888_REV] = 0,
290 [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
291 [MESA_FORMAT_ARGB8888_REV] = 0,
292 [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
293 [MESA_FORMAT_XRGB8888_REV] = 0,
294 [MESA_FORMAT_RGB888] = 0,
295 [MESA_FORMAT_BGR888] = 0,
296 [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
297 [MESA_FORMAT_RGB565_REV] = 0,
298 [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
299 [MESA_FORMAT_ARGB4444_REV] = 0,
300 [MESA_FORMAT_RGBA5551] = 0,
301 [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
302 [MESA_FORMAT_ARGB1555_REV] = 0,
303 [MESA_FORMAT_AL44] = 0,
304 [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
305 [MESA_FORMAT_AL88_REV] = 0,
306 [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
307 [MESA_FORMAT_AL1616_REV] = 0,
308 [MESA_FORMAT_RGB332] = 0,
309 [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
310 [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
311 [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
312 [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
313 [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
314 [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
315 [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
316 [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
317 [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
318 [MESA_FORMAT_RG88] = BRW_SURFACEFORMAT_R8G8_UNORM,
319 [MESA_FORMAT_RG88_REV] = 0,
320 [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
321 [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
322 [MESA_FORMAT_RG1616_REV] = 0,
323 [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
324 [MESA_FORMAT_Z24_S8] = 0,
325 [MESA_FORMAT_S8_Z24] = 0,
326 [MESA_FORMAT_Z16] = 0,
327 [MESA_FORMAT_X8_Z24] = 0,
328 [MESA_FORMAT_Z24_S8] = 0,
329 [MESA_FORMAT_Z32] = 0,
330 [MESA_FORMAT_S8] = 0,
331
332 [MESA_FORMAT_SRGB8] = 0,
333 [MESA_FORMAT_SRGBA8] = 0,
334 [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
335 [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
336 [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
337 [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
338 [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
339 [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
340 [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
341
342 [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
343 [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
344 [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
345 [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
346 [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
347 [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
348
349 [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
350 [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
351 [MESA_FORMAT_RGB_FLOAT32] = 0,
352 [MESA_FORMAT_RGB_FLOAT16] = 0,
353 [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
354 [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
355 [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
356 [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
357 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
358 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
359 [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
360 [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
361 [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
362 [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
363 [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
364 [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
365
366 [MESA_FORMAT_ALPHA_UINT8] = 0,
367 [MESA_FORMAT_ALPHA_UINT16] = 0,
368 [MESA_FORMAT_ALPHA_UINT32] = 0,
369 [MESA_FORMAT_ALPHA_INT8] = 0,
370 [MESA_FORMAT_ALPHA_INT16] = 0,
371 [MESA_FORMAT_ALPHA_INT32] = 0,
372
373 [MESA_FORMAT_INTENSITY_UINT8] = 0,
374 [MESA_FORMAT_INTENSITY_UINT16] = 0,
375 [MESA_FORMAT_INTENSITY_UINT32] = 0,
376 [MESA_FORMAT_INTENSITY_INT8] = 0,
377 [MESA_FORMAT_INTENSITY_INT16] = 0,
378 [MESA_FORMAT_INTENSITY_INT32] = 0,
379
380 [MESA_FORMAT_LUMINANCE_UINT8] = 0,
381 [MESA_FORMAT_LUMINANCE_UINT16] = 0,
382 [MESA_FORMAT_LUMINANCE_UINT32] = 0,
383 [MESA_FORMAT_LUMINANCE_INT8] = 0,
384 [MESA_FORMAT_LUMINANCE_INT16] = 0,
385 [MESA_FORMAT_LUMINANCE_INT32] = 0,
386
387 [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
388 [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
389 [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
390 [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
391 [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
392 [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
393
394 [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
395 [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
396 [MESA_FORMAT_RGB_INT8] = 0,
397 [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
398 [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
399 [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
400 [MESA_FORMAT_RGB_INT16] = 0,
401 [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
402 [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
403 [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
404 [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
405 [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
406
407 [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
408 [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
409 [MESA_FORMAT_RGB_UINT8] = 0,
410 [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
411 [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
412 [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
413 [MESA_FORMAT_RGB_UINT16] = 0,
414 [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
415 [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
416 [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
417 [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
418 [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
419
420 [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
421 [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
422 [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
423 [MESA_FORMAT_SIGNED_RGBX8888] = 0,
424 [MESA_FORMAT_SIGNED_RGBA8888] = 0,
425 [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
426 [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
427 [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
428 [MESA_FORMAT_SIGNED_RGB_16] = 0,
429 [MESA_FORMAT_SIGNED_RGBA_16] = 0,
430 [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
431
432 [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
433 [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
434 [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
435 [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
436
437 [MESA_FORMAT_L_LATC1] = 0,
438 [MESA_FORMAT_SIGNED_L_LATC1] = 0,
439 [MESA_FORMAT_LA_LATC2] = 0,
440 [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
441
442 [MESA_FORMAT_SIGNED_A8] = 0,
443 [MESA_FORMAT_SIGNED_L8] = 0,
444 [MESA_FORMAT_SIGNED_AL88] = 0,
445 [MESA_FORMAT_SIGNED_I8] = 0,
446 [MESA_FORMAT_SIGNED_A16] = 0,
447 [MESA_FORMAT_SIGNED_L16] = 0,
448 [MESA_FORMAT_SIGNED_AL1616] = 0,
449 [MESA_FORMAT_SIGNED_I16] = 0,
450
451 [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
452 [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
453
454 [MESA_FORMAT_Z32_FLOAT] = 0,
455 [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
456 };
457 assert(mesa_format < MESA_FORMAT_COUNT);
458 return table[mesa_format];
459 }
460
461 void
462 brw_init_surface_formats(struct brw_context *brw)
463 {
464 struct intel_context *intel = &brw->intel;
465 struct gl_context *ctx = &intel->ctx;
466 int gen;
467 gl_format format;
468
469 gen = intel->gen * 10;
470 if (intel->is_g4x)
471 gen += 5;
472
473 for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
474 uint32_t texture, render;
475 const struct surface_format_info *rinfo, *tinfo;
476 bool is_integer = _mesa_is_format_integer_color(format);
477
478 render = texture = brw_format_for_mesa_format(format);
479 tinfo = &surface_formats[texture];
480
481 /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
482 * it.
483 */
484 if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
485 continue;
486
487 if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
488 ctx->TextureFormatSupported[format] = true;
489
490 /* Re-map some render target formats to make them supported when they
491 * wouldn't be using their format for texturing.
492 */
493 switch (render) {
494 /* For these formats, we just need to read/write the first
495 * channel into R, which is to say that we just treat them as
496 * GL_RED.
497 */
498 case BRW_SURFACEFORMAT_I32_FLOAT:
499 case BRW_SURFACEFORMAT_L32_FLOAT:
500 render = BRW_SURFACEFORMAT_R32_FLOAT;
501 break;
502 case BRW_SURFACEFORMAT_I16_FLOAT:
503 case BRW_SURFACEFORMAT_L16_FLOAT:
504 render = BRW_SURFACEFORMAT_R16_FLOAT;
505 break;
506 case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
507 /* XRGB is handled as ARGB because the chips in this family
508 * cannot render to XRGB targets. This means that we have to
509 * mask writes to alpha (ala glColorMask) and reconfigure the
510 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
511 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
512 * used.
513 */
514 render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
515 break;
516 }
517
518 rinfo = &surface_formats[render];
519
520 /* Note that GL_EXT_texture_integer says that blending doesn't occur for
521 * integer, so we don't need hardware support for blending on it. Other
522 * than that, GL in general requires alpha blending for render targets,
523 * even though we don't support it for some formats.
524 *
525 * We don't currently support rendering to SNORM textures because some of
526 * the ARB_color_buffer_float clamping is broken for it
527 * (piglit arb_color_buffer_float-drawpixels GL_RGBA8_SNORM).
528 */
529 if (gen >= rinfo->render_target &&
530 (gen >= rinfo->alpha_blend || is_integer) &&
531 _mesa_get_format_datatype(format) != GL_SIGNED_NORMALIZED) {
532 brw->render_target_format[format] = render;
533 brw->format_supported_as_render_target[format] = true;
534 }
535 }
536
537 /* We will check this table for FBO completeness, but the surface format
538 * table above only covered color rendering.
539 */
540 brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
541 brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
542 brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
543 brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
544
545 /* We remap depth formats to a supported texturing format in
546 * translate_tex_format().
547 */
548 ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
549 ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
550 }
551
552 bool
553 brw_render_target_supported(struct intel_context *intel, gl_format format)
554 {
555 struct brw_context *brw = brw_context(&intel->ctx);
556 /* Not exactly true, as some of those formats are not renderable.
557 * But at least we know how to translate them.
558 */
559 return brw->format_supported_as_render_target[format];
560 }
561
562 GLuint
563 translate_tex_format(gl_format mesa_format,
564 GLenum internal_format,
565 GLenum depth_mode,
566 GLenum srgb_decode)
567 {
568 switch( mesa_format ) {
569
570 case MESA_FORMAT_Z16:
571 if (depth_mode == GL_INTENSITY)
572 return BRW_SURFACEFORMAT_I16_UNORM;
573 else if (depth_mode == GL_ALPHA)
574 return BRW_SURFACEFORMAT_A16_UNORM;
575 else if (depth_mode == GL_RED)
576 return BRW_SURFACEFORMAT_R16_UNORM;
577 else
578 return BRW_SURFACEFORMAT_L16_UNORM;
579
580 case MESA_FORMAT_S8_Z24:
581 case MESA_FORMAT_X8_Z24:
582 /* XXX: these different surface formats don't seem to
583 * make any difference for shadow sampler/compares.
584 */
585 if (depth_mode == GL_INTENSITY)
586 return BRW_SURFACEFORMAT_I24X8_UNORM;
587 else if (depth_mode == GL_ALPHA)
588 return BRW_SURFACEFORMAT_A24X8_UNORM;
589 else if (depth_mode == GL_RED)
590 return BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS;
591 else
592 return BRW_SURFACEFORMAT_L24X8_UNORM;
593
594 case MESA_FORMAT_SARGB8:
595 case MESA_FORMAT_SLA8:
596 case MESA_FORMAT_SL8:
597 if (srgb_decode == GL_DECODE_EXT)
598 return brw_format_for_mesa_format(mesa_format);
599 else if (srgb_decode == GL_SKIP_DECODE_EXT)
600 return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
601
602 case MESA_FORMAT_RGBA8888_REV:
603 /* This format is not renderable? */
604 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
605
606 case MESA_FORMAT_RGBA_FLOAT32:
607 /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
608 * assertion below.
609 */
610 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
611
612 default:
613 assert(brw_format_for_mesa_format(mesa_format) != 0);
614 return brw_format_for_mesa_format(mesa_format);
615 }
616 }
617
618 static uint32_t
619 brw_get_surface_tiling_bits(uint32_t tiling)
620 {
621 switch (tiling) {
622 case I915_TILING_X:
623 return BRW_SURFACE_TILED;
624 case I915_TILING_Y:
625 return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
626 default:
627 return 0;
628 }
629 }
630
631 static void
632 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
633 {
634 struct brw_context *brw = brw_context(ctx);
635 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
636 struct intel_texture_object *intelObj = intel_texture_object(tObj);
637 struct intel_mipmap_tree *mt = intelObj->mt;
638 struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
639 struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
640 const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
641 uint32_t *surf;
642 int width, height, depth;
643
644 intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
645
646 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
647 6 * 4, 32, &brw->bind.surf_offset[surf_index]);
648
649 surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
650 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
651 BRW_SURFACE_CUBEFACE_ENABLES |
652 (translate_tex_format(firstImage->TexFormat,
653 firstImage->InternalFormat,
654 sampler->DepthMode,
655 sampler->sRGBDecode) <<
656 BRW_SURFACE_FORMAT_SHIFT));
657
658 surf[1] = intelObj->mt->region->bo->offset; /* reloc */
659
660 surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
661 (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
662 (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
663
664 surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
665 (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
666 ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
667 BRW_SURFACE_PITCH_SHIFT);
668
669 surf[4] = 0;
670
671 surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
672
673 /* Emit relocation to surface contents */
674 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
675 brw->bind.surf_offset[surf_index] + 4,
676 intelObj->mt->region->bo, 0,
677 I915_GEM_DOMAIN_SAMPLER, 0);
678 }
679
680 /**
681 * Create the constant buffer surface. Vertex/fragment shader constants will be
682 * read from this buffer with Data Port Read instructions/messages.
683 */
684 void
685 brw_create_constant_surface(struct brw_context *brw,
686 drm_intel_bo *bo,
687 int width,
688 uint32_t *out_offset)
689 {
690 struct intel_context *intel = &brw->intel;
691 const GLint w = width - 1;
692 uint32_t *surf;
693
694 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
695 6 * 4, 32, out_offset);
696
697 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
698 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
699 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
700
701 if (intel->gen >= 6)
702 surf[0] |= BRW_SURFACE_RC_READ_WRITE;
703
704 surf[1] = bo->offset; /* reloc */
705
706 surf[2] = (((w & 0x7f) - 1) << BRW_SURFACE_WIDTH_SHIFT |
707 (((w >> 7) & 0x1fff) - 1) << BRW_SURFACE_HEIGHT_SHIFT);
708
709 surf[3] = ((((w >> 20) & 0x7f) - 1) << BRW_SURFACE_DEPTH_SHIFT |
710 (width * 16 - 1) << BRW_SURFACE_PITCH_SHIFT);
711
712 surf[4] = 0;
713 surf[5] = 0;
714
715 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
716 * bspec ("Data Cache") says that the data cache does not exist as
717 * a separate cache and is just the sampler cache.
718 */
719 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
720 *out_offset + 4,
721 bo, 0,
722 I915_GEM_DOMAIN_SAMPLER, 0);
723 }
724
725 /* Creates a new WM constant buffer reflecting the current fragment program's
726 * constants, if needed by the fragment program.
727 *
728 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
729 * state atom.
730 */
731 static void
732 brw_upload_wm_pull_constants(struct brw_context *brw)
733 {
734 struct gl_context *ctx = &brw->intel.ctx;
735 struct intel_context *intel = &brw->intel;
736 /* BRW_NEW_FRAGMENT_PROGRAM */
737 struct brw_fragment_program *fp =
738 (struct brw_fragment_program *) brw->fragment_program;
739 struct gl_program_parameter_list *params = fp->program.Base.Parameters;
740 const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
741 const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
742 float *constants;
743 unsigned int i;
744
745 _mesa_load_state_parameters(ctx, params);
746
747 /* CACHE_NEW_WM_PROG */
748 if (brw->wm.prog_data->nr_pull_params == 0) {
749 if (brw->wm.const_bo) {
750 drm_intel_bo_unreference(brw->wm.const_bo);
751 brw->wm.const_bo = NULL;
752 brw->bind.surf_offset[surf_index] = 0;
753 brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
754 }
755 return;
756 }
757
758 drm_intel_bo_unreference(brw->wm.const_bo);
759 brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
760 size, 64);
761
762 /* _NEW_PROGRAM_CONSTANTS */
763 drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
764 constants = brw->wm.const_bo->virtual;
765 for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
766 constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
767 brw->wm.prog_data->pull_param[i]);
768 }
769 drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
770
771 intel->vtbl.create_constant_surface(brw, brw->wm.const_bo,
772 params->NumParameters,
773 &brw->bind.surf_offset[surf_index]);
774
775 brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
776 }
777
778 const struct brw_tracked_state brw_wm_pull_constants = {
779 .dirty = {
780 .mesa = (_NEW_PROGRAM_CONSTANTS),
781 .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
782 .cache = CACHE_NEW_WM_PROG,
783 },
784 .emit = brw_upload_wm_pull_constants,
785 };
786
787 static void
788 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
789 {
790 struct intel_context *intel = &brw->intel;
791 uint32_t *surf;
792
793 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
794 6 * 4, 32, &brw->bind.surf_offset[unit]);
795
796 surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
797 BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
798 if (intel->gen < 6) {
799 surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
800 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
801 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
802 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
803 }
804 surf[1] = 0;
805 surf[2] = 0;
806 surf[3] = 0;
807 surf[4] = 0;
808 surf[5] = 0;
809 }
810
811 /**
812 * Sets up a surface state structure to point at the given region.
813 * While it is only used for the front/back buffer currently, it should be
814 * usable for further buffers when doing ARB_draw_buffer support.
815 */
816 static void
817 brw_update_renderbuffer_surface(struct brw_context *brw,
818 struct gl_renderbuffer *rb,
819 unsigned int unit)
820 {
821 struct intel_context *intel = &brw->intel;
822 struct gl_context *ctx = &intel->ctx;
823 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
824 struct intel_mipmap_tree *mt = irb->mt;
825 struct intel_region *region = irb->mt->region;
826 uint32_t *surf;
827 uint32_t tile_x, tile_y;
828 uint32_t format = 0;
829
830 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
831 6 * 4, 32, &brw->bind.surf_offset[unit]);
832
833 switch (irb->Base.Format) {
834 case MESA_FORMAT_SARGB8:
835 /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
836 surfaces to the blend/update as sRGB */
837 if (ctx->Color.sRGBEnabled)
838 format = brw_format_for_mesa_format(irb->Base.Format);
839 else
840 format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
841 break;
842 default:
843 format = brw->render_target_format[irb->Base.Format];
844 if (unlikely(!brw->format_supported_as_render_target[irb->Base.Format])) {
845 _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
846 __FUNCTION__, _mesa_get_format_name(irb->Base.Format));
847 }
848 break;
849 }
850
851 surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
852 format << BRW_SURFACE_FORMAT_SHIFT);
853
854 /* reloc */
855 surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
856 region->bo->offset);
857
858 surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
859 (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
860
861 surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
862 ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
863
864 surf[4] = 0;
865
866 assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
867 /* Note that the low bits of these fields are missing, so
868 * there's the possibility of getting in trouble.
869 */
870 assert(tile_x % 4 == 0);
871 assert(tile_y % 2 == 0);
872 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
873 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
874 (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
875
876 if (intel->gen < 6) {
877 /* _NEW_COLOR */
878 if (!ctx->Color.ColorLogicOpEnabled &&
879 (ctx->Color.BlendEnabled & (1 << unit)))
880 surf[0] |= BRW_SURFACE_BLEND_ENABLED;
881
882 if (!ctx->Color.ColorMask[unit][0])
883 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
884 if (!ctx->Color.ColorMask[unit][1])
885 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
886 if (!ctx->Color.ColorMask[unit][2])
887 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
888
889 /* As mentioned above, disable writes to the alpha component when the
890 * renderbuffer is XRGB.
891 */
892 if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
893 !ctx->Color.ColorMask[unit][3]) {
894 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
895 }
896 }
897
898 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
899 brw->bind.surf_offset[unit] + 4,
900 region->bo,
901 surf[1] - region->bo->offset,
902 I915_GEM_DOMAIN_RENDER,
903 I915_GEM_DOMAIN_RENDER);
904 }
905
906 /**
907 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
908 */
909 static void
910 brw_update_renderbuffer_surfaces(struct brw_context *brw)
911 {
912 struct intel_context *intel = &brw->intel;
913 struct gl_context *ctx = &brw->intel.ctx;
914 GLuint i;
915
916 /* _NEW_BUFFERS | _NEW_COLOR */
917 /* Update surfaces for drawing buffers */
918 if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
919 for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
920 if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
921 intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
922 } else {
923 intel->vtbl.update_null_renderbuffer_surface(brw, i);
924 }
925 }
926 } else {
927 intel->vtbl.update_null_renderbuffer_surface(brw, 0);
928 }
929 brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
930 }
931
932 const struct brw_tracked_state brw_renderbuffer_surfaces = {
933 .dirty = {
934 .mesa = (_NEW_COLOR |
935 _NEW_BUFFERS),
936 .brw = BRW_NEW_BATCH,
937 .cache = 0
938 },
939 .emit = brw_update_renderbuffer_surfaces,
940 };
941
942 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
943 .dirty = {
944 .mesa = _NEW_BUFFERS,
945 .brw = BRW_NEW_BATCH,
946 .cache = 0
947 },
948 .emit = brw_update_renderbuffer_surfaces,
949 };
950
951 /**
952 * Construct SURFACE_STATE objects for enabled textures.
953 */
954 static void
955 brw_update_texture_surfaces(struct brw_context *brw)
956 {
957 struct gl_context *ctx = &brw->intel.ctx;
958
959 for (unsigned i = 0; i < BRW_MAX_TEX_UNIT; i++) {
960 const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
961 const GLuint surf = SURF_INDEX_TEXTURE(i);
962
963 /* _NEW_TEXTURE */
964 if (texUnit->_ReallyEnabled) {
965 brw->intel.vtbl.update_texture_surface(ctx, i);
966 } else {
967 brw->bind.surf_offset[surf] = 0;
968 }
969 }
970
971 brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
972 }
973
974 const struct brw_tracked_state brw_texture_surfaces = {
975 .dirty = {
976 .mesa = _NEW_TEXTURE,
977 .brw = BRW_NEW_BATCH,
978 .cache = 0
979 },
980 .emit = brw_update_texture_surfaces,
981 };
982
983 /**
984 * Constructs the binding table for the WM surface state, which maps unit
985 * numbers to surface state objects.
986 */
987 static void
988 brw_upload_binding_table(struct brw_context *brw)
989 {
990 uint32_t *bind;
991 int i;
992
993 /* Might want to calculate nr_surfaces first, to avoid taking up so much
994 * space for the binding table.
995 */
996 bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
997 sizeof(uint32_t) * BRW_MAX_SURFACES,
998 32, &brw->bind.bo_offset);
999
1000 /* BRW_NEW_WM_SURFACES and BRW_NEW_VS_CONSTBUF */
1001 for (i = 0; i < BRW_MAX_SURFACES; i++) {
1002 bind[i] = brw->bind.surf_offset[i];
1003 }
1004
1005 brw->state.dirty.brw |= BRW_NEW_VS_BINDING_TABLE;
1006 brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1007 }
1008
1009 const struct brw_tracked_state brw_binding_table = {
1010 .dirty = {
1011 .mesa = 0,
1012 .brw = (BRW_NEW_BATCH |
1013 BRW_NEW_VS_CONSTBUF |
1014 BRW_NEW_WM_SURFACES),
1015 .cache = 0
1016 },
1017 .emit = brw_upload_binding_table,
1018 };
1019
1020 void
1021 gen4_init_vtable_surface_functions(struct brw_context *brw)
1022 {
1023 struct intel_context *intel = &brw->intel;
1024
1025 intel->vtbl.update_texture_surface = brw_update_texture_surface;
1026 intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1027 intel->vtbl.update_null_renderbuffer_surface =
1028 brw_update_null_renderbuffer_surface;
1029 intel->vtbl.create_constant_surface = brw_create_constant_surface;
1030 }