src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/context.h"
  34 #include "main/blend.h"
  35 #include "main/mtypes.h"
  36 #include "main/samplerobj.h"
  37 #include "program/prog_parameter.h"
  38
  39 #include "intel_mipmap_tree.h"
  40 #include "intel_batchbuffer.h"
  41 #include "intel_tex.h"
  42 #include "intel_fbo.h"
  43 #include "intel_buffer_objects.h"
  44
  45 #include "brw_context.h"
  46 #include "brw_state.h"
  47 #include "brw_defines.h"
  48 #include "brw_wm.h"
  49
  50 GLuint
  51 translate_tex_target(GLenum target)
  52 {
  53    switch (target) {
  54    case GL_TEXTURE_1D:
  55    case GL_TEXTURE_1D_ARRAY_EXT:
  56       return BRW_SURFACE_1D;
  57
  58    case GL_TEXTURE_RECTANGLE_NV:
  59       return BRW_SURFACE_2D;
  60
  61    case GL_TEXTURE_2D:
  62    case GL_TEXTURE_2D_ARRAY_EXT:
  63    case GL_TEXTURE_EXTERNAL_OES:
  64    case GL_TEXTURE_2D_MULTISAMPLE:
  65    case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
  66       return BRW_SURFACE_2D;
  67
  68    case GL_TEXTURE_3D:
  69       return BRW_SURFACE_3D;
  70
  71    case GL_TEXTURE_CUBE_MAP:
  72    case GL_TEXTURE_CUBE_MAP_ARRAY:
  73       return BRW_SURFACE_CUBE;
  74
  75    default:
  76       assert(0);
  77       return 0;
  78    }
  79 }
  80
  81 uint32_t
  82 brw_get_surface_tiling_bits(uint32_t tiling)
  83 {
  84    switch (tiling) {
  85    case I915_TILING_X:
  86       return BRW_SURFACE_TILED;
  87    case I915_TILING_Y:
  88       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
  89    default:
  90       return 0;
  91    }
  92 }
  93
  94
  95 uint32_t
  96 brw_get_surface_num_multisamples(unsigned num_samples)
  97 {
  98    if (num_samples > 1)
  99       return BRW_SURFACE_MULTISAMPLECOUNT_4;
 100    else
 101       return BRW_SURFACE_MULTISAMPLECOUNT_1;
 102 }
 103
 104
 105 /**
 106  * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
 107  * swizzling.
 108  */
 109 int
 110 brw_get_texture_swizzle(const struct gl_context *ctx,
 111                         const struct gl_texture_object *t)
 112 {
 113    const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
 114
 115    int swizzles[SWIZZLE_NIL + 1] = {
 116       SWIZZLE_X,
 117       SWIZZLE_Y,
 118       SWIZZLE_Z,
 119       SWIZZLE_W,
 120       SWIZZLE_ZERO,
 121       SWIZZLE_ONE,
 122       SWIZZLE_NIL
 123    };
 124
 125    if (img->_BaseFormat == GL_DEPTH_COMPONENT ||
 126        img->_BaseFormat == GL_DEPTH_STENCIL) {
 127       GLenum depth_mode = t->DepthMode;
 128
 129       /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
 130        * with depth component data specified with a sized internal format.
 131        * Otherwise, it's left at the old default, GL_LUMINANCE.
 132        */
 133       if (_mesa_is_gles3(ctx) &&
 134           img->InternalFormat != GL_DEPTH_COMPONENT &&
 135           img->InternalFormat != GL_DEPTH_STENCIL) {
 136          depth_mode = GL_RED;
 137       }
 138
 139       switch (depth_mode) {
 140       case GL_ALPHA:
 141          swizzles[0] = SWIZZLE_ZERO;
 142          swizzles[1] = SWIZZLE_ZERO;
 143          swizzles[2] = SWIZZLE_ZERO;
 144          swizzles[3] = SWIZZLE_X;
 145          break;
 146       case GL_LUMINANCE:
 147          swizzles[0] = SWIZZLE_X;
 148          swizzles[1] = SWIZZLE_X;
 149          swizzles[2] = SWIZZLE_X;
 150          swizzles[3] = SWIZZLE_ONE;
 151          break;
 152       case GL_INTENSITY:
 153          swizzles[0] = SWIZZLE_X;
 154          swizzles[1] = SWIZZLE_X;
 155          swizzles[2] = SWIZZLE_X;
 156          swizzles[3] = SWIZZLE_X;
 157          break;
 158       case GL_RED:
 159          swizzles[0] = SWIZZLE_X;
 160          swizzles[1] = SWIZZLE_ZERO;
 161          swizzles[2] = SWIZZLE_ZERO;
 162          swizzles[3] = SWIZZLE_ONE;
 163          break;
 164       }
 165    }
 166
 167    /* If the texture's format is alpha-only, force R, G, and B to
 168     * 0.0. Similarly, if the texture's format has no alpha channel,
 169     * force the alpha value read to 1.0. This allows for the
 170     * implementation to use an RGBA texture for any of these formats
 171     * without leaking any unexpected values.
 172     */
 173    switch (img->_BaseFormat) {
 174    case GL_ALPHA:
 175       swizzles[0] = SWIZZLE_ZERO;
 176       swizzles[1] = SWIZZLE_ZERO;
 177       swizzles[2] = SWIZZLE_ZERO;
 178       break;
 179    case GL_RED:
 180    case GL_RG:
 181    case GL_RGB:
 182       if (_mesa_get_format_bits(img->TexFormat, GL_ALPHA_BITS) > 0)
 183          swizzles[3] = SWIZZLE_ONE;
 184       break;
 185    }
 186
 187    return MAKE_SWIZZLE4(swizzles[GET_SWZ(t->_Swizzle, 0)],
 188                         swizzles[GET_SWZ(t->_Swizzle, 1)],
 189                         swizzles[GET_SWZ(t->_Swizzle, 2)],
 190                         swizzles[GET_SWZ(t->_Swizzle, 3)]);
 191 }
 192
 193
 194 static void
 195 brw_update_buffer_texture_surface(struct gl_context *ctx,
 196                                   unsigned unit,
 197                                   uint32_t *surf_offset)
 198 {
 199    struct brw_context *brw = brw_context(ctx);
 200    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 201    uint32_t *surf;
 202    struct intel_buffer_object *intel_obj =
 203       intel_buffer_object(tObj->BufferObject);
 204    drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
 205    gl_format format = tObj->_BufferObjectFormat;
 206    uint32_t brw_format = brw_format_for_mesa_format(format);
 207    int texel_size = _mesa_get_format_bytes(format);
 208
 209    if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
 210       _mesa_problem(NULL, "bad format %s for texture buffer\n",
 211                     _mesa_get_format_name(format));
 212    }
 213
 214    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 215                           6 * 4, 32, surf_offset);
 216
 217    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 218               (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT));
 219
 220    if (brw->gen >= 6)
 221       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 222
 223    if (bo) {
 224       surf[1] = bo->offset; /* reloc */
 225
 226       /* Emit relocation to surface contents. */
 227       drm_intel_bo_emit_reloc(brw->batch.bo,
 228                               *surf_offset + 4,
 229                               bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
 230
 231       int w = intel_obj->Base.Size / texel_size;
 232       surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 233                  ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 234       surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 235                  (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT);
 236    } else {
 237       surf[1] = 0;
 238       surf[2] = 0;
 239       surf[3] = 0;
 240    }
 241
 242    surf[4] = 0;
 243    surf[5] = 0;
 244 }
 245
 246 static void
 247 brw_update_texture_surface(struct gl_context *ctx,
 248                            unsigned unit,
 249                            uint32_t *surf_offset)
 250 {
 251    struct brw_context *brw = brw_context(ctx);
 252    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 253    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 254    struct intel_mipmap_tree *mt = intelObj->mt;
 255    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 256    struct intel_texture_image *intel_image = intel_texture_image(firstImage);
 257    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 258    uint32_t *surf;
 259
 260    if (tObj->Target == GL_TEXTURE_BUFFER) {
 261       brw_update_buffer_texture_surface(ctx, unit, surf_offset);
 262       return;
 263    }
 264
 265    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 266                           6 * 4, 32, surf_offset);
 267
 268    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 269               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 270               BRW_SURFACE_CUBEFACE_ENABLES |
 271               (translate_tex_format(brw,
 272                                     mt->format,
 273                                     tObj->DepthMode,
 274                                     sampler->sRGBDecode) <<
 275                BRW_SURFACE_FORMAT_SHIFT));
 276
 277    surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
 278
 279    surf[2] = ((intelObj->_MaxLevel - intel_image->mt->first_level) << BRW_SURFACE_LOD_SHIFT |
 280               (mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
 281               (mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 282
 283    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 284               (mt->logical_depth0 - 1) << BRW_SURFACE_DEPTH_SHIFT |
 285               (intelObj->mt->region->pitch - 1) <<
 286               BRW_SURFACE_PITCH_SHIFT);
 287
 288    surf[4] = brw_get_surface_num_multisamples(intelObj->mt->num_samples);
 289
 290    surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
 291
 292    /* Emit relocation to surface contents */
 293    drm_intel_bo_emit_reloc(brw->batch.bo,
 294                            *surf_offset + 4,
 295                            intelObj->mt->region->bo,
 296                            surf[1] - intelObj->mt->region->bo->offset,
 297                            I915_GEM_DOMAIN_SAMPLER, 0);
 298 }
 299
 300 /**
 301  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 302  * read from this buffer with Data Port Read instructions/messages.
 303  */
 304 static void
 305 brw_create_constant_surface(struct brw_context *brw,
 306                             drm_intel_bo *bo,
 307                             uint32_t offset,
 308                             uint32_t size,
 309                             uint32_t *out_offset,
 310                             bool dword_pitch)
 311 {
 312    uint32_t stride = dword_pitch ? 4 : 16;
 313    uint32_t elements = ALIGN(size, stride) / stride;
 314    const GLint w = elements - 1;
 315    uint32_t *surf;
 316
 317    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 318                           6 * 4, 32, out_offset);
 319
 320    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 321               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 322
 323    if (brw->gen >= 6)
 324       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 325
 326    surf[1] = bo->offset + offset; /* reloc */
 327
 328    surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 329               ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 330
 331    surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 332               (stride - 1) << BRW_SURFACE_PITCH_SHIFT);
 333
 334    surf[4] = 0;
 335    surf[5] = 0;
 336
 337    /* Emit relocation to surface contents.  The 965 PRM, Volume 4, section
 338     * 5.1.2 "Data Cache" says: "the data cache does not exist as a separate
 339     * physical cache.  It is mapped in hardware to the sampler cache."
 340     */
 341    drm_intel_bo_emit_reloc(brw->batch.bo,
 342                            *out_offset + 4,
 343                            bo, offset,
 344                            I915_GEM_DOMAIN_SAMPLER, 0);
 345 }
 346
 347 /**
 348  * Set up a binding table entry for use by stream output logic (transform
 349  * feedback).
 350  *
 351  * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
 352  */
 353 void
 354 brw_update_sol_surface(struct brw_context *brw,
 355                        struct gl_buffer_object *buffer_obj,
 356                        uint32_t *out_offset, unsigned num_vector_components,
 357                        unsigned stride_dwords, unsigned offset_dwords)
 358 {
 359    struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
 360    drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_bo, INTEL_WRITE_PART);
 361    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 362                                     out_offset);
 363    uint32_t pitch_minus_1 = 4*stride_dwords - 1;
 364    uint32_t offset_bytes = 4 * offset_dwords;
 365    size_t size_dwords = buffer_obj->Size / 4;
 366    uint32_t buffer_size_minus_1, width, height, depth, surface_format;
 367
 368    /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
 369     * too big to map using a single binding table entry?
 370     */
 371    assert((size_dwords - offset_dwords) / stride_dwords
 372           <= BRW_MAX_NUM_BUFFER_ENTRIES);
 373
 374    if (size_dwords > offset_dwords + num_vector_components) {
 375       /* There is room for at least 1 transform feedback output in the buffer.
 376        * Compute the number of additional transform feedback outputs the
 377        * buffer has room for.
 378        */
 379       buffer_size_minus_1 =
 380          (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
 381    } else {
 382       /* There isn't even room for a single transform feedback output in the
 383        * buffer.  We can't configure the binding table entry to prevent output
 384        * entirely; we'll have to rely on the geometry shader to detect
 385        * overflow.  But to minimize the damage in case of a bug, set up the
 386        * binding table entry to just allow a single output.
 387        */
 388       buffer_size_minus_1 = 0;
 389    }
 390    width = buffer_size_minus_1 & 0x7f;
 391    height = (buffer_size_minus_1 & 0xfff80) >> 7;
 392    depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
 393
 394    switch (num_vector_components) {
 395    case 1:
 396       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 397       break;
 398    case 2:
 399       surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
 400       break;
 401    case 3:
 402       surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
 403       break;
 404    case 4:
 405       surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 406       break;
 407    default:
 408       assert(!"Invalid vector size for transform feedback output");
 409       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 410       break;
 411    }
 412
 413    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 414       BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 415       surface_format << BRW_SURFACE_FORMAT_SHIFT |
 416       BRW_SURFACE_RC_READ_WRITE;
 417    surf[1] = bo->offset + offset_bytes; /* reloc */
 418    surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
 419               height << BRW_SURFACE_HEIGHT_SHIFT);
 420    surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
 421               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
 422    surf[4] = 0;
 423    surf[5] = 0;
 424
 425    /* Emit relocation to surface contents. */
 426    drm_intel_bo_emit_reloc(brw->batch.bo,
 427                            *out_offset + 4,
 428                            bo, offset_bytes,
 429                            I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 430 }
 431
 432 /* Creates a new WM constant buffer reflecting the current fragment program's
 433  * constants, if needed by the fragment program.
 434  *
 435  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 436  * state atom.
 437  */
 438 static void
 439 brw_upload_wm_pull_constants(struct brw_context *brw)
 440 {
 441    struct gl_context *ctx = &brw->ctx;
 442    /* BRW_NEW_FRAGMENT_PROGRAM */
 443    struct brw_fragment_program *fp =
 444       (struct brw_fragment_program *) brw->fragment_program;
 445    struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 446    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 447    const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
 448    float *constants;
 449    unsigned int i;
 450
 451    _mesa_load_state_parameters(ctx, params);
 452
 453    /* CACHE_NEW_WM_PROG */
 454    if (brw->wm.prog_data->nr_pull_params == 0) {
 455       if (brw->wm.base.const_bo) {
 456          drm_intel_bo_unreference(brw->wm.base.const_bo);
 457          brw->wm.base.const_bo = NULL;
 458          brw->wm.base.surf_offset[surf_index] = 0;
 459          brw->state.dirty.brw |= BRW_NEW_SURFACES;
 460       }
 461       return;
 462    }
 463
 464    drm_intel_bo_unreference(brw->wm.base.const_bo);
 465    brw->wm.base.const_bo = drm_intel_bo_alloc(brw->bufmgr, "WM const bo",
 466                                          size, 64);
 467
 468    /* _NEW_PROGRAM_CONSTANTS */
 469    drm_intel_gem_bo_map_gtt(brw->wm.base.const_bo);
 470    constants = brw->wm.base.const_bo->virtual;
 471    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 472       constants[i] = *brw->wm.prog_data->pull_param[i];
 473    }
 474    drm_intel_gem_bo_unmap_gtt(brw->wm.base.const_bo);
 475
 476    brw->vtbl.create_constant_surface(brw, brw->wm.base.const_bo, 0, size,
 477                                      &brw->wm.base.surf_offset[surf_index],
 478                                      true);
 479
 480    brw->state.dirty.brw |= BRW_NEW_SURFACES;
 481 }
 482
 483 const struct brw_tracked_state brw_wm_pull_constants = {
 484    .dirty = {
 485       .mesa = (_NEW_PROGRAM_CONSTANTS),
 486       .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
 487       .cache = CACHE_NEW_WM_PROG,
 488    },
 489    .emit = brw_upload_wm_pull_constants,
 490 };
 491
 492 static void
 493 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 494 {
 495    /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
 496     * Notes):
 497     *
 498     *     A null surface will be used in instances where an actual surface is
 499     *     not bound. When a write message is generated to a null surface, no
 500     *     actual surface is written to. When a read message (including any
 501     *     sampling engine message) is generated to a null surface, the result
 502     *     is all zeros. Note that a null surface type is allowed to be used
 503     *     with all messages, even if it is not specificially indicated as
 504     *     supported. All of the remaining fields in surface state are ignored
 505     *     for null surfaces, with the following exceptions:
 506     *
 507     *     - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
 508     *       depth buffer’s corresponding state for all render target surfaces,
 509     *       including null.
 510     *
 511     *     - Surface Format must be R8G8B8A8_UNORM.
 512     */
 513    struct gl_context *ctx = &brw->ctx;
 514    uint32_t *surf;
 515    unsigned surface_type = BRW_SURFACE_NULL;
 516    drm_intel_bo *bo = NULL;
 517    unsigned pitch_minus_1 = 0;
 518    uint32_t multisampling_state = 0;
 519
 520    /* _NEW_BUFFERS */
 521    const struct gl_framebuffer *fb = ctx->DrawBuffer;
 522
 523    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 524                           &brw->wm.base.surf_offset[SURF_INDEX_DRAW(unit)]);
 525
 526    if (fb->Visual.samples > 1) {
 527       /* On Gen6, null render targets seem to cause GPU hangs when
 528        * multisampling.  So work around this problem by rendering into dummy
 529        * color buffer.
 530        *
 531        * To decrease the amount of memory needed by the workaround buffer, we
 532        * set its pitch to 128 bytes (the width of a Y tile).  This means that
 533        * the amount of memory needed for the workaround buffer is
 534        * (width_in_tiles + height_in_tiles - 1) tiles.
 535        *
 536        * Note that since the workaround buffer will be interpreted by the
 537        * hardware as an interleaved multisampled buffer, we need to compute
 538        * width_in_tiles and height_in_tiles by dividing the width and height
 539        * by 16 rather than the normal Y-tile size of 32.
 540        */
 541       unsigned width_in_tiles = ALIGN(fb->Width, 16) / 16;
 542       unsigned height_in_tiles = ALIGN(fb->Height, 16) / 16;
 543       unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096;
 544       brw_get_scratch_bo(brw, &brw->wm.multisampled_null_render_target_bo,
 545                          size_needed);
 546       bo = brw->wm.multisampled_null_render_target_bo;
 547       surface_type = BRW_SURFACE_2D;
 548       pitch_minus_1 = 127;
 549       multisampling_state =
 550          brw_get_surface_num_multisamples(fb->Visual.samples);
 551    }
 552
 553    surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT |
 554               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
 555    if (brw->gen < 6) {
 556       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
 557                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
 558                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
 559                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
 560    }
 561    surf[1] = bo ? bo->offset : 0;
 562    surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 563               (fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 564
 565    /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
 566     * Notes):
 567     *
 568     *     If Surface Type is SURFTYPE_NULL, this field must be TRUE
 569     */
 570    surf[3] = (BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y |
 571               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
 572    surf[4] = multisampling_state;
 573    surf[5] = 0;
 574
 575    if (bo) {
 576       drm_intel_bo_emit_reloc(brw->batch.bo,
 577                               brw->wm.base.surf_offset[SURF_INDEX_DRAW(unit)] + 4,
 578                               bo, 0,
 579                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 580    }
 581 }
 582
 583 /**
 584  * Sets up a surface state structure to point at the given region.
 585  * While it is only used for the front/back buffer currently, it should be
 586  * usable for further buffers when doing ARB_draw_buffer support.
 587  */
 588 static void
 589 brw_update_renderbuffer_surface(struct brw_context *brw,
 590                                 struct gl_renderbuffer *rb,
 591                                 bool layered,
 592                                 unsigned int unit)
 593 {
 594    struct gl_context *ctx = &brw->ctx;
 595    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 596    struct intel_mipmap_tree *mt = irb->mt;
 597    struct intel_region *region;
 598    uint32_t *surf;
 599    uint32_t tile_x, tile_y;
 600    uint32_t format = 0;
 601    /* _NEW_BUFFERS */
 602    gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
 603
 604    assert(!layered);
 605
 606    if (rb->TexImage && !brw->has_surface_tile_offset) {
 607       intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y);
 608
 609       if (tile_x != 0 || tile_y != 0) {
 610          /* Original gen4 hardware couldn't draw to a non-tile-aligned
 611           * destination in a miptree unless you actually setup your renderbuffer
 612           * as a miptree and used the fragile lod/array_index/etc. controls to
 613           * select the image.  So, instead, we just make a new single-level
 614           * miptree and render into that.
 615           */
 616          intel_renderbuffer_move_to_temp(brw, irb, false);
 617          mt = irb->mt;
 618       }
 619    }
 620
 621    intel_miptree_used_for_rendering(irb->mt);
 622
 623    region = irb->mt->region;
 624
 625    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 626                           &brw->wm.base.surf_offset[SURF_INDEX_DRAW(unit)]);
 627
 628    format = brw->render_target_format[rb_format];
 629    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 630       _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 631                     __FUNCTION__, _mesa_get_format_name(rb_format));
 632    }
 633
 634    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 635               format << BRW_SURFACE_FORMAT_SHIFT);
 636
 637    /* reloc */
 638    surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
 639               region->bo->offset);
 640
 641    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 642               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 643
 644    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
 645               (region->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
 646
 647    surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
 648
 649    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 650    /* Note that the low bits of these fields are missing, so
 651     * there's the possibility of getting in trouble.
 652     */
 653    assert(tile_x % 4 == 0);
 654    assert(tile_y % 2 == 0);
 655    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 656               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
 657               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
 658
 659    if (brw->gen < 6) {
 660       /* _NEW_COLOR */
 661       if (!ctx->Color.ColorLogicOpEnabled &&
 662           (ctx->Color.BlendEnabled & (1 << unit)))
 663          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
 664
 665       if (!ctx->Color.ColorMask[unit][0])
 666          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
 667       if (!ctx->Color.ColorMask[unit][1])
 668          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
 669       if (!ctx->Color.ColorMask[unit][2])
 670          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
 671
 672       /* As mentioned above, disable writes to the alpha component when the
 673        * renderbuffer is XRGB.
 674        */
 675       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
 676           !ctx->Color.ColorMask[unit][3]) {
 677          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
 678       }
 679    }
 680
 681    drm_intel_bo_emit_reloc(brw->batch.bo,
 682                            brw->wm.base.surf_offset[SURF_INDEX_DRAW(unit)] + 4,
 683                            region->bo,
 684                            surf[1] - region->bo->offset,
 685                            I915_GEM_DOMAIN_RENDER,
 686                            I915_GEM_DOMAIN_RENDER);
 687 }
 688
 689 /**
 690  * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
 691  */
 692 static void
 693 brw_update_renderbuffer_surfaces(struct brw_context *brw)
 694 {
 695    struct gl_context *ctx = &brw->ctx;
 696    GLuint i;
 697
 698    /* _NEW_BUFFERS | _NEW_COLOR */
 699    /* Update surfaces for drawing buffers */
 700    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 701       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 702          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
 703             brw->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
 704                                                   ctx->DrawBuffer->Layered, i);
 705          } else {
 706             brw->vtbl.update_null_renderbuffer_surface(brw, i);
 707          }
 708       }
 709    } else {
 710       brw->vtbl.update_null_renderbuffer_surface(brw, 0);
 711    }
 712    brw->state.dirty.brw |= BRW_NEW_SURFACES;
 713 }
 714
 715 const struct brw_tracked_state brw_renderbuffer_surfaces = {
 716    .dirty = {
 717       .mesa = (_NEW_COLOR |
 718                _NEW_BUFFERS),
 719       .brw = BRW_NEW_BATCH,
 720       .cache = 0
 721    },
 722    .emit = brw_update_renderbuffer_surfaces,
 723 };
 724
 725 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
 726    .dirty = {
 727       .mesa = _NEW_BUFFERS,
 728       .brw = BRW_NEW_BATCH,
 729       .cache = 0
 730    },
 731    .emit = brw_update_renderbuffer_surfaces,
 732 };
 733
 734
 735 static void
 736 update_stage_texture_surfaces(struct brw_context *brw,
 737                               const struct gl_program *prog,
 738                               uint32_t *surf_offset)
 739 {
 740    if (!prog)
 741       return;
 742
 743    struct gl_context *ctx = &brw->ctx;
 744
 745    unsigned num_samplers = _mesa_fls(prog->SamplersUsed);
 746
 747    for (unsigned s = 0; s < num_samplers; s++) {
 748       surf_offset[s] = 0;
 749
 750       if (prog->SamplersUsed & (1 << s)) {
 751          const unsigned unit = prog->SamplerUnits[s];
 752
 753          /* _NEW_TEXTURE */
 754          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
 755             brw->vtbl.update_texture_surface(ctx, unit, surf_offset + s);
 756          }
 757       }
 758    }
 759 }
 760
 761
 762 /**
 763  * Construct SURFACE_STATE objects for enabled textures.
 764  */
 765 static void
 766 brw_update_texture_surfaces(struct brw_context *brw)
 767 {
 768    /* BRW_NEW_VERTEX_PROGRAM */
 769    struct gl_program *vs = (struct gl_program *) brw->vertex_program;
 770
 771    /* BRW_NEW_GEOMETRY_PROGRAM */
 772    struct gl_program *gs = (struct gl_program *) brw->geometry_program;
 773
 774    /* BRW_NEW_FRAGMENT_PROGRAM */
 775    struct gl_program *fs = (struct gl_program *) brw->fragment_program;
 776
 777    /* _NEW_TEXTURE */
 778    update_stage_texture_surfaces(brw, vs,
 779                                  brw->vs.base.surf_offset +
 780                                  SURF_INDEX_VEC4_TEXTURE(0));
 781    update_stage_texture_surfaces(brw, gs,
 782                                  brw->gs.base.surf_offset +
 783                                  SURF_INDEX_VEC4_TEXTURE(0));
 784    update_stage_texture_surfaces(brw, fs,
 785                                  brw->wm.base.surf_offset +
 786                                  SURF_INDEX_TEXTURE(0));
 787
 788    brw->state.dirty.brw |= BRW_NEW_SURFACES;
 789 }
 790
 791 const struct brw_tracked_state brw_texture_surfaces = {
 792    .dirty = {
 793       .mesa = _NEW_TEXTURE,
 794       .brw = BRW_NEW_BATCH |
 795              BRW_NEW_VERTEX_PROGRAM |
 796              BRW_NEW_GEOMETRY_PROGRAM |
 797              BRW_NEW_FRAGMENT_PROGRAM,
 798       .cache = 0
 799    },
 800    .emit = brw_update_texture_surfaces,
 801 };
 802
 803 void
 804 brw_upload_ubo_surfaces(struct brw_context *brw,
 805                         struct gl_shader *shader,
 806                         uint32_t *surf_offsets)
 807 {
 808    struct gl_context *ctx = &brw->ctx;
 809
 810    if (!shader)
 811       return;
 812
 813    for (int i = 0; i < shader->NumUniformBlocks; i++) {
 814       struct gl_uniform_buffer_binding *binding;
 815       struct intel_buffer_object *intel_bo;
 816
 817       binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding];
 818       intel_bo = intel_buffer_object(binding->BufferObject);
 819       drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_bo, INTEL_READ);
 820
 821       /* Because behavior for referencing outside of the binding's size in the
 822        * glBindBufferRange case is undefined, we can just bind the whole buffer
 823        * glBindBufferBase wants and be a correct implementation.
 824        */
 825       brw->vtbl.create_constant_surface(brw, bo, binding->Offset,
 826                                         bo->size - binding->Offset,
 827                                         &surf_offsets[i],
 828                                         shader->Type == GL_FRAGMENT_SHADER);
 829    }
 830
 831    if (shader->NumUniformBlocks)
 832       brw->state.dirty.brw |= BRW_NEW_SURFACES;
 833 }
 834
 835 static void
 836 brw_upload_wm_ubo_surfaces(struct brw_context *brw)
 837 {
 838    struct gl_context *ctx = &brw->ctx;
 839    /* _NEW_PROGRAM */
 840    struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
 841
 842    if (!prog)
 843       return;
 844
 845    brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
 846                            &brw->wm.base.surf_offset[SURF_INDEX_WM_UBO(0)]);
 847 }
 848
 849 const struct brw_tracked_state brw_wm_ubo_surfaces = {
 850    .dirty = {
 851       .mesa = _NEW_PROGRAM,
 852       .brw = BRW_NEW_BATCH | BRW_NEW_UNIFORM_BUFFER,
 853       .cache = 0,
 854    },
 855    .emit = brw_upload_wm_ubo_surfaces,
 856 };
 857
 858 void
 859 gen4_init_vtable_surface_functions(struct brw_context *brw)
 860 {
 861    brw->vtbl.update_texture_surface = brw_update_texture_surface;
 862    brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
 863    brw->vtbl.update_null_renderbuffer_surface =
 864       brw_update_null_renderbuffer_surface;
 865    brw->vtbl.create_constant_surface = brw_create_constant_surface;
 866 }