src/mesa/drivers/dri/i965/gen4_blorp_exec.h

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 static inline struct blorp_address
  25 dynamic_state_address(struct blorp_batch *batch, uint32_t offset)
  26 {
  27    assert(batch->blorp->driver_ctx == batch->driver_batch);
  28    struct brw_context *brw = batch->driver_batch;
  29
  30    return (struct blorp_address) {
  31       .buffer = brw->batch.bo,
  32       .offset = offset,
  33       .write_domain = 0,
  34       .read_domains = I915_GEM_DOMAIN_INSTRUCTION,
  35    };
  36 }
  37
  38 static inline struct blorp_address
  39 instruction_state_address(struct blorp_batch *batch, uint32_t offset)
  40 {
  41    assert(batch->blorp->driver_ctx == batch->driver_batch);
  42    struct brw_context *brw = batch->driver_batch;
  43
  44    return (struct blorp_address) {
  45       .buffer = brw->cache.bo,
  46       .offset = offset,
  47       .write_domain = 0,
  48       .read_domains = I915_GEM_DOMAIN_INSTRUCTION,
  49    };
  50 }
  51
  52 static struct blorp_address
  53 blorp_emit_vs_state(struct blorp_batch *batch,
  54                     const struct blorp_params *params)
  55 {
  56    assert(batch->blorp->driver_ctx == batch->driver_batch);
  57    struct brw_context *brw = batch->driver_batch;
  58
  59    uint32_t offset;
  60    blorp_emit_dynamic(batch, GENX(VS_STATE), vs, 64, &offset) {
  61       vs.Enable = false;
  62       vs.URBEntryAllocationSize = brw->urb.vsize - 1;
  63 #if GEN_GEN == 5
  64       vs.NumberofURBEntries = brw->urb.nr_vs_entries >> 2;
  65 #else
  66       vs.NumberofURBEntries = brw->urb.nr_vs_entries;
  67 #endif
  68    }
  69
  70    return dynamic_state_address(batch, offset);
  71 }
  72
  73 static struct blorp_address
  74 blorp_emit_sf_state(struct blorp_batch *batch,
  75                     const struct blorp_params *params)
  76 {
  77    assert(batch->blorp->driver_ctx == batch->driver_batch);
  78    struct brw_context *brw = batch->driver_batch;
  79    const struct brw_sf_prog_data *prog_data = params->sf_prog_data;
  80
  81    uint32_t offset;
  82    blorp_emit_dynamic(batch, GENX(SF_STATE), sf, 64, &offset) {
  83 #if GEN_GEN == 4
  84       sf.KernelStartPointer =
  85          instruction_state_address(batch, params->sf_prog_kernel);
  86 #else
  87       sf.KernelStartPointer = params->sf_prog_kernel;
  88 #endif
  89       sf.GRFRegisterCount = DIV_ROUND_UP(prog_data->total_grf, 16) - 1;
  90       sf.VertexURBEntryReadLength = prog_data->urb_read_length;
  91       sf.VertexURBEntryReadOffset = BRW_SF_URB_ENTRY_READ_OFFSET;
  92       sf.DispatchGRFStartRegisterForURBData = 3;
  93
  94       sf.URBEntryAllocationSize = brw->urb.sfsize - 1;
  95       sf.NumberofURBEntries = brw->urb.nr_sf_entries;
  96
  97 #if GEN_GEN == 5
  98       sf.MaximumNumberofThreads = MIN2(48, brw->urb.nr_sf_entries) - 1;
  99 #else
 100       sf.MaximumNumberofThreads = MIN2(24, brw->urb.nr_sf_entries) - 1;
 101 #endif
 102
 103       sf.ViewportTransformEnable = false;
 104
 105       sf.CullMode = CULLMODE_NONE;
 106    }
 107
 108    return dynamic_state_address(batch, offset);
 109 }
 110
 111 static struct blorp_address
 112 blorp_emit_wm_state(struct blorp_batch *batch,
 113                     const struct blorp_params *params)
 114 {
 115    const struct brw_wm_prog_data *prog_data = params->wm_prog_data;
 116
 117    uint32_t offset;
 118    blorp_emit_dynamic(batch, GENX(WM_STATE), wm, 64, &offset) {
 119       if (params->src.enabled) {
 120          /* Iron Lake can't do sampler prefetch */
 121          wm.SamplerCount = (GEN_GEN != 5);
 122          wm.BindingTableEntryCount = 2;
 123          uint32_t sampler = blorp_emit_sampler_state(batch, params);
 124          wm.SamplerStatePointer = dynamic_state_address(batch, sampler);
 125       }
 126
 127       if (prog_data) {
 128          wm.DispatchGRFStartRegisterForConstantSetupData0 =
 129             prog_data->base.dispatch_grf_start_reg;
 130          wm.SetupURBEntryReadLength = prog_data->num_varying_inputs * 2;
 131          wm.SetupURBEntryReadOffset = 0;
 132
 133          wm.DepthCoefficientURBReadOffset = 1;
 134          wm.PixelShaderKillsPixel = prog_data->uses_kill;
 135          wm.ThreadDispatchEnable = true;
 136          wm.EarlyDepthTestEnable = true;
 137
 138          wm._8PixelDispatchEnable = prog_data->dispatch_8;
 139          wm._16PixelDispatchEnable = prog_data->dispatch_16;
 140
 141 #if GEN_GEN == 4
 142          wm.KernelStartPointer0 =
 143             instruction_state_address(batch, params->wm_prog_kernel);
 144          wm.GRFRegisterCount0 = prog_data->reg_blocks_0;
 145 #else
 146          wm.KernelStartPointer0 = params->wm_prog_kernel;
 147          wm.GRFRegisterCount0 = prog_data->reg_blocks_0;
 148          wm.KernelStartPointer2 =
 149             params->wm_prog_kernel + prog_data->prog_offset_2;
 150          wm.GRFRegisterCount2 = prog_data->reg_blocks_2;
 151 #endif
 152       }
 153
 154       wm.MaximumNumberofThreads =
 155          batch->blorp->compiler->devinfo->max_wm_threads - 1;
 156    }
 157
 158    return dynamic_state_address(batch, offset);
 159 }
 160
 161 static struct blorp_address
 162 blorp_emit_color_calc_state(struct blorp_batch *batch,
 163                             const struct blorp_params *params)
 164 {
 165    uint32_t cc_viewport = blorp_emit_cc_viewport(batch, params);
 166
 167    uint32_t offset;
 168    blorp_emit_dynamic(batch, GENX(COLOR_CALC_STATE), cc, 64, &offset) {
 169       cc.CCViewportStatePointer = dynamic_state_address(batch, cc_viewport);
 170    }
 171
 172    return dynamic_state_address(batch, offset);
 173 }
 174
 175 static void
 176 blorp_emit_pipeline(struct blorp_batch *batch,
 177                     const struct blorp_params *params)
 178 {
 179    assert(batch->blorp->driver_ctx == batch->driver_batch);
 180    struct brw_context *brw = batch->driver_batch;
 181
 182    emit_urb_config(batch, params);
 183
 184    blorp_emit(batch, GENX(3DSTATE_PIPELINED_POINTERS), pp) {
 185       pp.PointertoVSState = blorp_emit_vs_state(batch, params);
 186       pp.GSEnable = false;
 187       pp.ClipEnable = false;
 188       pp.PointertoSFState = blorp_emit_sf_state(batch, params);
 189       pp.PointertoWMState = blorp_emit_wm_state(batch, params);
 190       pp.PointertoColorCalcState = blorp_emit_color_calc_state(batch, params);
 191    }
 192
 193    brw_upload_urb_fence(brw);
 194
 195    blorp_emit(batch, GENX(CS_URB_STATE), curb);
 196    blorp_emit(batch, GENX(CONSTANT_BUFFER), curb);
 197 }