2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_mipmap_tree.h"
29 #include "brw_context.h"
30 #include "brw_state.h"
32 #include "brw_blorp.h"
37 gen6_blorp_emit_input_varying_data(struct brw_context
*brw
,
38 const struct brw_blorp_params
*params
,
42 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
43 const unsigned max_num_varyings
=
44 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
45 const unsigned num_varyings
= params
->wm_prog_data
->num_varying_inputs
;
47 *size
= num_varyings
* vec4_size_in_bytes
;
49 const float *const inputs_src
= (const float *)¶ms
->wm_inputs
;
50 float *inputs
= (float *)brw_state_batch(brw
, AUB_TRACE_VERTEX_BUFFER
,
53 /* Walk over the attribute slots, determine if the attribute is used by
54 * the program and when necessary copy the values from the input storage to
55 * the vertex data buffer.
57 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
58 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
60 if (!(params
->wm_prog_data
->inputs_read
& BITFIELD64_BIT(attr
)))
63 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
70 gen6_blorp_emit_vertex_data(struct brw_context
*brw
,
71 const struct brw_blorp_params
*params
)
73 uint32_t vertex_offset
;
74 uint32_t const_data_offset
= 0;
75 unsigned const_data_size
= 0;
77 /* Setup VBO for the rectangle primitive..
79 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
80 * vertices. The vertices reside in screen space with DirectX coordinates
81 * (that is, (0, 0) is the upper left corner).
88 * Since the VS is disabled, the clipper loads each VUE directly from
89 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
90 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
92 * dw1: Render Target Array Index. The HiZ op does not use indexed
93 * vertices, so set the dword to 0.
94 * dw2: Viewport Index. The HiZ op disables viewport mapping and
95 * scissoring, so set the dword to 0.
96 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
98 * dw4: Vertex Position X.
99 * dw5: Vertex Position Y.
100 * dw6: Vertex Position Z.
101 * dw7: Vertex Position W.
103 * dw8: Flat vertex input 0
104 * dw9: Flat vertex input 1
106 * dwn: Flat vertex input n - 8
108 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
109 * "Vertex URB Entry (VUE) Formats".
111 * Only vertex position X and Y are going to be variable, Z is fixed to
112 * zero and W to one. Header words dw0-3 are all zero. There is no need to
113 * include the fixed values in the vertex buffer. Vertex fetcher can be
114 * instructed to fill vertex elements with constant values of one and zero
115 * instead of reading them from the buffer.
116 * Flat inputs are program constants that are not interpolated. Moreover
117 * their values will be the same between vertices.
119 * See the vertex element setup below.
121 const float vertices
[] = {
122 /* v0 */ (float)params
->x0
, (float)params
->y1
,
123 /* v1 */ (float)params
->x1
, (float)params
->y1
,
124 /* v2 */ (float)params
->x0
, (float)params
->y0
,
127 float *const vertex_data
= (float *)brw_state_batch(
128 brw
, AUB_TRACE_VERTEX_BUFFER
,
129 sizeof(vertices
), 32,
131 memcpy(vertex_data
, vertices
, sizeof(vertices
));
133 if (params
->wm_prog_data
&& params
->wm_prog_data
->num_varying_inputs
)
134 gen6_blorp_emit_input_varying_data(brw
, params
,
138 /* 3DSTATE_VERTEX_BUFFERS */
139 const int num_buffers
= 1 + (const_data_size
> 0);
140 const int batch_length
= 1 + 4 * num_buffers
;
142 BEGIN_BATCH(batch_length
);
143 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS
<< 16) | (batch_length
- 2));
145 const unsigned blorp_num_vue_elems
= 2;
146 const unsigned stride
= blorp_num_vue_elems
* sizeof(float);
147 EMIT_VERTEX_BUFFER_STATE(brw
, 0 /* buffer_nr */, brw
->batch
.bo
,
148 vertex_offset
, vertex_offset
+ sizeof(vertices
),
149 stride
, 0 /* steprate */);
151 if (const_data_size
) {
152 /* Tell vertex fetcher not to advance the pointer in the buffer when
153 * moving to the next vertex. This will effectively provide the same
154 * data for all the vertices. For flat inputs only the data provided
155 * for the first provoking vertex actually matters.
157 const unsigned stride_zero
= 0;
158 EMIT_VERTEX_BUFFER_STATE(brw
, 1 /* buffer_nr */, brw
->batch
.bo
,
160 const_data_offset
+ const_data_size
,
161 stride_zero
, 0 /* step_rate */);
168 gen6_blorp_emit_vertices(struct brw_context
*brw
,
169 const struct brw_blorp_params
*params
)
171 gen6_blorp_emit_vertex_data(brw
, params
);
173 const unsigned num_varyings
=
174 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
175 const unsigned num_elements
= 2 + num_varyings
;
176 const int batch_length
= 1 + 2 * num_elements
;
178 BEGIN_BATCH(batch_length
);
180 /* 3DSTATE_VERTEX_ELEMENTS
182 * Fetch dwords 0 - 7 from each VUE. See the comments above where
183 * the vertex_bo is filled with data. First element contains dwords
184 * for the VUE header, second the actual position values and the
185 * remaining contain the flat inputs.
188 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (batch_length
- 2));
190 OUT_BATCH(GEN6_VE0_VALID
|
191 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
192 0 << BRW_VE0_SRC_OFFSET_SHIFT
);
193 OUT_BATCH(BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_0_SHIFT
|
194 BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
|
195 BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
|
196 BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_3_SHIFT
);
198 OUT_BATCH(GEN6_VE0_VALID
|
199 BRW_SURFACEFORMAT_R32G32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
200 0 << BRW_VE0_SRC_OFFSET_SHIFT
);
201 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
202 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
203 BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
|
204 BRW_VE1_COMPONENT_STORE_1_FLT
<< BRW_VE1_COMPONENT_3_SHIFT
);
207 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
209 OUT_BATCH(1 << GEN6_VE0_INDEX_SHIFT
|
211 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
212 (i
* 4 * sizeof(float)) << BRW_VE0_SRC_OFFSET_SHIFT
);
213 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
214 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
215 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
216 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
225 * Assign the entire URB to the VS. Even though the VS disabled, URB space
226 * is still needed because the clipper loads the VUE's from the URB. From
227 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
228 * Dword 1.15:0 "VS Number of URB Entries":
229 * This field is always used (even if VS Function Enable is DISABLED).
231 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
232 * safely ignore it because this batch contains only one draw call.
233 * Because of URB corruption caused by allocating a previous GS unit
234 * URB entry to the VS unit, software is required to send a “GS NULL
235 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
236 * plus a dummy DRAW call before any case where VS will be taking over
240 gen6_blorp_emit_urb_config(struct brw_context
*brw
,
241 const struct brw_blorp_params
*params
)
244 OUT_BATCH(_3DSTATE_URB
<< 16 | (3 - 2));
245 OUT_BATCH(brw
->urb
.max_vs_entries
<< GEN6_URB_VS_ENTRIES_SHIFT
);
253 gen6_blorp_emit_blend_state(struct brw_context
*brw
,
254 const struct brw_blorp_params
*params
)
256 uint32_t cc_blend_state_offset
;
258 assume(params
->num_draw_buffers
);
260 const unsigned size
= params
->num_draw_buffers
*
261 sizeof(struct gen6_blend_state
);
262 struct gen6_blend_state
*blend
= (struct gen6_blend_state
*)
263 brw_state_batch(brw
, AUB_TRACE_BLEND_STATE
, size
, 64,
264 &cc_blend_state_offset
);
266 memset(blend
, 0, size
);
268 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
269 blend
[i
].blend1
.pre_blend_clamp_enable
= 1;
270 blend
[i
].blend1
.post_blend_clamp_enable
= 1;
271 blend
[i
].blend1
.clamp_range
= BRW_RENDERTARGET_CLAMPRANGE_FORMAT
;
273 blend
[i
].blend1
.write_disable_r
= params
->color_write_disable
[0];
274 blend
[i
].blend1
.write_disable_g
= params
->color_write_disable
[1];
275 blend
[i
].blend1
.write_disable_b
= params
->color_write_disable
[2];
276 blend
[i
].blend1
.write_disable_a
= params
->color_write_disable
[3];
279 return cc_blend_state_offset
;
285 gen6_blorp_emit_cc_state(struct brw_context
*brw
)
287 uint32_t cc_state_offset
;
289 struct gen6_color_calc_state
*cc
= (struct gen6_color_calc_state
*)
290 brw_state_batch(brw
, AUB_TRACE_CC_STATE
,
291 sizeof(gen6_color_calc_state
), 64,
293 memset(cc
, 0, sizeof(*cc
));
295 return cc_state_offset
;
300 * \param out_offset is relative to
301 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
304 gen6_blorp_emit_depth_stencil_state(struct brw_context
*brw
,
305 const struct brw_blorp_params
*params
)
307 uint32_t depthstencil_offset
;
309 struct gen6_depth_stencil_state
*state
;
310 state
= (struct gen6_depth_stencil_state
*)
311 brw_state_batch(brw
, AUB_TRACE_DEPTH_STENCIL_STATE
,
313 &depthstencil_offset
);
314 memset(state
, 0, sizeof(*state
));
316 /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
317 * - 7.5.3.1 Depth Buffer Clear
318 * - 7.5.3.2 Depth Buffer Resolve
319 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
321 state
->ds2
.depth_write_enable
= 1;
322 if (params
->hiz_op
== GEN6_HIZ_OP_DEPTH_RESOLVE
) {
323 state
->ds2
.depth_test_enable
= 1;
324 state
->ds2
.depth_test_func
= BRW_COMPAREFUNCTION_NEVER
;
327 return depthstencil_offset
;
331 /* 3DSTATE_CC_STATE_POINTERS
333 * The pointer offsets are relative to
334 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
336 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
339 gen6_blorp_emit_cc_state_pointers(struct brw_context
*brw
,
340 const struct brw_blorp_params
*params
,
341 uint32_t cc_blend_state_offset
,
342 uint32_t depthstencil_offset
,
343 uint32_t cc_state_offset
)
346 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (4 - 2));
347 OUT_BATCH(cc_blend_state_offset
| 1); /* BLEND_STATE offset */
348 OUT_BATCH(depthstencil_offset
| 1); /* DEPTH_STENCIL_STATE offset */
349 OUT_BATCH(cc_state_offset
| 1); /* COLOR_CALC_STATE offset */
354 /* WM push constants */
356 gen6_blorp_emit_wm_constants(struct brw_context
*brw
,
357 const struct brw_blorp_params
*params
)
359 uint32_t wm_push_const_offset
;
361 uint32_t *constants
= brw_state_batch(brw
, AUB_TRACE_WM_CONSTANTS
,
362 sizeof(params
->wm_inputs
),
363 32, &wm_push_const_offset
);
365 const uint32_t *push_consts
= (const uint32_t *)¶ms
->wm_inputs
;
366 for (unsigned i
= 0; i
< params
->wm_prog_data
->nr_params
; i
++)
367 constants
[i
] = push_consts
[params
->wm_prog_data
->param
[i
]];
369 return wm_push_const_offset
;
373 /* SURFACE_STATE for renderbuffer or texture surface (see
374 * brw_update_renderbuffer_surface and brw_update_texture_surface)
377 gen6_blorp_emit_surface_state(struct brw_context
*brw
,
378 const struct brw_blorp_params
*params
,
379 const struct brw_blorp_surface_info
*surface
,
380 uint32_t read_domains
, uint32_t write_domain
)
382 uint32_t wm_surf_offset
;
383 uint32_t width
= surface
->width
;
384 uint32_t height
= surface
->height
;
385 if (surface
->num_samples
> 1) {
386 /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
387 * in samples. But SURFACE_STATE wants them in pixels, so we need to
388 * divide them each by 2.
393 struct intel_mipmap_tree
*mt
= surface
->mt
;
394 uint32_t tile_x
, tile_y
;
396 uint32_t *surf
= (uint32_t *)
397 brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
400 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
401 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
402 BRW_SURFACE_CUBEFACE_ENABLES
|
403 surface
->brw_surfaceformat
<< BRW_SURFACE_FORMAT_SHIFT
);
406 surf
[1] = (brw_blorp_compute_tile_offsets(surface
, &tile_x
, &tile_y
) +
409 surf
[2] = (0 << BRW_SURFACE_LOD_SHIFT
|
410 (width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
411 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
413 uint32_t tiling
= surface
->map_stencil_as_y_tiled
414 ? BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
415 : brw_get_surface_tiling_bits(mt
->tiling
);
416 uint32_t pitch_bytes
= mt
->pitch
;
417 if (surface
->map_stencil_as_y_tiled
)
420 0 << BRW_SURFACE_DEPTH_SHIFT
|
421 (pitch_bytes
- 1) << BRW_SURFACE_PITCH_SHIFT
);
423 surf
[4] = brw_get_surface_num_multisamples(surface
->num_samples
);
425 /* Note that the low bits of these fields are missing, so
426 * there's the possibility of getting in trouble.
428 assert(tile_x
% 4 == 0);
429 assert(tile_y
% 2 == 0);
430 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
431 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
432 (surface
->mt
->valign
== 4 ?
433 BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
435 /* Emit relocation to surface contents */
436 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
439 surf
[1] - mt
->bo
->offset64
,
440 read_domains
, write_domain
);
442 return wm_surf_offset
;
446 /* BINDING_TABLE. See brw_wm_binding_table(). */
448 gen6_blorp_emit_binding_table(struct brw_context
*brw
,
449 uint32_t wm_surf_offset_renderbuffer
,
450 uint32_t wm_surf_offset_texture
)
452 uint32_t wm_bind_bo_offset
;
453 uint32_t *bind
= (uint32_t *)
454 brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
456 BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
,
459 bind
[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
] =
460 wm_surf_offset_renderbuffer
;
461 bind
[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
] = wm_surf_offset_texture
;
463 return wm_bind_bo_offset
;
468 * SAMPLER_STATE. See brw_update_sampler_state().
471 gen6_blorp_emit_sampler_state(struct brw_context
*brw
,
472 unsigned tex_filter
, unsigned max_lod
,
473 bool non_normalized_coords
)
475 uint32_t sampler_offset
;
476 uint32_t *sampler_state
= (uint32_t *)
477 brw_state_batch(brw
, AUB_TRACE_SAMPLER_STATE
, 16, 32, &sampler_offset
);
479 unsigned address_rounding
= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN
|
480 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN
|
481 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN
|
482 BRW_ADDRESS_ROUNDING_ENABLE_U_MAG
|
483 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG
|
484 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG
;
486 /* XXX: I don't think that using firstLevel, lastLevel works,
487 * because we always setup the surface state as if firstLevel ==
488 * level zero. Probably have to subtract firstLevel from each of
491 brw_emit_sampler_state(brw
,
494 tex_filter
, /* min filter */
495 tex_filter
, /* mag filter */
499 BRW_TEXCOORDMODE_CLAMP
,
500 BRW_TEXCOORDMODE_CLAMP
,
501 BRW_TEXCOORDMODE_CLAMP
,
505 0, /* shadow function */
506 non_normalized_coords
,
507 0); /* border color offset - unused */
509 return sampler_offset
;
514 * 3DSTATE_SAMPLER_STATE_POINTERS. See upload_sampler_state_pointers().
517 gen6_blorp_emit_sampler_state_pointers(struct brw_context
*brw
,
518 uint32_t sampler_offset
)
521 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS
<< 16 |
522 VS_SAMPLER_STATE_CHANGE
|
523 GS_SAMPLER_STATE_CHANGE
|
524 PS_SAMPLER_STATE_CHANGE
|
526 OUT_BATCH(0); /* VS */
527 OUT_BATCH(0); /* GS */
528 OUT_BATCH(sampler_offset
);
535 * Disable vertex shader.
538 gen6_blorp_emit_vs_disable(struct brw_context
*brw
,
539 const struct brw_blorp_params
*params
)
541 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
542 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
544 * [DevSNB] A pipeline flush must be programmed prior to a
545 * 3DSTATE_VS command that causes the VS Function Enable to
546 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
547 * command with CS stall bit set and a post sync operation.
549 * We've already done one at the start of the BLORP operation.
552 /* Disable the push constant buffers. */
554 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 | (5 - 2));
562 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
574 * Disable the geometry shader.
577 gen6_blorp_emit_gs_disable(struct brw_context
*brw
,
578 const struct brw_blorp_params
*params
)
580 /* Disable all the constant buffers. */
582 OUT_BATCH(_3DSTATE_CONSTANT_GS
<< 16 | (5 - 2));
590 OUT_BATCH(_3DSTATE_GS
<< 16 | (7 - 2));
598 brw
->gs
.enabled
= false;
604 * Disable the clipper.
606 * The BLORP op emits a rectangle primitive, which requires clipping to
607 * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
608 * Section 1.3 "3D Primitives Overview":
610 * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
611 * Mode should be set to a value other than CLIPMODE_NORMAL.
613 * Also disable perspective divide. This doesn't change the clipper's
614 * output, but does spare a few electrons.
617 gen6_blorp_emit_clip_disable(struct brw_context
*brw
)
620 OUT_BATCH(_3DSTATE_CLIP
<< 16 | (4 - 2));
622 OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE
);
630 * Disable ViewportTransformEnable (dw2.1)
632 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
633 * Primitives Overview":
634 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
635 * use of screen- space coordinates).
637 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
638 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
640 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
641 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
642 * SOLID: Any triangle or rectangle object found to be front-facing
643 * is rendered as a solid object. This setting is required when
644 * (rendering rectangle (RECTLIST) objects.
647 gen6_blorp_emit_sf_config(struct brw_context
*brw
,
648 const struct brw_blorp_params
*params
)
650 const unsigned num_varyings
=
651 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
654 OUT_BATCH(_3DSTATE_SF
<< 16 | (20 - 2));
655 OUT_BATCH(num_varyings
<< GEN6_SF_NUM_OUTPUTS_SHIFT
|
656 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT
|
657 BRW_SF_URB_ENTRY_READ_OFFSET
<<
658 GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT
);
659 OUT_BATCH(0); /* dw2 */
660 OUT_BATCH(params
->dst
.num_samples
> 1 ? GEN6_SF_MSRAST_ON_PATTERN
: 0);
661 for (int i
= 0; i
< 13; ++i
)
663 OUT_BATCH(params
->wm_prog_data
? params
->wm_prog_data
->flat_inputs
: 0);
671 * Enable or disable thread dispatch and set the HiZ op appropriately.
674 gen6_blorp_emit_wm_config(struct brw_context
*brw
,
675 const struct brw_blorp_params
*params
)
677 const struct brw_blorp_prog_data
*prog_data
= params
->wm_prog_data
;
678 uint32_t dw2
, dw4
, dw5
, dw6
, ksp0
, ksp2
;
680 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
681 * nonzero to prevent the GPU from hanging. While the documentation doesn't
682 * mention this explicitly, it notes that the valid range for the field is
683 * [1,39] = [2,40] threads, which excludes zero.
685 * To be safe (and to minimize extraneous code) we go ahead and fully
686 * configure the WM state whether or not there is a WM program.
689 dw2
= dw4
= dw5
= dw6
= ksp0
= ksp2
= 0;
690 switch (params
->hiz_op
) {
691 case GEN6_HIZ_OP_DEPTH_CLEAR
:
692 dw4
|= GEN6_WM_DEPTH_CLEAR
;
694 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
695 dw4
|= GEN6_WM_DEPTH_RESOLVE
;
697 case GEN6_HIZ_OP_HIZ_RESOLVE
:
698 dw4
|= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE
;
700 case GEN6_HIZ_OP_NONE
:
703 unreachable("not reached");
705 dw5
|= GEN6_WM_LINE_AA_WIDTH_1_0
;
706 dw5
|= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5
;
707 dw5
|= (brw
->max_wm_threads
- 1) << GEN6_WM_MAX_THREADS_SHIFT
;
708 dw6
|= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
; /* No interp */
709 dw6
|= (params
->wm_prog_data
? prog_data
->num_varying_inputs
: 0) <<
710 GEN6_WM_NUM_SF_OUTPUTS_SHIFT
;
712 if (params
->wm_prog_data
) {
713 dw5
|= GEN6_WM_DISPATCH_ENABLE
; /* We are rendering */
715 dw4
|= prog_data
->first_curbe_grf_0
<< GEN6_WM_DISPATCH_START_GRF_SHIFT_0
;
716 dw4
|= prog_data
->first_curbe_grf_2
<< GEN6_WM_DISPATCH_START_GRF_SHIFT_2
;
718 ksp0
= params
->wm_prog_kernel
;
719 ksp2
= params
->wm_prog_kernel
+ params
->wm_prog_data
->ksp_offset_2
;
721 if (params
->wm_prog_data
->dispatch_8
)
722 dw5
|= GEN6_WM_8_DISPATCH_ENABLE
;
723 if (params
->wm_prog_data
->dispatch_16
)
724 dw5
|= GEN6_WM_16_DISPATCH_ENABLE
;
727 if (params
->src
.mt
) {
728 dw5
|= GEN6_WM_KILL_ENABLE
; /* TODO: temporarily smash on */
729 dw2
|= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT
; /* Up to 4 samplers */
732 if (params
->dst
.num_samples
> 1) {
733 dw6
|= GEN6_WM_MSRAST_ON_PATTERN
;
734 if (prog_data
&& prog_data
->persample_msaa_dispatch
)
735 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
737 dw6
|= GEN6_WM_MSDISPMODE_PERPIXEL
;
739 dw6
|= GEN6_WM_MSRAST_OFF_PIXEL
;
740 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
744 OUT_BATCH(_3DSTATE_WM
<< 16 | (9 - 2));
747 OUT_BATCH(0); /* No scratch needed */
751 OUT_BATCH(0); /* kernel 1 pointer */
758 gen6_blorp_emit_constant_ps(struct brw_context
*brw
,
759 const struct brw_blorp_params
*params
,
760 uint32_t wm_push_const_offset
)
762 /* Make sure the push constants fill an exact integer number of
765 STATIC_ASSERT(sizeof(struct brw_blorp_wm_inputs
) % 32 == 0);
767 /* There must be at least one register worth of push constant data. */
768 assert(BRW_BLORP_NUM_PUSH_CONST_REGS
> 0);
770 /* Enable push constant buffer 0. */
772 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 |
773 GEN6_CONSTANT_BUFFER_0_ENABLE
|
775 OUT_BATCH(wm_push_const_offset
+ (BRW_BLORP_NUM_PUSH_CONST_REGS
- 1));
783 gen6_blorp_emit_constant_ps_disable(struct brw_context
*brw
,
784 const struct brw_blorp_params
*params
)
786 /* Disable the push constant buffers. */
788 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 | (5 - 2));
797 * 3DSTATE_BINDING_TABLE_POINTERS
800 gen6_blorp_emit_binding_table_pointers(struct brw_context
*brw
,
801 uint32_t wm_bind_bo_offset
)
804 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
805 GEN6_BINDING_TABLE_MODIFY_PS
|
807 OUT_BATCH(0); /* vs -- ignored */
808 OUT_BATCH(0); /* gs -- ignored */
809 OUT_BATCH(wm_bind_bo_offset
); /* wm/ps */
815 gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw
,
816 const struct brw_blorp_params
*params
)
818 uint32_t surfwidth
, surfheight
;
820 unsigned int depth
= MAX2(params
->depth
.mt
->logical_depth0
, 1);
821 GLenum gl_target
= params
->depth
.mt
->target
;
825 case GL_TEXTURE_CUBE_MAP_ARRAY
:
826 case GL_TEXTURE_CUBE_MAP
:
827 /* The PRM claims that we should use BRW_SURFACE_CUBE for this
828 * situation, but experiments show that gl_Layer doesn't work when we do
829 * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
832 surftype
= BRW_SURFACE_2D
;
836 surftype
= translate_tex_target(gl_target
);
840 const unsigned min_array_element
= params
->depth
.layer
;
842 lod
= params
->depth
.level
- params
->depth
.mt
->first_level
;
844 if (params
->hiz_op
!= GEN6_HIZ_OP_NONE
&& lod
== 0) {
845 /* HIZ ops for lod 0 may set the width & height a little
846 * larger to allow the fast depth clear to fit the hardware
847 * alignment requirements. (8x4)
849 surfwidth
= params
->depth
.width
;
850 surfheight
= params
->depth
.height
;
852 surfwidth
= params
->depth
.mt
->logical_width0
;
853 surfheight
= params
->depth
.mt
->logical_height0
;
856 /* 3DSTATE_DEPTH_BUFFER */
858 brw_emit_depth_stall_flushes(brw
);
861 /* 3DSTATE_DEPTH_BUFFER dw0 */
862 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
864 /* 3DSTATE_DEPTH_BUFFER dw1 */
865 OUT_BATCH((params
->depth
.mt
->pitch
- 1) |
866 params
->depth_format
<< 18 |
867 1 << 21 | /* separate stencil enable */
868 1 << 22 | /* hiz enable */
869 BRW_TILEWALK_YMAJOR
<< 26 |
870 1 << 27 | /* y-tiled */
873 /* 3DSTATE_DEPTH_BUFFER dw2 */
874 OUT_RELOC(params
->depth
.mt
->bo
,
875 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
878 /* 3DSTATE_DEPTH_BUFFER dw3 */
879 OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1 |
880 (surfwidth
- 1) << 6 |
881 (surfheight
- 1) << 19 |
884 /* 3DSTATE_DEPTH_BUFFER dw4 */
885 OUT_BATCH((depth
- 1) << 21 |
886 min_array_element
<< 10 |
889 /* 3DSTATE_DEPTH_BUFFER dw5 */
892 /* 3DSTATE_DEPTH_BUFFER dw6 */
897 /* 3DSTATE_HIER_DEPTH_BUFFER */
899 struct intel_mipmap_tree
*hiz_mt
= params
->depth
.mt
->hiz_buf
->mt
;
902 if (hiz_mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
903 offset
= intel_miptree_get_aligned_offset(hiz_mt
,
904 hiz_mt
->level
[lod
].level_x
,
905 hiz_mt
->level
[lod
].level_y
,
910 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
911 OUT_BATCH(hiz_mt
->pitch
- 1);
912 OUT_RELOC(hiz_mt
->bo
,
913 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
918 /* 3DSTATE_STENCIL_BUFFER */
921 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
930 gen6_blorp_emit_depth_disable(struct brw_context
*brw
,
931 const struct brw_blorp_params
*params
)
933 brw_emit_depth_stall_flushes(brw
);
936 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
937 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
938 (BRW_SURFACE_NULL
<< 29));
947 OUT_BATCH(_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (3 - 2));
953 OUT_BATCH(_3DSTATE_STENCIL_BUFFER
<< 16 | (3 - 2));
960 /* 3DSTATE_CLEAR_PARAMS
962 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
963 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
964 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
967 gen6_blorp_emit_clear_params(struct brw_context
*brw
,
968 const struct brw_blorp_params
*params
)
971 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
972 GEN5_DEPTH_CLEAR_VALID
|
974 OUT_BATCH(params
->depth
.mt
? params
->depth
.mt
->depth_clear_value
: 0);
979 /* 3DSTATE_DRAWING_RECTANGLE */
981 gen6_blorp_emit_drawing_rectangle(struct brw_context
*brw
,
982 const struct brw_blorp_params
*params
)
985 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
987 OUT_BATCH(((MAX2(params
->x1
, params
->x0
) - 1) & 0xffff) |
988 ((MAX2(params
->y1
, params
->y0
) - 1) << 16));
993 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
995 gen6_blorp_emit_viewport_state(struct brw_context
*brw
,
996 const struct brw_blorp_params
*params
)
998 struct brw_cc_viewport
*ccv
;
999 uint32_t cc_vp_offset
;
1001 ccv
= (struct brw_cc_viewport
*)brw_state_batch(brw
, AUB_TRACE_CC_VP_STATE
,
1005 ccv
->min_depth
= 0.0;
1006 ccv
->max_depth
= 1.0;
1009 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS
<< 16 | (4 - 2) |
1010 GEN6_CC_VIEWPORT_MODIFY
);
1011 OUT_BATCH(0); /* clip VP */
1012 OUT_BATCH(0); /* SF VP */
1013 OUT_BATCH(cc_vp_offset
);
1020 gen6_blorp_emit_primitive(struct brw_context
*brw
,
1021 const struct brw_blorp_params
*params
)
1024 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
1025 _3DPRIM_RECTLIST
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
1026 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
);
1027 OUT_BATCH(3); /* vertex count per instance */
1029 OUT_BATCH(params
->num_layers
); /* instance count */
1036 * \brief Execute a blit or render pass operation.
1038 * To execute the operation, this function manually constructs and emits a
1039 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1040 * constructing and after emitting the batch.
1042 * This function alters no GL state.
1045 gen6_blorp_exec(struct brw_context
*brw
,
1046 const struct brw_blorp_params
*params
)
1048 uint32_t cc_blend_state_offset
= 0;
1049 uint32_t cc_state_offset
= 0;
1050 uint32_t depthstencil_offset
;
1051 uint32_t wm_push_const_offset
= 0;
1052 uint32_t wm_bind_bo_offset
= 0;
1054 /* Emit workaround flushes when we switch from drawing to blorping. */
1055 brw_emit_post_sync_nonzero_flush(brw
);
1057 brw_upload_state_base_address(brw
);
1059 gen6_emit_3dstate_multisample(brw
, params
->dst
.num_samples
);
1060 gen6_emit_3dstate_sample_mask(brw
,
1061 params
->dst
.num_samples
> 1 ?
1062 (1 << params
->dst
.num_samples
) - 1 : 1);
1063 gen6_blorp_emit_vertices(brw
, params
);
1064 gen6_blorp_emit_urb_config(brw
, params
);
1065 if (params
->wm_prog_data
) {
1066 cc_blend_state_offset
= gen6_blorp_emit_blend_state(brw
, params
);
1067 cc_state_offset
= gen6_blorp_emit_cc_state(brw
);
1069 depthstencil_offset
= gen6_blorp_emit_depth_stencil_state(brw
, params
);
1070 gen6_blorp_emit_cc_state_pointers(brw
, params
, cc_blend_state_offset
,
1071 depthstencil_offset
, cc_state_offset
);
1072 if (params
->wm_prog_data
) {
1073 uint32_t wm_surf_offset_renderbuffer
;
1074 uint32_t wm_surf_offset_texture
= 0;
1076 if (params
->wm_prog_data
->nr_params
) {
1077 wm_push_const_offset
= gen6_blorp_emit_wm_constants(brw
, params
);
1080 intel_miptree_used_for_rendering(params
->dst
.mt
);
1081 wm_surf_offset_renderbuffer
=
1082 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->dst
,
1083 I915_GEM_DOMAIN_RENDER
,
1084 I915_GEM_DOMAIN_RENDER
);
1085 if (params
->src
.mt
) {
1086 wm_surf_offset_texture
=
1087 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->src
,
1088 I915_GEM_DOMAIN_SAMPLER
, 0);
1091 gen6_blorp_emit_binding_table(brw
,
1092 wm_surf_offset_renderbuffer
,
1093 wm_surf_offset_texture
);
1096 if (params
->src
.mt
) {
1097 const uint32_t sampler_offset
=
1098 gen6_blorp_emit_sampler_state(brw
, BRW_MAPFILTER_LINEAR
, 0, true);
1099 gen6_blorp_emit_sampler_state_pointers(brw
, sampler_offset
);
1101 gen6_blorp_emit_vs_disable(brw
, params
);
1102 gen6_blorp_emit_gs_disable(brw
, params
);
1103 gen6_blorp_emit_clip_disable(brw
);
1104 gen6_blorp_emit_sf_config(brw
, params
);
1105 if (params
->wm_prog_data
&& params
->wm_prog_data
->nr_params
)
1106 gen6_blorp_emit_constant_ps(brw
, params
, wm_push_const_offset
);
1108 gen6_blorp_emit_constant_ps_disable(brw
, params
);
1109 gen6_blorp_emit_wm_config(brw
, params
);
1110 if (params
->wm_prog_data
)
1111 gen6_blorp_emit_binding_table_pointers(brw
, wm_bind_bo_offset
);
1112 gen6_blorp_emit_viewport_state(brw
, params
);
1114 if (params
->depth
.mt
)
1115 gen6_blorp_emit_depth_stencil_config(brw
, params
);
1117 gen6_blorp_emit_depth_disable(brw
, params
);
1118 gen6_blorp_emit_clear_params(brw
, params
);
1119 gen6_blorp_emit_drawing_rectangle(brw
, params
);
1120 gen6_blorp_emit_primitive(brw
, params
);