2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
28 #include "intel_mipmap_tree.h"
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_state.h"
34 #include "brw_blorp.h"
35 #include "gen6_blorp.h"
38 * \name Constants for BLORP VBO
41 #define GEN6_BLORP_NUM_VERTICES 3
42 #define GEN6_BLORP_NUM_VUE_ELEMS 8
43 #define GEN6_BLORP_VBO_SIZE (GEN6_BLORP_NUM_VERTICES \
44 * GEN6_BLORP_NUM_VUE_ELEMS \
49 gen6_blorp_emit_batch_head(struct brw_context
*brw
,
50 const brw_blorp_params
*params
)
52 struct gl_context
*ctx
= &brw
->ctx
;
54 /* To ensure that the batch contains only the resolve, flush the batch
55 * before beginning and after finishing emitting the resolve packets.
62 * CMD_STATE_BASE_ADDRESS
64 * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS:
65 * The following commands must be reissued following any change to the
68 * 3DSTATE_BINDING_TABLE_POINTERS
69 * 3DSTATE_SAMPLER_STATE_POINTERS
70 * 3DSTATE_VIEWPORT_STATE_POINTERS
71 * MEDIA_STATE_POINTERS
74 gen6_blorp_emit_state_base_address(struct brw_context
*brw
,
75 const brw_blorp_params
*params
)
77 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
80 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
81 OUT_BATCH(mocs
<< 8 | /* GeneralStateMemoryObjectControlState */
82 mocs
<< 4 | /* StatelessDataPortAccessMemoryObjectControlState */
83 1); /* GeneralStateBaseAddressModifyEnable */
85 /* SurfaceStateBaseAddress */
86 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
87 /* DynamicStateBaseAddress */
88 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
89 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
90 OUT_BATCH(1); /* IndirectObjectBaseAddress */
91 if (params
->use_wm_prog
) {
92 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
93 1); /* Instruction base address: shader kernels */
95 OUT_BATCH(1); /* InstructionBaseAddress */
97 OUT_BATCH(1); /* GeneralStateUpperBound */
98 /* Dynamic state upper bound. Although the documentation says that
99 * programming it to zero will cause it to be ignored, that is a lie.
100 * If this isn't programmed to a real bound, the sampler border color
101 * pointer is rejected, causing border color to mysteriously fail.
103 OUT_BATCH(0xfffff001);
104 OUT_BATCH(1); /* IndirectObjectUpperBound*/
105 OUT_BATCH(1); /* InstructionAccessUpperBound */
111 gen6_blorp_emit_vertices(struct brw_context
*brw
,
112 const brw_blorp_params
*params
)
114 uint32_t vertex_offset
;
116 /* Setup VBO for the rectangle primitive..
118 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
119 * vertices. The vertices reside in screen space with DirectX coordinates
120 * (that is, (0, 0) is the upper left corner).
127 * Since the VS is disabled, the clipper loads each VUE directly from
128 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
129 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
130 * dw0: Reserved, MBZ.
131 * dw1: Render Target Array Index. The HiZ op does not use indexed
132 * vertices, so set the dword to 0.
133 * dw2: Viewport Index. The HiZ op disables viewport mapping and
134 * scissoring, so set the dword to 0.
135 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
136 * set the dword to 0.
137 * dw4: Vertex Position X.
138 * dw5: Vertex Position Y.
139 * dw6: Vertex Position Z.
140 * dw7: Vertex Position W.
142 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
143 * "Vertex URB Entry (VUE) Formats".
148 const float vertices
[GEN6_BLORP_VBO_SIZE
] = {
149 /* v0 */ 0, 0, 0, 0, (float) params
->x0
, (float) params
->y1
, 0, 1,
150 /* v1 */ 0, 0, 0, 0, (float) params
->x1
, (float) params
->y1
, 0, 1,
151 /* v2 */ 0, 0, 0, 0, (float) params
->x0
, (float) params
->y0
, 0, 1,
154 vertex_data
= (float *) brw_state_batch(brw
, AUB_TRACE_VERTEX_BUFFER
,
155 GEN6_BLORP_VBO_SIZE
, 32,
157 memcpy(vertex_data
, vertices
, GEN6_BLORP_VBO_SIZE
);
160 /* 3DSTATE_VERTEX_BUFFERS */
162 const int num_buffers
= 1;
163 const int batch_length
= 1 + 4 * num_buffers
;
165 uint32_t dw0
= GEN6_VB0_ACCESS_VERTEXDATA
|
166 (GEN6_BLORP_NUM_VUE_ELEMS
* sizeof(float)) << BRW_VB0_PITCH_SHIFT
;
169 dw0
|= GEN7_VB0_ADDRESS_MODIFYENABLE
;
172 dw0
|= GEN7_MOCS_L3
<< 16;
174 BEGIN_BATCH(batch_length
);
175 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS
<< 16) | (batch_length
- 2));
178 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
181 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
182 vertex_offset
+ GEN6_BLORP_VBO_SIZE
- 1);
187 /* 3DSTATE_VERTEX_ELEMENTS
189 * Fetch dwords 0 - 7 from each VUE. See the comments above where
190 * the vertex_bo is filled with data.
193 const int num_elements
= 2;
194 const int batch_length
= 1 + 2 * num_elements
;
196 BEGIN_BATCH(batch_length
);
197 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (batch_length
- 2));
199 OUT_BATCH(GEN6_VE0_VALID
|
200 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
201 0 << BRW_VE0_SRC_OFFSET_SHIFT
);
202 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
203 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
204 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
205 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
207 OUT_BATCH(GEN6_VE0_VALID
|
208 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
209 16 << BRW_VE0_SRC_OFFSET_SHIFT
);
210 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
211 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
212 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
213 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
221 * Assign the entire URB to the VS. Even though the VS disabled, URB space
222 * is still needed because the clipper loads the VUE's from the URB. From
223 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
224 * Dword 1.15:0 "VS Number of URB Entries":
225 * This field is always used (even if VS Function Enable is DISABLED).
227 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
228 * safely ignore it because this batch contains only one draw call.
229 * Because of URB corruption caused by allocating a previous GS unit
230 * URB entry to the VS unit, software is required to send a “GS NULL
231 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
232 * plus a dummy DRAW call before any case where VS will be taking over
236 gen6_blorp_emit_urb_config(struct brw_context
*brw
,
237 const brw_blorp_params
*params
)
240 OUT_BATCH(_3DSTATE_URB
<< 16 | (3 - 2));
241 OUT_BATCH(brw
->urb
.max_vs_entries
<< GEN6_URB_VS_ENTRIES_SHIFT
);
249 gen6_blorp_emit_blend_state(struct brw_context
*brw
,
250 const brw_blorp_params
*params
)
252 uint32_t cc_blend_state_offset
;
254 struct gen6_blend_state
*blend
= (struct gen6_blend_state
*)
255 brw_state_batch(brw
, AUB_TRACE_BLEND_STATE
,
256 sizeof(struct gen6_blend_state
), 64,
257 &cc_blend_state_offset
);
259 memset(blend
, 0, sizeof(*blend
));
261 blend
->blend1
.pre_blend_clamp_enable
= 1;
262 blend
->blend1
.post_blend_clamp_enable
= 1;
263 blend
->blend1
.clamp_range
= BRW_RENDERTARGET_CLAMPRANGE_FORMAT
;
265 blend
->blend1
.write_disable_r
= params
->color_write_disable
[0];
266 blend
->blend1
.write_disable_g
= params
->color_write_disable
[1];
267 blend
->blend1
.write_disable_b
= params
->color_write_disable
[2];
268 blend
->blend1
.write_disable_a
= params
->color_write_disable
[3];
270 /* When blitting from an XRGB source to a ARGB destination, we need to
271 * interpret the missing channel as 1.0. Blending can do that for us:
272 * we simply use the RGB values from the fragment shader ("source RGB"),
273 * but smash the alpha channel to 1.
275 if (params
->src
.mt
&&
276 _mesa_get_format_bits(params
->dst
.mt
->format
, GL_ALPHA_BITS
) > 0 &&
277 _mesa_get_format_bits(params
->src
.mt
->format
, GL_ALPHA_BITS
) == 0) {
278 blend
->blend0
.blend_enable
= 1;
279 blend
->blend0
.ia_blend_enable
= 1;
281 blend
->blend0
.blend_func
= BRW_BLENDFUNCTION_ADD
;
282 blend
->blend0
.ia_blend_func
= BRW_BLENDFUNCTION_ADD
;
284 blend
->blend0
.source_blend_factor
= BRW_BLENDFACTOR_SRC_COLOR
;
285 blend
->blend0
.dest_blend_factor
= BRW_BLENDFACTOR_ZERO
;
286 blend
->blend0
.ia_source_blend_factor
= BRW_BLENDFACTOR_ONE
;
287 blend
->blend0
.ia_dest_blend_factor
= BRW_BLENDFACTOR_ZERO
;
290 return cc_blend_state_offset
;
296 gen6_blorp_emit_cc_state(struct brw_context
*brw
,
297 const brw_blorp_params
*params
)
299 uint32_t cc_state_offset
;
301 struct gen6_color_calc_state
*cc
= (struct gen6_color_calc_state
*)
302 brw_state_batch(brw
, AUB_TRACE_CC_STATE
,
303 sizeof(gen6_color_calc_state
), 64,
305 memset(cc
, 0, sizeof(*cc
));
307 return cc_state_offset
;
312 * \param out_offset is relative to
313 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
316 gen6_blorp_emit_depth_stencil_state(struct brw_context
*brw
,
317 const brw_blorp_params
*params
)
319 uint32_t depthstencil_offset
;
321 struct gen6_depth_stencil_state
*state
;
322 state
= (struct gen6_depth_stencil_state
*)
323 brw_state_batch(brw
, AUB_TRACE_DEPTH_STENCIL_STATE
,
325 &depthstencil_offset
);
326 memset(state
, 0, sizeof(*state
));
328 /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
329 * - 7.5.3.1 Depth Buffer Clear
330 * - 7.5.3.2 Depth Buffer Resolve
331 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
333 state
->ds2
.depth_write_enable
= 1;
334 if (params
->hiz_op
== GEN6_HIZ_OP_DEPTH_RESOLVE
) {
335 state
->ds2
.depth_test_enable
= 1;
336 state
->ds2
.depth_test_func
= BRW_COMPAREFUNCTION_NEVER
;
339 return depthstencil_offset
;
343 /* 3DSTATE_CC_STATE_POINTERS
345 * The pointer offsets are relative to
346 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
348 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
351 gen6_blorp_emit_cc_state_pointers(struct brw_context
*brw
,
352 const brw_blorp_params
*params
,
353 uint32_t cc_blend_state_offset
,
354 uint32_t depthstencil_offset
,
355 uint32_t cc_state_offset
)
358 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (4 - 2));
359 OUT_BATCH(cc_blend_state_offset
| 1); /* BLEND_STATE offset */
360 OUT_BATCH(depthstencil_offset
| 1); /* DEPTH_STENCIL_STATE offset */
361 OUT_BATCH(cc_state_offset
| 1); /* COLOR_CALC_STATE offset */
366 /* WM push constants */
368 gen6_blorp_emit_wm_constants(struct brw_context
*brw
,
369 const brw_blorp_params
*params
)
371 uint32_t wm_push_const_offset
;
373 void *constants
= brw_state_batch(brw
, AUB_TRACE_WM_CONSTANTS
,
374 sizeof(params
->wm_push_consts
),
375 32, &wm_push_const_offset
);
376 memcpy(constants
, ¶ms
->wm_push_consts
,
377 sizeof(params
->wm_push_consts
));
379 return wm_push_const_offset
;
383 /* SURFACE_STATE for renderbuffer or texture surface (see
384 * brw_update_renderbuffer_surface and brw_update_texture_surface)
387 gen6_blorp_emit_surface_state(struct brw_context
*brw
,
388 const brw_blorp_params
*params
,
389 const brw_blorp_surface_info
*surface
,
390 uint32_t read_domains
, uint32_t write_domain
)
392 uint32_t wm_surf_offset
;
393 uint32_t width
= surface
->width
;
394 uint32_t height
= surface
->height
;
395 if (surface
->num_samples
> 1) {
396 /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
397 * in samples. But SURFACE_STATE wants them in pixels, so we need to
398 * divide them each by 2.
403 struct intel_region
*region
= surface
->mt
->region
;
404 uint32_t tile_x
, tile_y
;
406 uint32_t *surf
= (uint32_t *)
407 brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
410 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
411 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
412 BRW_SURFACE_CUBEFACE_ENABLES
|
413 surface
->brw_surfaceformat
<< BRW_SURFACE_FORMAT_SHIFT
);
416 surf
[1] = (surface
->compute_tile_offsets(&tile_x
, &tile_y
) +
419 surf
[2] = (0 << BRW_SURFACE_LOD_SHIFT
|
420 (width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
421 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
423 uint32_t tiling
= surface
->map_stencil_as_y_tiled
424 ? BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
425 : brw_get_surface_tiling_bits(region
->tiling
);
426 uint32_t pitch_bytes
= region
->pitch
;
427 if (surface
->map_stencil_as_y_tiled
)
430 0 << BRW_SURFACE_DEPTH_SHIFT
|
431 (pitch_bytes
- 1) << BRW_SURFACE_PITCH_SHIFT
);
433 surf
[4] = brw_get_surface_num_multisamples(surface
->num_samples
);
435 /* Note that the low bits of these fields are missing, so
436 * there's the possibility of getting in trouble.
438 assert(tile_x
% 4 == 0);
439 assert(tile_y
% 2 == 0);
440 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
441 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
442 (surface
->mt
->align_h
== 4 ?
443 BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
445 /* Emit relocation to surface contents */
446 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
449 surf
[1] - region
->bo
->offset
,
450 read_domains
, write_domain
);
452 return wm_surf_offset
;
456 /* BINDING_TABLE. See brw_wm_binding_table(). */
458 gen6_blorp_emit_binding_table(struct brw_context
*brw
,
459 const brw_blorp_params
*params
,
460 uint32_t wm_surf_offset_renderbuffer
,
461 uint32_t wm_surf_offset_texture
)
463 uint32_t wm_bind_bo_offset
;
464 uint32_t *bind
= (uint32_t *)
465 brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
467 BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
,
470 bind
[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
] =
471 wm_surf_offset_renderbuffer
;
472 bind
[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
] = wm_surf_offset_texture
;
474 return wm_bind_bo_offset
;
479 * SAMPLER_STATE. See brw_update_sampler_state().
482 gen6_blorp_emit_sampler_state(struct brw_context
*brw
,
483 const brw_blorp_params
*params
)
485 uint32_t sampler_offset
;
487 struct brw_sampler_state
*sampler
= (struct brw_sampler_state
*)
488 brw_state_batch(brw
, AUB_TRACE_SAMPLER_STATE
,
489 sizeof(struct brw_sampler_state
),
490 32, &sampler_offset
);
491 memset(sampler
, 0, sizeof(*sampler
));
493 sampler
->ss0
.min_filter
= BRW_MAPFILTER_LINEAR
;
494 sampler
->ss0
.mip_filter
= BRW_MIPFILTER_NONE
;
495 sampler
->ss0
.mag_filter
= BRW_MAPFILTER_LINEAR
;
497 sampler
->ss1
.r_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
498 sampler
->ss1
.s_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
499 sampler
->ss1
.t_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
501 sampler
->ss0
.min_mag_neq
= 1;
505 sampler
->ss0
.lod_bias
= 0;
507 sampler
->ss0
.lod_preclamp
= 1; /* OpenGL mode */
508 sampler
->ss0
.default_color_mode
= 0; /* OpenGL/DX10 mode */
510 /* Set BaseMipLevel, MaxLOD, MinLOD:
512 * XXX: I don't think that using firstLevel, lastLevel works,
513 * because we always setup the surface state as if firstLevel ==
514 * level zero. Probably have to subtract firstLevel from each of
517 sampler
->ss0
.base_level
= U_FIXED(0, 1);
519 sampler
->ss1
.max_lod
= U_FIXED(0, 6);
520 sampler
->ss1
.min_lod
= U_FIXED(0, 6);
522 sampler
->ss3
.non_normalized_coord
= 1;
524 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN
|
525 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN
|
526 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN
;
527 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG
|
528 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG
|
529 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG
;
531 return sampler_offset
;
536 * 3DSTATE_SAMPLER_STATE_POINTERS. See upload_sampler_state_pointers().
539 gen6_blorp_emit_sampler_state_pointers(struct brw_context
*brw
,
540 const brw_blorp_params
*params
,
541 uint32_t sampler_offset
)
544 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS
<< 16 |
545 VS_SAMPLER_STATE_CHANGE
|
546 GS_SAMPLER_STATE_CHANGE
|
547 PS_SAMPLER_STATE_CHANGE
|
549 OUT_BATCH(0); /* VS */
550 OUT_BATCH(0); /* GS */
551 OUT_BATCH(sampler_offset
);
558 * Disable vertex shader.
561 gen6_blorp_emit_vs_disable(struct brw_context
*brw
,
562 const brw_blorp_params
*params
)
565 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
566 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
568 * [DevSNB] A pipeline flush must be programmed prior to a
569 * 3DSTATE_VS command that causes the VS Function Enable to
570 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
571 * command with CS stall bit set and a post sync operation.
573 intel_emit_post_sync_nonzero_flush(brw
);
576 /* Disable the push constant buffers. */
578 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 | (5 - 2));
586 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
598 * Disable the geometry shader.
601 gen6_blorp_emit_gs_disable(struct brw_context
*brw
,
602 const brw_blorp_params
*params
)
604 /* Disable all the constant buffers. */
606 OUT_BATCH(_3DSTATE_CONSTANT_GS
<< 16 | (5 - 2));
614 OUT_BATCH(_3DSTATE_GS
<< 16 | (7 - 2));
627 * Disable the clipper.
629 * The BLORP op emits a rectangle primitive, which requires clipping to
630 * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
631 * Section 1.3 "3D Primitives Overview":
633 * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
634 * Mode should be set to a value other than CLIPMODE_NORMAL.
636 * Also disable perspective divide. This doesn't change the clipper's
637 * output, but does spare a few electrons.
640 gen6_blorp_emit_clip_disable(struct brw_context
*brw
,
641 const brw_blorp_params
*params
)
644 OUT_BATCH(_3DSTATE_CLIP
<< 16 | (4 - 2));
646 OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE
);
654 * Disable ViewportTransformEnable (dw2.1)
656 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
657 * Primitives Overview":
658 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
659 * use of screen- space coordinates).
661 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
662 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
664 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
665 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
666 * SOLID: Any triangle or rectangle object found to be front-facing
667 * is rendered as a solid object. This setting is required when
668 * (rendering rectangle (RECTLIST) objects.
671 gen6_blorp_emit_sf_config(struct brw_context
*brw
,
672 const brw_blorp_params
*params
)
675 OUT_BATCH(_3DSTATE_SF
<< 16 | (20 - 2));
676 OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT
| /* only position */
677 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT
|
678 0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT
);
679 OUT_BATCH(0); /* dw2 */
680 OUT_BATCH(params
->num_samples
> 1 ? GEN6_SF_MSRAST_ON_PATTERN
: 0);
681 for (int i
= 0; i
< 16; ++i
)
688 * Enable or disable thread dispatch and set the HiZ op appropriately.
691 gen6_blorp_emit_wm_config(struct brw_context
*brw
,
692 const brw_blorp_params
*params
,
693 uint32_t prog_offset
,
694 brw_blorp_prog_data
*prog_data
)
696 uint32_t dw2
, dw4
, dw5
, dw6
;
698 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
699 * nonzero to prevent the GPU from hanging. While the documentation doesn't
700 * mention this explicitly, it notes that the valid range for the field is
701 * [1,39] = [2,40] threads, which excludes zero.
703 * To be safe (and to minimize extraneous code) we go ahead and fully
704 * configure the WM state whether or not there is a WM program.
707 dw2
= dw4
= dw5
= dw6
= 0;
708 switch (params
->hiz_op
) {
709 case GEN6_HIZ_OP_DEPTH_CLEAR
:
710 dw4
|= GEN6_WM_DEPTH_CLEAR
;
712 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
713 dw4
|= GEN6_WM_DEPTH_RESOLVE
;
715 case GEN6_HIZ_OP_HIZ_RESOLVE
:
716 dw4
|= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE
;
718 case GEN6_HIZ_OP_NONE
:
724 dw5
|= GEN6_WM_LINE_AA_WIDTH_1_0
;
725 dw5
|= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5
;
726 dw5
|= (brw
->max_wm_threads
- 1) << GEN6_WM_MAX_THREADS_SHIFT
;
727 dw6
|= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
; /* No interp */
728 dw6
|= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT
; /* No inputs from SF */
729 if (params
->use_wm_prog
) {
730 dw2
|= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT
; /* Up to 4 samplers */
731 dw4
|= prog_data
->first_curbe_grf
<< GEN6_WM_DISPATCH_START_GRF_SHIFT_0
;
732 dw5
|= GEN6_WM_16_DISPATCH_ENABLE
;
733 dw5
|= GEN6_WM_KILL_ENABLE
; /* TODO: temporarily smash on */
734 dw5
|= GEN6_WM_DISPATCH_ENABLE
; /* We are rendering */
737 if (params
->num_samples
> 1) {
738 dw6
|= GEN6_WM_MSRAST_ON_PATTERN
;
739 if (prog_data
&& prog_data
->persample_msaa_dispatch
)
740 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
742 dw6
|= GEN6_WM_MSDISPMODE_PERPIXEL
;
744 dw6
|= GEN6_WM_MSRAST_OFF_PIXEL
;
745 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
749 OUT_BATCH(_3DSTATE_WM
<< 16 | (9 - 2));
750 OUT_BATCH(params
->use_wm_prog
? prog_offset
: 0);
752 OUT_BATCH(0); /* No scratch needed */
756 OUT_BATCH(0); /* No other programs */
757 OUT_BATCH(0); /* No other programs */
763 gen6_blorp_emit_constant_ps(struct brw_context
*brw
,
764 const brw_blorp_params
*params
,
765 uint32_t wm_push_const_offset
)
767 /* Make sure the push constants fill an exact integer number of
770 assert(sizeof(brw_blorp_wm_push_constants
) % 32 == 0);
772 /* There must be at least one register worth of push constant data. */
773 assert(BRW_BLORP_NUM_PUSH_CONST_REGS
> 0);
775 /* Enable push constant buffer 0. */
777 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 |
778 GEN6_CONSTANT_BUFFER_0_ENABLE
|
780 OUT_BATCH(wm_push_const_offset
+ (BRW_BLORP_NUM_PUSH_CONST_REGS
- 1));
788 gen6_blorp_emit_constant_ps_disable(struct brw_context
*brw
,
789 const brw_blorp_params
*params
)
791 /* Disable the push constant buffers. */
793 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 | (5 - 2));
802 * 3DSTATE_BINDING_TABLE_POINTERS
805 gen6_blorp_emit_binding_table_pointers(struct brw_context
*brw
,
806 const brw_blorp_params
*params
,
807 uint32_t wm_bind_bo_offset
)
810 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
811 GEN6_BINDING_TABLE_MODIFY_PS
|
813 OUT_BATCH(0); /* vs -- ignored */
814 OUT_BATCH(0); /* gs -- ignored */
815 OUT_BATCH(wm_bind_bo_offset
); /* wm/ps */
821 gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw
,
822 const brw_blorp_params
*params
)
824 struct gl_context
*ctx
= &brw
->ctx
;
825 uint32_t draw_x
= params
->depth
.x_offset
;
826 uint32_t draw_y
= params
->depth
.y_offset
;
827 uint32_t tile_mask_x
, tile_mask_y
;
829 brw_get_depthstencil_tile_masks(params
->depth
.mt
,
833 &tile_mask_x
, &tile_mask_y
);
835 /* 3DSTATE_DEPTH_BUFFER */
837 uint32_t tile_x
= draw_x
& tile_mask_x
;
838 uint32_t tile_y
= draw_y
& tile_mask_y
;
840 intel_region_get_aligned_offset(params
->depth
.mt
->region
,
841 draw_x
& ~tile_mask_x
,
842 draw_y
& ~tile_mask_y
, false);
844 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
845 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
846 * Coordinate Offset X/Y":
848 * "The 3 LSBs of both offsets must be zero to ensure correct
851 * We have no guarantee that tile_x and tile_y are correctly aligned,
852 * since they are determined by the mipmap layout, which is only aligned
855 * So, to avoid hanging the GPU, just smash the low order 3 bits of
856 * tile_x and tile_y to 0. This is a temporary workaround until we come
857 * up with a better solution.
859 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
860 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
861 "Truncating offset, bad rendering may occur.\n");
865 intel_emit_post_sync_nonzero_flush(brw
);
866 intel_emit_depth_stall_flushes(brw
);
869 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
870 OUT_BATCH((params
->depth
.mt
->region
->pitch
- 1) |
871 params
->depth_format
<< 18 |
872 1 << 21 | /* separate stencil enable */
873 1 << 22 | /* hiz enable */
874 BRW_TILEWALK_YMAJOR
<< 26 |
875 1 << 27 | /* y-tiled */
876 BRW_SURFACE_2D
<< 29);
877 OUT_RELOC(params
->depth
.mt
->region
->bo
,
878 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
880 OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1 |
881 (params
->depth
.width
+ tile_x
- 1) << 6 |
882 (params
->depth
.height
+ tile_y
- 1) << 19);
890 /* 3DSTATE_HIER_DEPTH_BUFFER */
892 struct intel_region
*hiz_region
= params
->depth
.mt
->hiz_mt
->region
;
893 uint32_t hiz_offset
=
894 intel_region_get_aligned_offset(hiz_region
,
895 draw_x
& ~tile_mask_x
,
896 (draw_y
& ~tile_mask_y
) / 2, false);
899 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
900 OUT_BATCH(hiz_region
->pitch
- 1);
901 OUT_RELOC(hiz_region
->bo
,
902 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
907 /* 3DSTATE_STENCIL_BUFFER */
910 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
919 gen6_blorp_emit_depth_disable(struct brw_context
*brw
,
920 const brw_blorp_params
*params
)
922 intel_emit_post_sync_nonzero_flush(brw
);
923 intel_emit_depth_stall_flushes(brw
);
926 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
927 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
928 (BRW_SURFACE_NULL
<< 29));
938 /* 3DSTATE_CLEAR_PARAMS
940 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
941 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
942 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
945 gen6_blorp_emit_clear_params(struct brw_context
*brw
,
946 const brw_blorp_params
*params
)
949 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
950 GEN5_DEPTH_CLEAR_VALID
|
952 OUT_BATCH(params
->depth
.mt
? params
->depth
.mt
->depth_clear_value
: 0);
957 /* 3DSTATE_DRAWING_RECTANGLE */
959 gen6_blorp_emit_drawing_rectangle(struct brw_context
*brw
,
960 const brw_blorp_params
*params
)
963 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
965 OUT_BATCH(((params
->x1
- 1) & 0xffff) |
966 ((params
->y1
- 1) << 16));
971 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
973 gen6_blorp_emit_viewport_state(struct brw_context
*brw
,
974 const brw_blorp_params
*params
)
976 struct brw_cc_viewport
*ccv
;
977 uint32_t cc_vp_offset
;
979 ccv
= (struct brw_cc_viewport
*)brw_state_batch(brw
, AUB_TRACE_CC_VP_STATE
,
983 ccv
->min_depth
= 0.0;
984 ccv
->max_depth
= 1.0;
987 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS
<< 16 | (4 - 2) |
988 GEN6_CC_VIEWPORT_MODIFY
);
989 OUT_BATCH(0); /* clip VP */
990 OUT_BATCH(0); /* SF VP */
991 OUT_BATCH(cc_vp_offset
);
998 gen6_blorp_emit_primitive(struct brw_context
*brw
,
999 const brw_blorp_params
*params
)
1002 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
1003 _3DPRIM_RECTLIST
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
1004 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
);
1005 OUT_BATCH(3); /* vertex count per instance */
1007 OUT_BATCH(1); /* instance count */
1015 * \brief Execute a blit or render pass operation.
1017 * To execute the operation, this function manually constructs and emits a
1018 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1019 * constructing and after emitting the batch.
1021 * This function alters no GL state.
1024 gen6_blorp_exec(struct brw_context
*brw
,
1025 const brw_blorp_params
*params
)
1027 brw_blorp_prog_data
*prog_data
= NULL
;
1028 uint32_t cc_blend_state_offset
= 0;
1029 uint32_t cc_state_offset
= 0;
1030 uint32_t depthstencil_offset
;
1031 uint32_t wm_push_const_offset
= 0;
1032 uint32_t wm_bind_bo_offset
= 0;
1034 uint32_t prog_offset
= params
->get_wm_prog(brw
, &prog_data
);
1035 gen6_blorp_emit_batch_head(brw
, params
);
1036 gen6_emit_3dstate_multisample(brw
, params
->num_samples
);
1037 gen6_emit_3dstate_sample_mask(brw
, params
->num_samples
, 1.0, false, ~0u);
1038 gen6_blorp_emit_state_base_address(brw
, params
);
1039 gen6_blorp_emit_vertices(brw
, params
);
1040 gen6_blorp_emit_urb_config(brw
, params
);
1041 if (params
->use_wm_prog
) {
1042 cc_blend_state_offset
= gen6_blorp_emit_blend_state(brw
, params
);
1043 cc_state_offset
= gen6_blorp_emit_cc_state(brw
, params
);
1045 depthstencil_offset
= gen6_blorp_emit_depth_stencil_state(brw
, params
);
1046 gen6_blorp_emit_cc_state_pointers(brw
, params
, cc_blend_state_offset
,
1047 depthstencil_offset
, cc_state_offset
);
1048 if (params
->use_wm_prog
) {
1049 uint32_t wm_surf_offset_renderbuffer
;
1050 uint32_t wm_surf_offset_texture
= 0;
1051 uint32_t sampler_offset
;
1052 wm_push_const_offset
= gen6_blorp_emit_wm_constants(brw
, params
);
1053 intel_miptree_used_for_rendering(params
->dst
.mt
);
1054 wm_surf_offset_renderbuffer
=
1055 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->dst
,
1056 I915_GEM_DOMAIN_RENDER
,
1057 I915_GEM_DOMAIN_RENDER
);
1058 if (params
->src
.mt
) {
1059 wm_surf_offset_texture
=
1060 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->src
,
1061 I915_GEM_DOMAIN_SAMPLER
, 0);
1064 gen6_blorp_emit_binding_table(brw
, params
,
1065 wm_surf_offset_renderbuffer
,
1066 wm_surf_offset_texture
);
1067 sampler_offset
= gen6_blorp_emit_sampler_state(brw
, params
);
1068 gen6_blorp_emit_sampler_state_pointers(brw
, params
, sampler_offset
);
1070 gen6_blorp_emit_vs_disable(brw
, params
);
1071 gen6_blorp_emit_gs_disable(brw
, params
);
1072 gen6_blorp_emit_clip_disable(brw
, params
);
1073 gen6_blorp_emit_sf_config(brw
, params
);
1074 if (params
->use_wm_prog
)
1075 gen6_blorp_emit_constant_ps(brw
, params
, wm_push_const_offset
);
1077 gen6_blorp_emit_constant_ps_disable(brw
, params
);
1078 gen6_blorp_emit_wm_config(brw
, params
, prog_offset
, prog_data
);
1079 if (params
->use_wm_prog
)
1080 gen6_blorp_emit_binding_table_pointers(brw
, params
, wm_bind_bo_offset
);
1081 gen6_blorp_emit_viewport_state(brw
, params
);
1083 if (params
->depth
.mt
)
1084 gen6_blorp_emit_depth_stencil_config(brw
, params
);
1086 gen6_blorp_emit_depth_disable(brw
, params
);
1087 gen6_blorp_emit_clear_params(brw
, params
);
1088 gen6_blorp_emit_drawing_rectangle(brw
, params
);
1089 gen6_blorp_emit_primitive(brw
, params
);