2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
28 #include "intel_mipmap_tree.h"
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_state.h"
34 #include "brw_blorp.h"
35 #include "gen6_blorp.h"
38 * \name Constants for BLORP VBO
41 #define GEN6_BLORP_NUM_VERTICES 3
42 #define GEN6_BLORP_NUM_VUE_ELEMS 8
43 #define GEN6_BLORP_VBO_SIZE (GEN6_BLORP_NUM_VERTICES \
44 * GEN6_BLORP_NUM_VUE_ELEMS \
49 * CMD_STATE_BASE_ADDRESS
51 * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS:
52 * The following commands must be reissued following any change to the
55 * 3DSTATE_BINDING_TABLE_POINTERS
56 * 3DSTATE_SAMPLER_STATE_POINTERS
57 * 3DSTATE_VIEWPORT_STATE_POINTERS
58 * MEDIA_STATE_POINTERS
61 gen6_blorp_emit_state_base_address(struct brw_context
*brw
,
62 const brw_blorp_params
*params
)
64 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
67 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
68 OUT_BATCH(mocs
<< 8 | /* GeneralStateMemoryObjectControlState */
69 mocs
<< 4 | /* StatelessDataPortAccessMemoryObjectControlState */
70 1); /* GeneralStateBaseAddressModifyEnable */
72 /* SurfaceStateBaseAddress */
73 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
74 /* DynamicStateBaseAddress */
75 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
76 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
77 OUT_BATCH(1); /* IndirectObjectBaseAddress */
78 if (params
->use_wm_prog
) {
79 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
80 1); /* Instruction base address: shader kernels */
82 OUT_BATCH(1); /* InstructionBaseAddress */
84 OUT_BATCH(1); /* GeneralStateUpperBound */
85 /* Dynamic state upper bound. Although the documentation says that
86 * programming it to zero will cause it to be ignored, that is a lie.
87 * If this isn't programmed to a real bound, the sampler border color
88 * pointer is rejected, causing border color to mysteriously fail.
90 OUT_BATCH(0xfffff001);
91 OUT_BATCH(1); /* IndirectObjectUpperBound*/
92 OUT_BATCH(1); /* InstructionAccessUpperBound */
98 gen6_blorp_emit_vertices(struct brw_context
*brw
,
99 const brw_blorp_params
*params
)
101 uint32_t vertex_offset
;
103 /* Setup VBO for the rectangle primitive..
105 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
106 * vertices. The vertices reside in screen space with DirectX coordinates
107 * (that is, (0, 0) is the upper left corner).
114 * Since the VS is disabled, the clipper loads each VUE directly from
115 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
116 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
117 * dw0: Reserved, MBZ.
118 * dw1: Render Target Array Index. The HiZ op does not use indexed
119 * vertices, so set the dword to 0.
120 * dw2: Viewport Index. The HiZ op disables viewport mapping and
121 * scissoring, so set the dword to 0.
122 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
123 * set the dword to 0.
124 * dw4: Vertex Position X.
125 * dw5: Vertex Position Y.
126 * dw6: Vertex Position Z.
127 * dw7: Vertex Position W.
129 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
130 * "Vertex URB Entry (VUE) Formats".
135 const float vertices
[GEN6_BLORP_VBO_SIZE
] = {
136 /* v0 */ 0, 0, 0, 0, (float) params
->x0
, (float) params
->y1
, 0, 1,
137 /* v1 */ 0, 0, 0, 0, (float) params
->x1
, (float) params
->y1
, 0, 1,
138 /* v2 */ 0, 0, 0, 0, (float) params
->x0
, (float) params
->y0
, 0, 1,
141 vertex_data
= (float *) brw_state_batch(brw
, AUB_TRACE_VERTEX_BUFFER
,
142 GEN6_BLORP_VBO_SIZE
, 32,
144 memcpy(vertex_data
, vertices
, GEN6_BLORP_VBO_SIZE
);
147 /* 3DSTATE_VERTEX_BUFFERS */
149 const int num_buffers
= 1;
150 const int batch_length
= 1 + 4 * num_buffers
;
152 uint32_t dw0
= GEN6_VB0_ACCESS_VERTEXDATA
|
153 (GEN6_BLORP_NUM_VUE_ELEMS
* sizeof(float)) << BRW_VB0_PITCH_SHIFT
;
156 dw0
|= GEN7_VB0_ADDRESS_MODIFYENABLE
;
159 dw0
|= GEN7_MOCS_L3
<< 16;
161 BEGIN_BATCH(batch_length
);
162 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS
<< 16) | (batch_length
- 2));
165 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
168 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
169 vertex_offset
+ GEN6_BLORP_VBO_SIZE
- 1);
174 /* 3DSTATE_VERTEX_ELEMENTS
176 * Fetch dwords 0 - 7 from each VUE. See the comments above where
177 * the vertex_bo is filled with data.
180 const int num_elements
= 2;
181 const int batch_length
= 1 + 2 * num_elements
;
183 BEGIN_BATCH(batch_length
);
184 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (batch_length
- 2));
186 OUT_BATCH(GEN6_VE0_VALID
|
187 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
188 0 << BRW_VE0_SRC_OFFSET_SHIFT
);
189 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
190 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
191 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
192 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
194 OUT_BATCH(GEN6_VE0_VALID
|
195 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
196 16 << BRW_VE0_SRC_OFFSET_SHIFT
);
197 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
198 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
199 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
200 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
208 * Assign the entire URB to the VS. Even though the VS disabled, URB space
209 * is still needed because the clipper loads the VUE's from the URB. From
210 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
211 * Dword 1.15:0 "VS Number of URB Entries":
212 * This field is always used (even if VS Function Enable is DISABLED).
214 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
215 * safely ignore it because this batch contains only one draw call.
216 * Because of URB corruption caused by allocating a previous GS unit
217 * URB entry to the VS unit, software is required to send a “GS NULL
218 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
219 * plus a dummy DRAW call before any case where VS will be taking over
223 gen6_blorp_emit_urb_config(struct brw_context
*brw
,
224 const brw_blorp_params
*params
)
227 OUT_BATCH(_3DSTATE_URB
<< 16 | (3 - 2));
228 OUT_BATCH(brw
->urb
.max_vs_entries
<< GEN6_URB_VS_ENTRIES_SHIFT
);
236 gen6_blorp_emit_blend_state(struct brw_context
*brw
,
237 const brw_blorp_params
*params
)
239 uint32_t cc_blend_state_offset
;
241 struct gen6_blend_state
*blend
= (struct gen6_blend_state
*)
242 brw_state_batch(brw
, AUB_TRACE_BLEND_STATE
,
243 sizeof(struct gen6_blend_state
), 64,
244 &cc_blend_state_offset
);
246 memset(blend
, 0, sizeof(*blend
));
248 blend
->blend1
.pre_blend_clamp_enable
= 1;
249 blend
->blend1
.post_blend_clamp_enable
= 1;
250 blend
->blend1
.clamp_range
= BRW_RENDERTARGET_CLAMPRANGE_FORMAT
;
252 blend
->blend1
.write_disable_r
= params
->color_write_disable
[0];
253 blend
->blend1
.write_disable_g
= params
->color_write_disable
[1];
254 blend
->blend1
.write_disable_b
= params
->color_write_disable
[2];
255 blend
->blend1
.write_disable_a
= params
->color_write_disable
[3];
257 return cc_blend_state_offset
;
263 gen6_blorp_emit_cc_state(struct brw_context
*brw
,
264 const brw_blorp_params
*params
)
266 uint32_t cc_state_offset
;
268 struct gen6_color_calc_state
*cc
= (struct gen6_color_calc_state
*)
269 brw_state_batch(brw
, AUB_TRACE_CC_STATE
,
270 sizeof(gen6_color_calc_state
), 64,
272 memset(cc
, 0, sizeof(*cc
));
274 return cc_state_offset
;
279 * \param out_offset is relative to
280 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
283 gen6_blorp_emit_depth_stencil_state(struct brw_context
*brw
,
284 const brw_blorp_params
*params
)
286 uint32_t depthstencil_offset
;
288 struct gen6_depth_stencil_state
*state
;
289 state
= (struct gen6_depth_stencil_state
*)
290 brw_state_batch(brw
, AUB_TRACE_DEPTH_STENCIL_STATE
,
292 &depthstencil_offset
);
293 memset(state
, 0, sizeof(*state
));
295 /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
296 * - 7.5.3.1 Depth Buffer Clear
297 * - 7.5.3.2 Depth Buffer Resolve
298 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
300 state
->ds2
.depth_write_enable
= 1;
301 if (params
->hiz_op
== GEN6_HIZ_OP_DEPTH_RESOLVE
) {
302 state
->ds2
.depth_test_enable
= 1;
303 state
->ds2
.depth_test_func
= BRW_COMPAREFUNCTION_NEVER
;
306 return depthstencil_offset
;
310 /* 3DSTATE_CC_STATE_POINTERS
312 * The pointer offsets are relative to
313 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
315 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
318 gen6_blorp_emit_cc_state_pointers(struct brw_context
*brw
,
319 const brw_blorp_params
*params
,
320 uint32_t cc_blend_state_offset
,
321 uint32_t depthstencil_offset
,
322 uint32_t cc_state_offset
)
325 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (4 - 2));
326 OUT_BATCH(cc_blend_state_offset
| 1); /* BLEND_STATE offset */
327 OUT_BATCH(depthstencil_offset
| 1); /* DEPTH_STENCIL_STATE offset */
328 OUT_BATCH(cc_state_offset
| 1); /* COLOR_CALC_STATE offset */
333 /* WM push constants */
335 gen6_blorp_emit_wm_constants(struct brw_context
*brw
,
336 const brw_blorp_params
*params
)
338 uint32_t wm_push_const_offset
;
340 void *constants
= brw_state_batch(brw
, AUB_TRACE_WM_CONSTANTS
,
341 sizeof(params
->wm_push_consts
),
342 32, &wm_push_const_offset
);
343 memcpy(constants
, ¶ms
->wm_push_consts
,
344 sizeof(params
->wm_push_consts
));
346 return wm_push_const_offset
;
350 /* SURFACE_STATE for renderbuffer or texture surface (see
351 * brw_update_renderbuffer_surface and brw_update_texture_surface)
354 gen6_blorp_emit_surface_state(struct brw_context
*brw
,
355 const brw_blorp_params
*params
,
356 const brw_blorp_surface_info
*surface
,
357 uint32_t read_domains
, uint32_t write_domain
)
359 uint32_t wm_surf_offset
;
360 uint32_t width
= surface
->width
;
361 uint32_t height
= surface
->height
;
362 if (surface
->num_samples
> 1) {
363 /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
364 * in samples. But SURFACE_STATE wants them in pixels, so we need to
365 * divide them each by 2.
370 struct intel_region
*region
= surface
->mt
->region
;
371 uint32_t tile_x
, tile_y
;
373 uint32_t *surf
= (uint32_t *)
374 brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
377 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
378 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
379 BRW_SURFACE_CUBEFACE_ENABLES
|
380 surface
->brw_surfaceformat
<< BRW_SURFACE_FORMAT_SHIFT
);
383 surf
[1] = (surface
->compute_tile_offsets(&tile_x
, &tile_y
) +
384 region
->bo
->offset64
);
386 surf
[2] = (0 << BRW_SURFACE_LOD_SHIFT
|
387 (width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
388 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
390 uint32_t tiling
= surface
->map_stencil_as_y_tiled
391 ? BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
392 : brw_get_surface_tiling_bits(region
->tiling
);
393 uint32_t pitch_bytes
= region
->pitch
;
394 if (surface
->map_stencil_as_y_tiled
)
397 0 << BRW_SURFACE_DEPTH_SHIFT
|
398 (pitch_bytes
- 1) << BRW_SURFACE_PITCH_SHIFT
);
400 surf
[4] = brw_get_surface_num_multisamples(surface
->num_samples
);
402 /* Note that the low bits of these fields are missing, so
403 * there's the possibility of getting in trouble.
405 assert(tile_x
% 4 == 0);
406 assert(tile_y
% 2 == 0);
407 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
408 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
409 (surface
->mt
->align_h
== 4 ?
410 BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
412 /* Emit relocation to surface contents */
413 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
416 surf
[1] - region
->bo
->offset64
,
417 read_domains
, write_domain
);
419 return wm_surf_offset
;
423 /* BINDING_TABLE. See brw_wm_binding_table(). */
425 gen6_blorp_emit_binding_table(struct brw_context
*brw
,
426 const brw_blorp_params
*params
,
427 uint32_t wm_surf_offset_renderbuffer
,
428 uint32_t wm_surf_offset_texture
)
430 uint32_t wm_bind_bo_offset
;
431 uint32_t *bind
= (uint32_t *)
432 brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
434 BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
,
437 bind
[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
] =
438 wm_surf_offset_renderbuffer
;
439 bind
[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
] = wm_surf_offset_texture
;
441 return wm_bind_bo_offset
;
446 * SAMPLER_STATE. See brw_update_sampler_state().
449 gen6_blorp_emit_sampler_state(struct brw_context
*brw
,
450 const brw_blorp_params
*params
)
452 uint32_t sampler_offset
;
454 struct brw_sampler_state
*sampler
= (struct brw_sampler_state
*)
455 brw_state_batch(brw
, AUB_TRACE_SAMPLER_STATE
,
456 sizeof(struct brw_sampler_state
),
457 32, &sampler_offset
);
458 memset(sampler
, 0, sizeof(*sampler
));
460 sampler
->ss0
.min_filter
= BRW_MAPFILTER_LINEAR
;
461 sampler
->ss0
.mip_filter
= BRW_MIPFILTER_NONE
;
462 sampler
->ss0
.mag_filter
= BRW_MAPFILTER_LINEAR
;
464 sampler
->ss1
.r_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
465 sampler
->ss1
.s_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
466 sampler
->ss1
.t_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
468 sampler
->ss0
.min_mag_neq
= 1;
472 sampler
->ss0
.lod_bias
= 0;
474 sampler
->ss0
.lod_preclamp
= 1; /* OpenGL mode */
475 sampler
->ss0
.default_color_mode
= 0; /* OpenGL/DX10 mode */
477 /* Set BaseMipLevel, MaxLOD, MinLOD:
479 * XXX: I don't think that using firstLevel, lastLevel works,
480 * because we always setup the surface state as if firstLevel ==
481 * level zero. Probably have to subtract firstLevel from each of
484 sampler
->ss0
.base_level
= U_FIXED(0, 1);
486 sampler
->ss1
.max_lod
= U_FIXED(0, 6);
487 sampler
->ss1
.min_lod
= U_FIXED(0, 6);
489 sampler
->ss3
.non_normalized_coord
= 1;
491 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN
|
492 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN
|
493 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN
;
494 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG
|
495 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG
|
496 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG
;
498 return sampler_offset
;
503 * 3DSTATE_SAMPLER_STATE_POINTERS. See upload_sampler_state_pointers().
506 gen6_blorp_emit_sampler_state_pointers(struct brw_context
*brw
,
507 const brw_blorp_params
*params
,
508 uint32_t sampler_offset
)
511 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS
<< 16 |
512 VS_SAMPLER_STATE_CHANGE
|
513 GS_SAMPLER_STATE_CHANGE
|
514 PS_SAMPLER_STATE_CHANGE
|
516 OUT_BATCH(0); /* VS */
517 OUT_BATCH(0); /* GS */
518 OUT_BATCH(sampler_offset
);
525 * Disable vertex shader.
528 gen6_blorp_emit_vs_disable(struct brw_context
*brw
,
529 const brw_blorp_params
*params
)
532 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
533 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
535 * [DevSNB] A pipeline flush must be programmed prior to a
536 * 3DSTATE_VS command that causes the VS Function Enable to
537 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
538 * command with CS stall bit set and a post sync operation.
540 intel_emit_post_sync_nonzero_flush(brw
);
543 /* Disable the push constant buffers. */
545 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 | (5 - 2));
553 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
565 * Disable the geometry shader.
568 gen6_blorp_emit_gs_disable(struct brw_context
*brw
,
569 const brw_blorp_params
*params
)
571 /* Disable all the constant buffers. */
573 OUT_BATCH(_3DSTATE_CONSTANT_GS
<< 16 | (5 - 2));
581 OUT_BATCH(_3DSTATE_GS
<< 16 | (7 - 2));
594 * Disable the clipper.
596 * The BLORP op emits a rectangle primitive, which requires clipping to
597 * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
598 * Section 1.3 "3D Primitives Overview":
600 * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
601 * Mode should be set to a value other than CLIPMODE_NORMAL.
603 * Also disable perspective divide. This doesn't change the clipper's
604 * output, but does spare a few electrons.
607 gen6_blorp_emit_clip_disable(struct brw_context
*brw
,
608 const brw_blorp_params
*params
)
611 OUT_BATCH(_3DSTATE_CLIP
<< 16 | (4 - 2));
613 OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE
);
621 * Disable ViewportTransformEnable (dw2.1)
623 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
624 * Primitives Overview":
625 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
626 * use of screen- space coordinates).
628 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
629 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
631 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
632 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
633 * SOLID: Any triangle or rectangle object found to be front-facing
634 * is rendered as a solid object. This setting is required when
635 * (rendering rectangle (RECTLIST) objects.
638 gen6_blorp_emit_sf_config(struct brw_context
*brw
,
639 const brw_blorp_params
*params
)
642 OUT_BATCH(_3DSTATE_SF
<< 16 | (20 - 2));
643 OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT
| /* only position */
644 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT
|
645 0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT
);
646 OUT_BATCH(0); /* dw2 */
647 OUT_BATCH(params
->dst
.num_samples
> 1 ? GEN6_SF_MSRAST_ON_PATTERN
: 0);
648 for (int i
= 0; i
< 16; ++i
)
655 * Enable or disable thread dispatch and set the HiZ op appropriately.
658 gen6_blorp_emit_wm_config(struct brw_context
*brw
,
659 const brw_blorp_params
*params
,
660 uint32_t prog_offset
,
661 brw_blorp_prog_data
*prog_data
)
663 uint32_t dw2
, dw4
, dw5
, dw6
;
665 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
666 * nonzero to prevent the GPU from hanging. While the documentation doesn't
667 * mention this explicitly, it notes that the valid range for the field is
668 * [1,39] = [2,40] threads, which excludes zero.
670 * To be safe (and to minimize extraneous code) we go ahead and fully
671 * configure the WM state whether or not there is a WM program.
674 dw2
= dw4
= dw5
= dw6
= 0;
675 switch (params
->hiz_op
) {
676 case GEN6_HIZ_OP_DEPTH_CLEAR
:
677 dw4
|= GEN6_WM_DEPTH_CLEAR
;
679 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
680 dw4
|= GEN6_WM_DEPTH_RESOLVE
;
682 case GEN6_HIZ_OP_HIZ_RESOLVE
:
683 dw4
|= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE
;
685 case GEN6_HIZ_OP_NONE
:
691 dw5
|= GEN6_WM_LINE_AA_WIDTH_1_0
;
692 dw5
|= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5
;
693 dw5
|= (brw
->max_wm_threads
- 1) << GEN6_WM_MAX_THREADS_SHIFT
;
694 dw6
|= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
; /* No interp */
695 dw6
|= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT
; /* No inputs from SF */
696 if (params
->use_wm_prog
) {
697 dw2
|= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT
; /* Up to 4 samplers */
698 dw4
|= prog_data
->first_curbe_grf
<< GEN6_WM_DISPATCH_START_GRF_SHIFT_0
;
699 dw5
|= GEN6_WM_16_DISPATCH_ENABLE
;
700 dw5
|= GEN6_WM_KILL_ENABLE
; /* TODO: temporarily smash on */
701 dw5
|= GEN6_WM_DISPATCH_ENABLE
; /* We are rendering */
704 if (params
->dst
.num_samples
> 1) {
705 dw6
|= GEN6_WM_MSRAST_ON_PATTERN
;
706 if (prog_data
&& prog_data
->persample_msaa_dispatch
)
707 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
709 dw6
|= GEN6_WM_MSDISPMODE_PERPIXEL
;
711 dw6
|= GEN6_WM_MSRAST_OFF_PIXEL
;
712 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
716 OUT_BATCH(_3DSTATE_WM
<< 16 | (9 - 2));
717 OUT_BATCH(params
->use_wm_prog
? prog_offset
: 0);
719 OUT_BATCH(0); /* No scratch needed */
723 OUT_BATCH(0); /* No other programs */
724 OUT_BATCH(0); /* No other programs */
730 gen6_blorp_emit_constant_ps(struct brw_context
*brw
,
731 const brw_blorp_params
*params
,
732 uint32_t wm_push_const_offset
)
734 /* Make sure the push constants fill an exact integer number of
737 assert(sizeof(brw_blorp_wm_push_constants
) % 32 == 0);
739 /* There must be at least one register worth of push constant data. */
740 assert(BRW_BLORP_NUM_PUSH_CONST_REGS
> 0);
742 /* Enable push constant buffer 0. */
744 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 |
745 GEN6_CONSTANT_BUFFER_0_ENABLE
|
747 OUT_BATCH(wm_push_const_offset
+ (BRW_BLORP_NUM_PUSH_CONST_REGS
- 1));
755 gen6_blorp_emit_constant_ps_disable(struct brw_context
*brw
,
756 const brw_blorp_params
*params
)
758 /* Disable the push constant buffers. */
760 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 | (5 - 2));
769 * 3DSTATE_BINDING_TABLE_POINTERS
772 gen6_blorp_emit_binding_table_pointers(struct brw_context
*brw
,
773 const brw_blorp_params
*params
,
774 uint32_t wm_bind_bo_offset
)
777 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
778 GEN6_BINDING_TABLE_MODIFY_PS
|
780 OUT_BATCH(0); /* vs -- ignored */
781 OUT_BATCH(0); /* gs -- ignored */
782 OUT_BATCH(wm_bind_bo_offset
); /* wm/ps */
788 gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw
,
789 const brw_blorp_params
*params
)
791 struct gl_context
*ctx
= &brw
->ctx
;
792 uint32_t draw_x
= params
->depth
.x_offset
;
793 uint32_t draw_y
= params
->depth
.y_offset
;
794 uint32_t tile_mask_x
, tile_mask_y
;
796 brw_get_depthstencil_tile_masks(params
->depth
.mt
,
800 &tile_mask_x
, &tile_mask_y
);
802 /* 3DSTATE_DEPTH_BUFFER */
804 uint32_t tile_x
= draw_x
& tile_mask_x
;
805 uint32_t tile_y
= draw_y
& tile_mask_y
;
807 intel_region_get_aligned_offset(params
->depth
.mt
->region
,
808 draw_x
& ~tile_mask_x
,
809 draw_y
& ~tile_mask_y
, false);
811 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
812 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
813 * Coordinate Offset X/Y":
815 * "The 3 LSBs of both offsets must be zero to ensure correct
818 * We have no guarantee that tile_x and tile_y are correctly aligned,
819 * since they are determined by the mipmap layout, which is only aligned
822 * So, to avoid hanging the GPU, just smash the low order 3 bits of
823 * tile_x and tile_y to 0. This is a temporary workaround until we come
824 * up with a better solution.
826 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
827 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
828 "Truncating offset, bad rendering may occur.\n");
832 intel_emit_post_sync_nonzero_flush(brw
);
833 intel_emit_depth_stall_flushes(brw
);
836 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
837 OUT_BATCH((params
->depth
.mt
->region
->pitch
- 1) |
838 params
->depth_format
<< 18 |
839 1 << 21 | /* separate stencil enable */
840 1 << 22 | /* hiz enable */
841 BRW_TILEWALK_YMAJOR
<< 26 |
842 1 << 27 | /* y-tiled */
843 BRW_SURFACE_2D
<< 29);
844 OUT_RELOC(params
->depth
.mt
->region
->bo
,
845 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
847 OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1 |
848 (params
->depth
.width
+ tile_x
- 1) << 6 |
849 (params
->depth
.height
+ tile_y
- 1) << 19);
857 /* 3DSTATE_HIER_DEPTH_BUFFER */
859 struct intel_region
*hiz_region
= params
->depth
.mt
->hiz_mt
->region
;
860 uint32_t hiz_offset
=
861 intel_region_get_aligned_offset(hiz_region
,
862 draw_x
& ~tile_mask_x
,
863 (draw_y
& ~tile_mask_y
) / 2, false);
866 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
867 OUT_BATCH(hiz_region
->pitch
- 1);
868 OUT_RELOC(hiz_region
->bo
,
869 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
874 /* 3DSTATE_STENCIL_BUFFER */
877 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
886 gen6_blorp_emit_depth_disable(struct brw_context
*brw
,
887 const brw_blorp_params
*params
)
889 intel_emit_post_sync_nonzero_flush(brw
);
890 intel_emit_depth_stall_flushes(brw
);
893 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
894 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
895 (BRW_SURFACE_NULL
<< 29));
904 OUT_BATCH(_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (3 - 2));
910 OUT_BATCH(_3DSTATE_STENCIL_BUFFER
<< 16 | (3 - 2));
917 /* 3DSTATE_CLEAR_PARAMS
919 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
920 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
921 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
924 gen6_blorp_emit_clear_params(struct brw_context
*brw
,
925 const brw_blorp_params
*params
)
928 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
929 GEN5_DEPTH_CLEAR_VALID
|
931 OUT_BATCH(params
->depth
.mt
? params
->depth
.mt
->depth_clear_value
: 0);
936 /* 3DSTATE_DRAWING_RECTANGLE */
938 gen6_blorp_emit_drawing_rectangle(struct brw_context
*brw
,
939 const brw_blorp_params
*params
)
942 intel_emit_post_sync_nonzero_flush(brw
);
945 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
947 OUT_BATCH(((params
->x1
- 1) & 0xffff) |
948 ((params
->y1
- 1) << 16));
953 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
955 gen6_blorp_emit_viewport_state(struct brw_context
*brw
,
956 const brw_blorp_params
*params
)
958 struct brw_cc_viewport
*ccv
;
959 uint32_t cc_vp_offset
;
961 ccv
= (struct brw_cc_viewport
*)brw_state_batch(brw
, AUB_TRACE_CC_VP_STATE
,
965 ccv
->min_depth
= 0.0;
966 ccv
->max_depth
= 1.0;
969 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS
<< 16 | (4 - 2) |
970 GEN6_CC_VIEWPORT_MODIFY
);
971 OUT_BATCH(0); /* clip VP */
972 OUT_BATCH(0); /* SF VP */
973 OUT_BATCH(cc_vp_offset
);
980 gen6_blorp_emit_primitive(struct brw_context
*brw
,
981 const brw_blorp_params
*params
)
984 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
985 _3DPRIM_RECTLIST
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
986 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
);
987 OUT_BATCH(3); /* vertex count per instance */
989 OUT_BATCH(1); /* instance count */
994 /* Only used on Sandybridge; harmless to set elsewhere. */
995 brw
->batch
.need_workaround_flush
= true;
999 * \brief Execute a blit or render pass operation.
1001 * To execute the operation, this function manually constructs and emits a
1002 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1003 * constructing and after emitting the batch.
1005 * This function alters no GL state.
1008 gen6_blorp_exec(struct brw_context
*brw
,
1009 const brw_blorp_params
*params
)
1011 brw_blorp_prog_data
*prog_data
= NULL
;
1012 uint32_t cc_blend_state_offset
= 0;
1013 uint32_t cc_state_offset
= 0;
1014 uint32_t depthstencil_offset
;
1015 uint32_t wm_push_const_offset
= 0;
1016 uint32_t wm_bind_bo_offset
= 0;
1018 uint32_t prog_offset
= params
->get_wm_prog(brw
, &prog_data
);
1020 /* Emit workaround flushes when we switch from drawing to blorping. */
1021 brw
->batch
.need_workaround_flush
= true;
1023 gen6_emit_3dstate_multisample(brw
, params
->dst
.num_samples
);
1024 gen6_emit_3dstate_sample_mask(brw
,
1025 params
->dst
.num_samples
> 1 ?
1026 (1 << params
->dst
.num_samples
) - 1 : 1);
1027 gen6_blorp_emit_state_base_address(brw
, params
);
1028 gen6_blorp_emit_vertices(brw
, params
);
1029 gen6_blorp_emit_urb_config(brw
, params
);
1030 if (params
->use_wm_prog
) {
1031 cc_blend_state_offset
= gen6_blorp_emit_blend_state(brw
, params
);
1032 cc_state_offset
= gen6_blorp_emit_cc_state(brw
, params
);
1034 depthstencil_offset
= gen6_blorp_emit_depth_stencil_state(brw
, params
);
1035 gen6_blorp_emit_cc_state_pointers(brw
, params
, cc_blend_state_offset
,
1036 depthstencil_offset
, cc_state_offset
);
1037 if (params
->use_wm_prog
) {
1038 uint32_t wm_surf_offset_renderbuffer
;
1039 uint32_t wm_surf_offset_texture
= 0;
1040 uint32_t sampler_offset
;
1041 wm_push_const_offset
= gen6_blorp_emit_wm_constants(brw
, params
);
1042 intel_miptree_used_for_rendering(params
->dst
.mt
);
1043 wm_surf_offset_renderbuffer
=
1044 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->dst
,
1045 I915_GEM_DOMAIN_RENDER
,
1046 I915_GEM_DOMAIN_RENDER
);
1047 if (params
->src
.mt
) {
1048 wm_surf_offset_texture
=
1049 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->src
,
1050 I915_GEM_DOMAIN_SAMPLER
, 0);
1053 gen6_blorp_emit_binding_table(brw
, params
,
1054 wm_surf_offset_renderbuffer
,
1055 wm_surf_offset_texture
);
1056 sampler_offset
= gen6_blorp_emit_sampler_state(brw
, params
);
1057 gen6_blorp_emit_sampler_state_pointers(brw
, params
, sampler_offset
);
1059 gen6_blorp_emit_vs_disable(brw
, params
);
1060 gen6_blorp_emit_gs_disable(brw
, params
);
1061 gen6_blorp_emit_clip_disable(brw
, params
);
1062 gen6_blorp_emit_sf_config(brw
, params
);
1063 if (params
->use_wm_prog
)
1064 gen6_blorp_emit_constant_ps(brw
, params
, wm_push_const_offset
);
1066 gen6_blorp_emit_constant_ps_disable(brw
, params
);
1067 gen6_blorp_emit_wm_config(brw
, params
, prog_offset
, prog_data
);
1068 if (params
->use_wm_prog
)
1069 gen6_blorp_emit_binding_table_pointers(brw
, params
, wm_bind_bo_offset
);
1070 gen6_blorp_emit_viewport_state(brw
, params
);
1072 if (params
->depth
.mt
)
1073 gen6_blorp_emit_depth_stencil_config(brw
, params
);
1075 gen6_blorp_emit_depth_disable(brw
, params
);
1076 gen6_blorp_emit_clear_params(brw
, params
);
1077 gen6_blorp_emit_drawing_rectangle(brw
, params
);
1078 gen6_blorp_emit_primitive(brw
, params
);