2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
28 #include "intel_mipmap_tree.h"
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_state.h"
34 #include "brw_blorp.h"
35 #include "gen6_blorp.h"
38 * \name Constants for BLORP VBO
41 #define GEN6_BLORP_NUM_VERTICES 3
42 #define GEN6_BLORP_NUM_VUE_ELEMS 8
43 #define GEN6_BLORP_VBO_SIZE (GEN6_BLORP_NUM_VERTICES \
44 * GEN6_BLORP_NUM_VUE_ELEMS \
49 gen6_blorp_emit_batch_head(struct brw_context
*brw
,
50 const brw_blorp_params
*params
)
52 struct gl_context
*ctx
= &brw
->ctx
;
54 /* To ensure that the batch contains only the resolve, flush the batch
55 * before beginning and after finishing emitting the resolve packets.
62 * CMD_STATE_BASE_ADDRESS
64 * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS:
65 * The following commands must be reissued following any change to the
68 * 3DSTATE_BINDING_TABLE_POINTERS
69 * 3DSTATE_SAMPLER_STATE_POINTERS
70 * 3DSTATE_VIEWPORT_STATE_POINTERS
71 * MEDIA_STATE_POINTERS
74 gen6_blorp_emit_state_base_address(struct brw_context
*brw
,
75 const brw_blorp_params
*params
)
78 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
79 OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */
80 /* SurfaceStateBaseAddress */
81 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
82 /* DynamicStateBaseAddress */
83 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
84 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
85 OUT_BATCH(1); /* IndirectObjectBaseAddress */
86 if (params
->use_wm_prog
) {
87 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
88 1); /* Instruction base address: shader kernels */
90 OUT_BATCH(1); /* InstructionBaseAddress */
92 OUT_BATCH(1); /* GeneralStateUpperBound */
93 /* Dynamic state upper bound. Although the documentation says that
94 * programming it to zero will cause it to be ignored, that is a lie.
95 * If this isn't programmed to a real bound, the sampler border color
96 * pointer is rejected, causing border color to mysteriously fail.
98 OUT_BATCH(0xfffff001);
99 OUT_BATCH(1); /* IndirectObjectUpperBound*/
100 OUT_BATCH(1); /* InstructionAccessUpperBound */
106 gen6_blorp_emit_vertices(struct brw_context
*brw
,
107 const brw_blorp_params
*params
)
109 uint32_t vertex_offset
;
111 /* Setup VBO for the rectangle primitive..
113 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
114 * vertices. The vertices reside in screen space with DirectX coordinates
115 * (that is, (0, 0) is the upper left corner).
122 * Since the VS is disabled, the clipper loads each VUE directly from
123 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
124 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
125 * dw0: Reserved, MBZ.
126 * dw1: Render Target Array Index. The HiZ op does not use indexed
127 * vertices, so set the dword to 0.
128 * dw2: Viewport Index. The HiZ op disables viewport mapping and
129 * scissoring, so set the dword to 0.
130 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
131 * set the dword to 0.
132 * dw4: Vertex Position X.
133 * dw5: Vertex Position Y.
134 * dw6: Vertex Position Z.
135 * dw7: Vertex Position W.
137 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
138 * "Vertex URB Entry (VUE) Formats".
143 const float vertices
[GEN6_BLORP_VBO_SIZE
] = {
144 /* v0 */ 0, 0, 0, 0, (float) params
->x0
, (float) params
->y1
, 0, 1,
145 /* v1 */ 0, 0, 0, 0, (float) params
->x1
, (float) params
->y1
, 0, 1,
146 /* v2 */ 0, 0, 0, 0, (float) params
->x0
, (float) params
->y0
, 0, 1,
149 vertex_data
= (float *) brw_state_batch(brw
, AUB_TRACE_VERTEX_BUFFER
,
150 GEN6_BLORP_VBO_SIZE
, 32,
152 memcpy(vertex_data
, vertices
, GEN6_BLORP_VBO_SIZE
);
155 /* 3DSTATE_VERTEX_BUFFERS */
157 const int num_buffers
= 1;
158 const int batch_length
= 1 + 4 * num_buffers
;
160 uint32_t dw0
= GEN6_VB0_ACCESS_VERTEXDATA
|
161 (GEN6_BLORP_NUM_VUE_ELEMS
* sizeof(float)) << BRW_VB0_PITCH_SHIFT
;
164 dw0
|= GEN7_VB0_ADDRESS_MODIFYENABLE
;
166 BEGIN_BATCH(batch_length
);
167 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS
<< 16) | (batch_length
- 2));
170 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
173 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
174 vertex_offset
+ GEN6_BLORP_VBO_SIZE
- 1);
179 /* 3DSTATE_VERTEX_ELEMENTS
181 * Fetch dwords 0 - 7 from each VUE. See the comments above where
182 * the vertex_bo is filled with data.
185 const int num_elements
= 2;
186 const int batch_length
= 1 + 2 * num_elements
;
188 BEGIN_BATCH(batch_length
);
189 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (batch_length
- 2));
191 OUT_BATCH(GEN6_VE0_VALID
|
192 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
193 0 << BRW_VE0_SRC_OFFSET_SHIFT
);
194 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
195 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
196 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
197 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
199 OUT_BATCH(GEN6_VE0_VALID
|
200 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
201 16 << BRW_VE0_SRC_OFFSET_SHIFT
);
202 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
203 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
204 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
205 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
213 * Assign the entire URB to the VS. Even though the VS disabled, URB space
214 * is still needed because the clipper loads the VUE's from the URB. From
215 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
216 * Dword 1.15:0 "VS Number of URB Entries":
217 * This field is always used (even if VS Function Enable is DISABLED).
219 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
220 * safely ignore it because this batch contains only one draw call.
221 * Because of URB corruption caused by allocating a previous GS unit
222 * URB entry to the VS unit, software is required to send a “GS NULL
223 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
224 * plus a dummy DRAW call before any case where VS will be taking over
228 gen6_blorp_emit_urb_config(struct brw_context
*brw
,
229 const brw_blorp_params
*params
)
232 OUT_BATCH(_3DSTATE_URB
<< 16 | (3 - 2));
233 OUT_BATCH(brw
->urb
.max_vs_entries
<< GEN6_URB_VS_ENTRIES_SHIFT
);
241 gen6_blorp_emit_blend_state(struct brw_context
*brw
,
242 const brw_blorp_params
*params
)
244 uint32_t cc_blend_state_offset
;
246 struct gen6_blend_state
*blend
= (struct gen6_blend_state
*)
247 brw_state_batch(brw
, AUB_TRACE_BLEND_STATE
,
248 sizeof(struct gen6_blend_state
), 64,
249 &cc_blend_state_offset
);
251 memset(blend
, 0, sizeof(*blend
));
253 blend
->blend1
.pre_blend_clamp_enable
= 1;
254 blend
->blend1
.post_blend_clamp_enable
= 1;
255 blend
->blend1
.clamp_range
= BRW_RENDERTARGET_CLAMPRANGE_FORMAT
;
257 blend
->blend1
.write_disable_r
= params
->color_write_disable
[0];
258 blend
->blend1
.write_disable_g
= params
->color_write_disable
[1];
259 blend
->blend1
.write_disable_b
= params
->color_write_disable
[2];
260 blend
->blend1
.write_disable_a
= params
->color_write_disable
[3];
262 /* When blitting from an XRGB source to a ARGB destination, we need to
263 * interpret the missing channel as 1.0. Blending can do that for us:
264 * we simply use the RGB values from the fragment shader ("source RGB"),
265 * but smash the alpha channel to 1.
267 if (params
->src
.mt
&&
268 _mesa_get_format_bits(params
->dst
.mt
->format
, GL_ALPHA_BITS
) > 0 &&
269 _mesa_get_format_bits(params
->src
.mt
->format
, GL_ALPHA_BITS
) == 0) {
270 blend
->blend0
.blend_enable
= 1;
271 blend
->blend0
.ia_blend_enable
= 1;
273 blend
->blend0
.blend_func
= BRW_BLENDFUNCTION_ADD
;
274 blend
->blend0
.ia_blend_func
= BRW_BLENDFUNCTION_ADD
;
276 blend
->blend0
.source_blend_factor
= BRW_BLENDFACTOR_SRC_COLOR
;
277 blend
->blend0
.dest_blend_factor
= BRW_BLENDFACTOR_ZERO
;
278 blend
->blend0
.ia_source_blend_factor
= BRW_BLENDFACTOR_ONE
;
279 blend
->blend0
.ia_dest_blend_factor
= BRW_BLENDFACTOR_ZERO
;
282 return cc_blend_state_offset
;
288 gen6_blorp_emit_cc_state(struct brw_context
*brw
,
289 const brw_blorp_params
*params
)
291 uint32_t cc_state_offset
;
293 struct gen6_color_calc_state
*cc
= (struct gen6_color_calc_state
*)
294 brw_state_batch(brw
, AUB_TRACE_CC_STATE
,
295 sizeof(gen6_color_calc_state
), 64,
297 memset(cc
, 0, sizeof(*cc
));
299 return cc_state_offset
;
304 * \param out_offset is relative to
305 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
308 gen6_blorp_emit_depth_stencil_state(struct brw_context
*brw
,
309 const brw_blorp_params
*params
)
311 uint32_t depthstencil_offset
;
313 struct gen6_depth_stencil_state
*state
;
314 state
= (struct gen6_depth_stencil_state
*)
315 brw_state_batch(brw
, AUB_TRACE_DEPTH_STENCIL_STATE
,
317 &depthstencil_offset
);
318 memset(state
, 0, sizeof(*state
));
320 /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
321 * - 7.5.3.1 Depth Buffer Clear
322 * - 7.5.3.2 Depth Buffer Resolve
323 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
325 state
->ds2
.depth_write_enable
= 1;
326 if (params
->hiz_op
== GEN6_HIZ_OP_DEPTH_RESOLVE
) {
327 state
->ds2
.depth_test_enable
= 1;
328 state
->ds2
.depth_test_func
= BRW_COMPAREFUNCTION_NEVER
;
331 return depthstencil_offset
;
335 /* 3DSTATE_CC_STATE_POINTERS
337 * The pointer offsets are relative to
338 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
340 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
343 gen6_blorp_emit_cc_state_pointers(struct brw_context
*brw
,
344 const brw_blorp_params
*params
,
345 uint32_t cc_blend_state_offset
,
346 uint32_t depthstencil_offset
,
347 uint32_t cc_state_offset
)
350 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (4 - 2));
351 OUT_BATCH(cc_blend_state_offset
| 1); /* BLEND_STATE offset */
352 OUT_BATCH(depthstencil_offset
| 1); /* DEPTH_STENCIL_STATE offset */
353 OUT_BATCH(cc_state_offset
| 1); /* COLOR_CALC_STATE offset */
358 /* WM push constants */
360 gen6_blorp_emit_wm_constants(struct brw_context
*brw
,
361 const brw_blorp_params
*params
)
363 uint32_t wm_push_const_offset
;
365 void *constants
= brw_state_batch(brw
, AUB_TRACE_WM_CONSTANTS
,
366 sizeof(params
->wm_push_consts
),
367 32, &wm_push_const_offset
);
368 memcpy(constants
, ¶ms
->wm_push_consts
,
369 sizeof(params
->wm_push_consts
));
371 return wm_push_const_offset
;
375 /* SURFACE_STATE for renderbuffer or texture surface (see
376 * brw_update_renderbuffer_surface and brw_update_texture_surface)
379 gen6_blorp_emit_surface_state(struct brw_context
*brw
,
380 const brw_blorp_params
*params
,
381 const brw_blorp_surface_info
*surface
,
382 uint32_t read_domains
, uint32_t write_domain
)
384 uint32_t wm_surf_offset
;
385 uint32_t width
= surface
->width
;
386 uint32_t height
= surface
->height
;
387 if (surface
->num_samples
> 1) {
388 /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
389 * in samples. But SURFACE_STATE wants them in pixels, so we need to
390 * divide them each by 2.
395 struct intel_region
*region
= surface
->mt
->region
;
396 uint32_t tile_x
, tile_y
;
398 uint32_t *surf
= (uint32_t *)
399 brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
402 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
403 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
404 BRW_SURFACE_CUBEFACE_ENABLES
|
405 surface
->brw_surfaceformat
<< BRW_SURFACE_FORMAT_SHIFT
);
408 surf
[1] = (surface
->compute_tile_offsets(&tile_x
, &tile_y
) +
411 surf
[2] = (0 << BRW_SURFACE_LOD_SHIFT
|
412 (width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
413 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
415 uint32_t tiling
= surface
->map_stencil_as_y_tiled
416 ? BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
417 : brw_get_surface_tiling_bits(region
->tiling
);
418 uint32_t pitch_bytes
= region
->pitch
;
419 if (surface
->map_stencil_as_y_tiled
)
422 0 << BRW_SURFACE_DEPTH_SHIFT
|
423 (pitch_bytes
- 1) << BRW_SURFACE_PITCH_SHIFT
);
425 surf
[4] = brw_get_surface_num_multisamples(surface
->num_samples
);
427 /* Note that the low bits of these fields are missing, so
428 * there's the possibility of getting in trouble.
430 assert(tile_x
% 4 == 0);
431 assert(tile_y
% 2 == 0);
432 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
433 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
434 (surface
->mt
->align_h
== 4 ?
435 BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
437 /* Emit relocation to surface contents */
438 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
441 surf
[1] - region
->bo
->offset
,
442 read_domains
, write_domain
);
444 return wm_surf_offset
;
448 /* BINDING_TABLE. See brw_wm_binding_table(). */
450 gen6_blorp_emit_binding_table(struct brw_context
*brw
,
451 const brw_blorp_params
*params
,
452 uint32_t wm_surf_offset_renderbuffer
,
453 uint32_t wm_surf_offset_texture
)
455 uint32_t wm_bind_bo_offset
;
456 uint32_t *bind
= (uint32_t *)
457 brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
459 BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
,
462 bind
[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
] =
463 wm_surf_offset_renderbuffer
;
464 bind
[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
] = wm_surf_offset_texture
;
466 return wm_bind_bo_offset
;
471 * SAMPLER_STATE. See brw_update_sampler_state().
474 gen6_blorp_emit_sampler_state(struct brw_context
*brw
,
475 const brw_blorp_params
*params
)
477 uint32_t sampler_offset
;
479 struct brw_sampler_state
*sampler
= (struct brw_sampler_state
*)
480 brw_state_batch(brw
, AUB_TRACE_SAMPLER_STATE
,
481 sizeof(struct brw_sampler_state
),
482 32, &sampler_offset
);
483 memset(sampler
, 0, sizeof(*sampler
));
485 sampler
->ss0
.min_filter
= BRW_MAPFILTER_LINEAR
;
486 sampler
->ss0
.mip_filter
= BRW_MIPFILTER_NONE
;
487 sampler
->ss0
.mag_filter
= BRW_MAPFILTER_LINEAR
;
489 sampler
->ss1
.r_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
490 sampler
->ss1
.s_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
491 sampler
->ss1
.t_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
493 sampler
->ss0
.min_mag_neq
= 1;
497 sampler
->ss0
.lod_bias
= 0;
499 sampler
->ss0
.lod_preclamp
= 1; /* OpenGL mode */
500 sampler
->ss0
.default_color_mode
= 0; /* OpenGL/DX10 mode */
502 /* Set BaseMipLevel, MaxLOD, MinLOD:
504 * XXX: I don't think that using firstLevel, lastLevel works,
505 * because we always setup the surface state as if firstLevel ==
506 * level zero. Probably have to subtract firstLevel from each of
509 sampler
->ss0
.base_level
= U_FIXED(0, 1);
511 sampler
->ss1
.max_lod
= U_FIXED(0, 6);
512 sampler
->ss1
.min_lod
= U_FIXED(0, 6);
514 sampler
->ss3
.non_normalized_coord
= 1;
516 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN
|
517 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN
|
518 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN
;
519 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG
|
520 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG
|
521 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG
;
523 return sampler_offset
;
528 * 3DSTATE_SAMPLER_STATE_POINTERS. See upload_sampler_state_pointers().
531 gen6_blorp_emit_sampler_state_pointers(struct brw_context
*brw
,
532 const brw_blorp_params
*params
,
533 uint32_t sampler_offset
)
536 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS
<< 16 |
537 VS_SAMPLER_STATE_CHANGE
|
538 GS_SAMPLER_STATE_CHANGE
|
539 PS_SAMPLER_STATE_CHANGE
|
541 OUT_BATCH(0); /* VS */
542 OUT_BATCH(0); /* GS */
543 OUT_BATCH(sampler_offset
);
550 * Disable vertex shader.
553 gen6_blorp_emit_vs_disable(struct brw_context
*brw
,
554 const brw_blorp_params
*params
)
557 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
558 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
560 * [DevSNB] A pipeline flush must be programmed prior to a
561 * 3DSTATE_VS command that causes the VS Function Enable to
562 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
563 * command with CS stall bit set and a post sync operation.
565 intel_emit_post_sync_nonzero_flush(brw
);
568 /* Disable the push constant buffers. */
570 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 | (5 - 2));
578 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
590 * Disable the geometry shader.
593 gen6_blorp_emit_gs_disable(struct brw_context
*brw
,
594 const brw_blorp_params
*params
)
596 /* Disable all the constant buffers. */
598 OUT_BATCH(_3DSTATE_CONSTANT_GS
<< 16 | (5 - 2));
606 OUT_BATCH(_3DSTATE_GS
<< 16 | (7 - 2));
619 * Disable the clipper.
621 * The BLORP op emits a rectangle primitive, which requires clipping to
622 * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
623 * Section 1.3 "3D Primitives Overview":
625 * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
626 * Mode should be set to a value other than CLIPMODE_NORMAL.
628 * Also disable perspective divide. This doesn't change the clipper's
629 * output, but does spare a few electrons.
632 gen6_blorp_emit_clip_disable(struct brw_context
*brw
,
633 const brw_blorp_params
*params
)
636 OUT_BATCH(_3DSTATE_CLIP
<< 16 | (4 - 2));
638 OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE
);
646 * Disable ViewportTransformEnable (dw2.1)
648 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
649 * Primitives Overview":
650 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
651 * use of screen- space coordinates).
653 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
654 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
656 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
657 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
658 * SOLID: Any triangle or rectangle object found to be front-facing
659 * is rendered as a solid object. This setting is required when
660 * (rendering rectangle (RECTLIST) objects.
663 gen6_blorp_emit_sf_config(struct brw_context
*brw
,
664 const brw_blorp_params
*params
)
667 OUT_BATCH(_3DSTATE_SF
<< 16 | (20 - 2));
668 OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT
| /* only position */
669 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT
|
670 0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT
);
671 OUT_BATCH(0); /* dw2 */
672 OUT_BATCH(params
->num_samples
> 1 ? GEN6_SF_MSRAST_ON_PATTERN
: 0);
673 for (int i
= 0; i
< 16; ++i
)
680 * Enable or disable thread dispatch and set the HiZ op appropriately.
683 gen6_blorp_emit_wm_config(struct brw_context
*brw
,
684 const brw_blorp_params
*params
,
685 uint32_t prog_offset
,
686 brw_blorp_prog_data
*prog_data
)
688 uint32_t dw2
, dw4
, dw5
, dw6
;
690 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
691 * nonzero to prevent the GPU from hanging. While the documentation doesn't
692 * mention this explicitly, it notes that the valid range for the field is
693 * [1,39] = [2,40] threads, which excludes zero.
695 * To be safe (and to minimize extraneous code) we go ahead and fully
696 * configure the WM state whether or not there is a WM program.
699 dw2
= dw4
= dw5
= dw6
= 0;
700 switch (params
->hiz_op
) {
701 case GEN6_HIZ_OP_DEPTH_CLEAR
:
702 dw4
|= GEN6_WM_DEPTH_CLEAR
;
704 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
705 dw4
|= GEN6_WM_DEPTH_RESOLVE
;
707 case GEN6_HIZ_OP_HIZ_RESOLVE
:
708 dw4
|= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE
;
710 case GEN6_HIZ_OP_NONE
:
716 dw5
|= GEN6_WM_LINE_AA_WIDTH_1_0
;
717 dw5
|= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5
;
718 dw5
|= (brw
->max_wm_threads
- 1) << GEN6_WM_MAX_THREADS_SHIFT
;
719 dw6
|= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
; /* No interp */
720 dw6
|= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT
; /* No inputs from SF */
721 if (params
->use_wm_prog
) {
722 dw2
|= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT
; /* Up to 4 samplers */
723 dw4
|= prog_data
->first_curbe_grf
<< GEN6_WM_DISPATCH_START_GRF_SHIFT_0
;
724 dw5
|= GEN6_WM_16_DISPATCH_ENABLE
;
725 dw5
|= GEN6_WM_KILL_ENABLE
; /* TODO: temporarily smash on */
726 dw5
|= GEN6_WM_DISPATCH_ENABLE
; /* We are rendering */
729 if (params
->num_samples
> 1) {
730 dw6
|= GEN6_WM_MSRAST_ON_PATTERN
;
731 if (prog_data
&& prog_data
->persample_msaa_dispatch
)
732 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
734 dw6
|= GEN6_WM_MSDISPMODE_PERPIXEL
;
736 dw6
|= GEN6_WM_MSRAST_OFF_PIXEL
;
737 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
741 OUT_BATCH(_3DSTATE_WM
<< 16 | (9 - 2));
742 OUT_BATCH(params
->use_wm_prog
? prog_offset
: 0);
744 OUT_BATCH(0); /* No scratch needed */
748 OUT_BATCH(0); /* No other programs */
749 OUT_BATCH(0); /* No other programs */
755 gen6_blorp_emit_constant_ps(struct brw_context
*brw
,
756 const brw_blorp_params
*params
,
757 uint32_t wm_push_const_offset
)
759 /* Make sure the push constants fill an exact integer number of
762 assert(sizeof(brw_blorp_wm_push_constants
) % 32 == 0);
764 /* There must be at least one register worth of push constant data. */
765 assert(BRW_BLORP_NUM_PUSH_CONST_REGS
> 0);
767 /* Enable push constant buffer 0. */
769 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 |
770 GEN6_CONSTANT_BUFFER_0_ENABLE
|
772 OUT_BATCH(wm_push_const_offset
+ (BRW_BLORP_NUM_PUSH_CONST_REGS
- 1));
780 gen6_blorp_emit_constant_ps_disable(struct brw_context
*brw
,
781 const brw_blorp_params
*params
)
783 /* Disable the push constant buffers. */
785 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 | (5 - 2));
794 * 3DSTATE_BINDING_TABLE_POINTERS
797 gen6_blorp_emit_binding_table_pointers(struct brw_context
*brw
,
798 const brw_blorp_params
*params
,
799 uint32_t wm_bind_bo_offset
)
802 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
803 GEN6_BINDING_TABLE_MODIFY_PS
|
805 OUT_BATCH(0); /* vs -- ignored */
806 OUT_BATCH(0); /* gs -- ignored */
807 OUT_BATCH(wm_bind_bo_offset
); /* wm/ps */
813 gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw
,
814 const brw_blorp_params
*params
)
816 struct gl_context
*ctx
= &brw
->ctx
;
817 uint32_t draw_x
= params
->depth
.x_offset
;
818 uint32_t draw_y
= params
->depth
.y_offset
;
819 uint32_t tile_mask_x
, tile_mask_y
;
821 brw_get_depthstencil_tile_masks(params
->depth
.mt
,
825 &tile_mask_x
, &tile_mask_y
);
827 /* 3DSTATE_DEPTH_BUFFER */
829 uint32_t tile_x
= draw_x
& tile_mask_x
;
830 uint32_t tile_y
= draw_y
& tile_mask_y
;
832 intel_region_get_aligned_offset(params
->depth
.mt
->region
,
833 draw_x
& ~tile_mask_x
,
834 draw_y
& ~tile_mask_y
, false);
836 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
837 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
838 * Coordinate Offset X/Y":
840 * "The 3 LSBs of both offsets must be zero to ensure correct
843 * We have no guarantee that tile_x and tile_y are correctly aligned,
844 * since they are determined by the mipmap layout, which is only aligned
847 * So, to avoid hanging the GPU, just smash the low order 3 bits of
848 * tile_x and tile_y to 0. This is a temporary workaround until we come
849 * up with a better solution.
851 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
852 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
853 "Truncating offset, bad rendering may occur.\n");
857 intel_emit_post_sync_nonzero_flush(brw
);
858 intel_emit_depth_stall_flushes(brw
);
861 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
862 OUT_BATCH((params
->depth
.mt
->region
->pitch
- 1) |
863 params
->depth_format
<< 18 |
864 1 << 21 | /* separate stencil enable */
865 1 << 22 | /* hiz enable */
866 BRW_TILEWALK_YMAJOR
<< 26 |
867 1 << 27 | /* y-tiled */
868 BRW_SURFACE_2D
<< 29);
869 OUT_RELOC(params
->depth
.mt
->region
->bo
,
870 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
872 OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1 |
873 (params
->depth
.width
+ tile_x
- 1) << 6 |
874 (params
->depth
.height
+ tile_y
- 1) << 19);
882 /* 3DSTATE_HIER_DEPTH_BUFFER */
884 struct intel_region
*hiz_region
= params
->depth
.mt
->hiz_mt
->region
;
885 uint32_t hiz_offset
=
886 intel_region_get_aligned_offset(hiz_region
,
887 draw_x
& ~tile_mask_x
,
888 (draw_y
& ~tile_mask_y
) / 2, false);
891 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
892 OUT_BATCH(hiz_region
->pitch
- 1);
893 OUT_RELOC(hiz_region
->bo
,
894 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
899 /* 3DSTATE_STENCIL_BUFFER */
902 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
911 gen6_blorp_emit_depth_disable(struct brw_context
*brw
,
912 const brw_blorp_params
*params
)
915 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
916 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
917 (BRW_SURFACE_NULL
<< 29));
927 /* 3DSTATE_CLEAR_PARAMS
929 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
930 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
931 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
934 gen6_blorp_emit_clear_params(struct brw_context
*brw
,
935 const brw_blorp_params
*params
)
938 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
939 GEN5_DEPTH_CLEAR_VALID
|
941 OUT_BATCH(params
->depth
.mt
? params
->depth
.mt
->depth_clear_value
: 0);
946 /* 3DSTATE_DRAWING_RECTANGLE */
948 gen6_blorp_emit_drawing_rectangle(struct brw_context
*brw
,
949 const brw_blorp_params
*params
)
952 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
954 OUT_BATCH(((params
->x1
- 1) & 0xffff) |
955 ((params
->y1
- 1) << 16));
960 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
962 gen6_blorp_emit_viewport_state(struct brw_context
*brw
,
963 const brw_blorp_params
*params
)
965 struct brw_cc_viewport
*ccv
;
966 uint32_t cc_vp_offset
;
968 ccv
= (struct brw_cc_viewport
*)brw_state_batch(brw
, AUB_TRACE_CC_VP_STATE
,
972 ccv
->min_depth
= 0.0;
973 ccv
->max_depth
= 1.0;
976 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS
<< 16 | (4 - 2) |
977 GEN6_CC_VIEWPORT_MODIFY
);
978 OUT_BATCH(0); /* clip VP */
979 OUT_BATCH(0); /* SF VP */
980 OUT_BATCH(cc_vp_offset
);
987 gen6_blorp_emit_primitive(struct brw_context
*brw
,
988 const brw_blorp_params
*params
)
991 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
992 _3DPRIM_RECTLIST
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
993 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
);
994 OUT_BATCH(3); /* vertex count per instance */
996 OUT_BATCH(1); /* instance count */
1004 * \brief Execute a blit or render pass operation.
1006 * To execute the operation, this function manually constructs and emits a
1007 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1008 * constructing and after emitting the batch.
1010 * This function alters no GL state.
1013 gen6_blorp_exec(struct brw_context
*brw
,
1014 const brw_blorp_params
*params
)
1016 brw_blorp_prog_data
*prog_data
= NULL
;
1017 uint32_t cc_blend_state_offset
= 0;
1018 uint32_t cc_state_offset
= 0;
1019 uint32_t depthstencil_offset
;
1020 uint32_t wm_push_const_offset
= 0;
1021 uint32_t wm_bind_bo_offset
= 0;
1023 uint32_t prog_offset
= params
->get_wm_prog(brw
, &prog_data
);
1024 gen6_blorp_emit_batch_head(brw
, params
);
1025 gen6_emit_3dstate_multisample(brw
, params
->num_samples
);
1026 gen6_emit_3dstate_sample_mask(brw
, params
->num_samples
, 1.0, false, ~0u);
1027 gen6_blorp_emit_state_base_address(brw
, params
);
1028 gen6_blorp_emit_vertices(brw
, params
);
1029 gen6_blorp_emit_urb_config(brw
, params
);
1030 if (params
->use_wm_prog
) {
1031 cc_blend_state_offset
= gen6_blorp_emit_blend_state(brw
, params
);
1032 cc_state_offset
= gen6_blorp_emit_cc_state(brw
, params
);
1034 depthstencil_offset
= gen6_blorp_emit_depth_stencil_state(brw
, params
);
1035 gen6_blorp_emit_cc_state_pointers(brw
, params
, cc_blend_state_offset
,
1036 depthstencil_offset
, cc_state_offset
);
1037 if (params
->use_wm_prog
) {
1038 uint32_t wm_surf_offset_renderbuffer
;
1039 uint32_t wm_surf_offset_texture
= 0;
1040 uint32_t sampler_offset
;
1041 wm_push_const_offset
= gen6_blorp_emit_wm_constants(brw
, params
);
1042 intel_miptree_used_for_rendering(params
->dst
.mt
);
1043 wm_surf_offset_renderbuffer
=
1044 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->dst
,
1045 I915_GEM_DOMAIN_RENDER
,
1046 I915_GEM_DOMAIN_RENDER
);
1047 if (params
->src
.mt
) {
1048 wm_surf_offset_texture
=
1049 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->src
,
1050 I915_GEM_DOMAIN_SAMPLER
, 0);
1053 gen6_blorp_emit_binding_table(brw
, params
,
1054 wm_surf_offset_renderbuffer
,
1055 wm_surf_offset_texture
);
1056 sampler_offset
= gen6_blorp_emit_sampler_state(brw
, params
);
1057 gen6_blorp_emit_sampler_state_pointers(brw
, params
, sampler_offset
);
1059 gen6_blorp_emit_vs_disable(brw
, params
);
1060 gen6_blorp_emit_gs_disable(brw
, params
);
1061 gen6_blorp_emit_clip_disable(brw
, params
);
1062 gen6_blorp_emit_sf_config(brw
, params
);
1063 if (params
->use_wm_prog
)
1064 gen6_blorp_emit_constant_ps(brw
, params
, wm_push_const_offset
);
1066 gen6_blorp_emit_constant_ps_disable(brw
, params
);
1067 gen6_blorp_emit_wm_config(brw
, params
, prog_offset
, prog_data
);
1068 if (params
->use_wm_prog
)
1069 gen6_blorp_emit_binding_table_pointers(brw
, params
, wm_bind_bo_offset
);
1070 gen6_blorp_emit_viewport_state(brw
, params
);
1072 if (params
->depth
.mt
)
1073 gen6_blorp_emit_depth_stencil_config(brw
, params
);
1075 gen6_blorp_emit_depth_disable(brw
, params
);
1076 gen6_blorp_emit_clear_params(brw
, params
);
1077 gen6_blorp_emit_drawing_rectangle(brw
, params
);
1078 gen6_blorp_emit_primitive(brw
, params
);