2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
28 #include "intel_mipmap_tree.h"
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_state.h"
34 #include "brw_blorp.h"
35 #include "gen6_blorp.h"
38 * \name Constants for BLORP VBO
41 #define GEN6_BLORP_NUM_VERTICES 3
42 #define GEN6_BLORP_NUM_VUE_ELEMS 8
43 #define GEN6_BLORP_VBO_SIZE (GEN6_BLORP_NUM_VERTICES \
44 * GEN6_BLORP_NUM_VUE_ELEMS \
50 * Compute masks to determine how much of draw_x and draw_y should be
51 * performed using the fine adjustment of "depth coordinate offset X/Y"
52 * (dw5 of 3DSTATE_DEPTH_BUFFER). See the emit_depthbuffer() function for
56 gen6_blorp_compute_tile_masks(const brw_blorp_params
*params
,
57 uint32_t *tile_mask_x
, uint32_t *tile_mask_y
)
59 uint32_t depth_mask_x
, depth_mask_y
, hiz_mask_x
, hiz_mask_y
;
60 intel_region_get_tile_masks(params
->depth
.mt
->region
,
61 &depth_mask_x
, &depth_mask_y
);
62 intel_region_get_tile_masks(params
->depth
.mt
->hiz_mt
->region
,
63 &hiz_mask_x
, &hiz_mask_y
);
65 /* Each HiZ row represents 2 rows of pixels */
66 hiz_mask_y
= hiz_mask_y
<< 1 | 1;
68 *tile_mask_x
= depth_mask_x
| hiz_mask_x
;
69 *tile_mask_y
= depth_mask_y
| hiz_mask_y
;
74 gen6_blorp_emit_batch_head(struct brw_context
*brw
,
75 const brw_blorp_params
*params
)
77 struct gl_context
*ctx
= &brw
->intel
.ctx
;
78 struct intel_context
*intel
= &brw
->intel
;
80 /* To ensure that the batch contains only the resolve, flush the batch
81 * before beginning and after finishing emitting the resolve packets.
83 * Ideally, we would not need to flush for the resolve op. But, I suspect
84 * that it's unsafe for CMD_PIPELINE_SELECT to occur multiple times in
85 * a single batch, and there is no safe way to ensure that other than by
86 * fencing the resolve with flushes. Ideally, we would just detect if
87 * a batch is in progress and do the right thing, but that would require
88 * the ability to *safely* access brw_context::state::dirty::brw
89 * outside of the brw_upload_state() codepath.
93 /* CMD_PIPELINE_SELECT
95 * Select the 3D pipeline, as opposed to the media pipeline.
99 OUT_BATCH(brw
->CMD_PIPELINE_SELECT
<< 16);
106 * CMD_STATE_BASE_ADDRESS
108 * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS:
109 * The following commands must be reissued following any change to the
111 * 3DSTATE_CC_POINTERS
112 * 3DSTATE_BINDING_TABLE_POINTERS
113 * 3DSTATE_SAMPLER_STATE_POINTERS
114 * 3DSTATE_VIEWPORT_STATE_POINTERS
115 * MEDIA_STATE_POINTERS
118 gen6_blorp_emit_state_base_address(struct brw_context
*brw
,
119 const brw_blorp_params
*params
)
121 struct intel_context
*intel
= &brw
->intel
;
124 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
125 OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */
126 /* SurfaceStateBaseAddress */
127 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
128 /* DynamicStateBaseAddress */
129 OUT_RELOC(intel
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
130 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
131 OUT_BATCH(1); /* IndirectObjectBaseAddress */
132 if (params
->use_wm_prog
) {
133 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
134 1); /* Instruction base address: shader kernels */
136 OUT_BATCH(1); /* InstructionBaseAddress */
138 OUT_BATCH(1); /* GeneralStateUpperBound */
139 /* Dynamic state upper bound. Although the documentation says that
140 * programming it to zero will cause it to be ignored, that is a lie.
141 * If this isn't programmed to a real bound, the sampler border color
142 * pointer is rejected, causing border color to mysteriously fail.
144 OUT_BATCH(0xfffff001);
145 OUT_BATCH(1); /* IndirectObjectUpperBound*/
146 OUT_BATCH(1); /* InstructionAccessUpperBound */
152 gen6_blorp_emit_vertices(struct brw_context
*brw
,
153 const brw_blorp_params
*params
)
155 struct intel_context
*intel
= &brw
->intel
;
156 uint32_t vertex_offset
;
158 /* Setup VBO for the rectangle primitive..
160 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
161 * vertices. The vertices reside in screen space with DirectX coordinates
162 * (that is, (0, 0) is the upper left corner).
169 * Since the VS is disabled, the clipper loads each VUE directly from
170 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
171 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
172 * dw0: Reserved, MBZ.
173 * dw1: Render Target Array Index. The HiZ op does not use indexed
174 * vertices, so set the dword to 0.
175 * dw2: Viewport Index. The HiZ op disables viewport mapping and
176 * scissoring, so set the dword to 0.
177 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
178 * set the dword to 0.
179 * dw4: Vertex Position X.
180 * dw5: Vertex Position Y.
181 * dw6: Vertex Position Z.
182 * dw7: Vertex Position W.
184 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
185 * "Vertex URB Entry (VUE) Formats".
190 const float vertices
[GEN6_BLORP_VBO_SIZE
] = {
191 /* v0 */ 0, 0, 0, 0, params
->x0
, params
->y1
, 0, 1,
192 /* v1 */ 0, 0, 0, 0, params
->x1
, params
->y1
, 0, 1,
193 /* v2 */ 0, 0, 0, 0, params
->x0
, params
->y0
, 0, 1,
196 vertex_data
= (float *) brw_state_batch(brw
, AUB_TRACE_VERTEX_BUFFER
,
197 GEN6_BLORP_VBO_SIZE
, 32,
199 memcpy(vertex_data
, vertices
, GEN6_BLORP_VBO_SIZE
);
202 /* 3DSTATE_VERTEX_BUFFERS */
204 const int num_buffers
= 1;
205 const int batch_length
= 1 + 4 * num_buffers
;
207 uint32_t dw0
= GEN6_VB0_ACCESS_VERTEXDATA
|
208 (GEN6_BLORP_NUM_VUE_ELEMS
* sizeof(float)) << BRW_VB0_PITCH_SHIFT
;
211 dw0
|= GEN7_VB0_ADDRESS_MODIFYENABLE
;
213 BEGIN_BATCH(batch_length
);
214 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS
<< 16) | (batch_length
- 2));
217 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
220 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
221 vertex_offset
+ GEN6_BLORP_VBO_SIZE
- 1);
226 /* 3DSTATE_VERTEX_ELEMENTS
228 * Fetch dwords 0 - 7 from each VUE. See the comments above where
229 * the vertex_bo is filled with data.
232 const int num_elements
= 2;
233 const int batch_length
= 1 + 2 * num_elements
;
235 BEGIN_BATCH(batch_length
);
236 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (batch_length
- 2));
238 OUT_BATCH(GEN6_VE0_VALID
|
239 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
240 0 << BRW_VE0_SRC_OFFSET_SHIFT
);
241 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
242 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
243 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
244 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
246 OUT_BATCH(GEN6_VE0_VALID
|
247 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
248 16 << BRW_VE0_SRC_OFFSET_SHIFT
);
249 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
250 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
251 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
252 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
260 * Assign the entire URB to the VS. Even though the VS disabled, URB space
261 * is still needed because the clipper loads the VUE's from the URB. From
262 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
263 * Dword 1.15:0 "VS Number of URB Entries":
264 * This field is always used (even if VS Function Enable is DISABLED).
266 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
267 * safely ignore it because this batch contains only one draw call.
268 * Because of URB corruption caused by allocating a previous GS unit
269 * URB entry to the VS unit, software is required to send a “GS NULL
270 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
271 * plus a dummy DRAW call before any case where VS will be taking over
275 gen6_blorp_emit_urb_config(struct brw_context
*brw
,
276 const brw_blorp_params
*params
)
278 struct intel_context
*intel
= &brw
->intel
;
281 OUT_BATCH(_3DSTATE_URB
<< 16 | (3 - 2));
282 OUT_BATCH(brw
->urb
.max_vs_entries
<< GEN6_URB_VS_ENTRIES_SHIFT
);
290 gen6_blorp_emit_blend_state(struct brw_context
*brw
,
291 const brw_blorp_params
*params
)
293 uint32_t cc_blend_state_offset
;
295 struct gen6_blend_state
*blend
= (struct gen6_blend_state
*)
296 brw_state_batch(brw
, AUB_TRACE_BLEND_STATE
,
297 sizeof(struct gen6_blend_state
), 64,
298 &cc_blend_state_offset
);
300 memset(blend
, 0, sizeof(*blend
));
302 blend
->blend1
.pre_blend_clamp_enable
= 1;
303 blend
->blend1
.post_blend_clamp_enable
= 1;
304 blend
->blend1
.clamp_range
= BRW_RENDERTARGET_CLAMPRANGE_FORMAT
;
306 blend
->blend1
.write_disable_r
= false;
307 blend
->blend1
.write_disable_g
= false;
308 blend
->blend1
.write_disable_b
= false;
309 blend
->blend1
.write_disable_a
= false;
311 return cc_blend_state_offset
;
317 gen6_blorp_emit_cc_state(struct brw_context
*brw
,
318 const brw_blorp_params
*params
)
320 uint32_t cc_state_offset
;
322 struct gen6_color_calc_state
*cc
= (struct gen6_color_calc_state
*)
323 brw_state_batch(brw
, AUB_TRACE_CC_STATE
,
324 sizeof(gen6_color_calc_state
), 64,
326 memset(cc
, 0, sizeof(*cc
));
328 return cc_state_offset
;
333 * \param out_offset is relative to
334 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
337 gen6_blorp_emit_depth_stencil_state(struct brw_context
*brw
,
338 const brw_blorp_params
*params
)
340 uint32_t depthstencil_offset
;
342 struct gen6_depth_stencil_state
*state
;
343 state
= (struct gen6_depth_stencil_state
*)
344 brw_state_batch(brw
, AUB_TRACE_DEPTH_STENCIL_STATE
,
346 &depthstencil_offset
);
347 memset(state
, 0, sizeof(*state
));
349 /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
350 * - 7.5.3.1 Depth Buffer Clear
351 * - 7.5.3.2 Depth Buffer Resolve
352 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
354 state
->ds2
.depth_write_enable
= 1;
355 if (params
->hiz_op
== GEN6_HIZ_OP_DEPTH_RESOLVE
) {
356 state
->ds2
.depth_test_enable
= 1;
357 state
->ds2
.depth_test_func
= COMPAREFUNC_NEVER
;
360 return depthstencil_offset
;
364 /* 3DSTATE_CC_STATE_POINTERS
366 * The pointer offsets are relative to
367 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
369 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
372 gen6_blorp_emit_cc_state_pointers(struct brw_context
*brw
,
373 const brw_blorp_params
*params
,
374 uint32_t cc_blend_state_offset
,
375 uint32_t depthstencil_offset
,
376 uint32_t cc_state_offset
)
378 struct intel_context
*intel
= &brw
->intel
;
381 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (4 - 2));
382 OUT_BATCH(cc_blend_state_offset
| 1); /* BLEND_STATE offset */
383 OUT_BATCH(depthstencil_offset
| 1); /* DEPTH_STENCIL_STATE offset */
384 OUT_BATCH(cc_state_offset
| 1); /* COLOR_CALC_STATE offset */
389 /* WM push constants */
391 gen6_blorp_emit_wm_constants(struct brw_context
*brw
,
392 const brw_blorp_params
*params
)
394 uint32_t wm_push_const_offset
;
396 void *constants
= brw_state_batch(brw
, AUB_TRACE_WM_CONSTANTS
,
397 sizeof(params
->wm_push_consts
),
398 32, &wm_push_const_offset
);
399 memcpy(constants
, ¶ms
->wm_push_consts
,
400 sizeof(params
->wm_push_consts
));
402 return wm_push_const_offset
;
406 /* SURFACE_STATE for renderbuffer or texture surface (see
407 * brw_update_renderbuffer_surface and brw_update_texture_surface)
410 gen6_blorp_emit_surface_state(struct brw_context
*brw
,
411 const brw_blorp_params
*params
,
412 const brw_blorp_surface_info
*surface
,
413 uint32_t read_domains
, uint32_t write_domain
)
415 uint32_t wm_surf_offset
;
416 uint32_t width
, height
;
417 surface
->get_miplevel_dims(&width
, &height
);
418 if (surface
->num_samples
> 1) { /* TODO: seems clumsy */
422 if (surface
->map_stencil_as_y_tiled
) {
426 struct intel_region
*region
= surface
->mt
->region
;
428 uint32_t *surf
= (uint32_t *)
429 brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
432 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
433 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
434 BRW_SURFACE_CUBEFACE_ENABLES
|
435 surface
->brw_surfaceformat
<< BRW_SURFACE_FORMAT_SHIFT
);
438 surf
[1] = region
->bo
->offset
; /* No tile offsets needed */
440 surf
[2] = (0 << BRW_SURFACE_LOD_SHIFT
|
441 (width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
442 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
444 uint32_t tiling
= surface
->map_stencil_as_y_tiled
445 ? BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
446 : brw_get_surface_tiling_bits(region
->tiling
);
447 uint32_t pitch_bytes
= region
->pitch
* region
->cpp
;
448 if (surface
->map_stencil_as_y_tiled
)
451 0 << BRW_SURFACE_DEPTH_SHIFT
|
452 (pitch_bytes
- 1) << BRW_SURFACE_PITCH_SHIFT
);
454 surf
[4] = brw_get_surface_num_multisamples(surface
->num_samples
);
456 surf
[5] = (0 << BRW_SURFACE_X_OFFSET_SHIFT
|
457 0 << BRW_SURFACE_Y_OFFSET_SHIFT
|
458 (surface
->mt
->align_h
== 4 ?
459 BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
461 /* Emit relocation to surface contents */
462 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
465 surf
[1] - region
->bo
->offset
,
466 read_domains
, write_domain
);
468 return wm_surf_offset
;
472 /* BINDING_TABLE. See brw_wm_binding_table(). */
474 gen6_blorp_emit_binding_table(struct brw_context
*brw
,
475 const brw_blorp_params
*params
,
476 uint32_t wm_surf_offset_renderbuffer
,
477 uint32_t wm_surf_offset_texture
)
479 uint32_t wm_bind_bo_offset
;
480 uint32_t *bind
= (uint32_t *)
481 brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
483 BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
,
486 bind
[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
] =
487 wm_surf_offset_renderbuffer
;
488 bind
[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
] = wm_surf_offset_texture
;
490 return wm_bind_bo_offset
;
495 * SAMPLER_STATE. See brw_update_sampler_state().
498 gen6_blorp_emit_sampler_state(struct brw_context
*brw
,
499 const brw_blorp_params
*params
)
501 uint32_t sampler_offset
;
503 struct brw_sampler_state
*sampler
= (struct brw_sampler_state
*)
504 brw_state_batch(brw
, AUB_TRACE_SAMPLER_STATE
,
505 sizeof(struct brw_sampler_state
),
506 32, &sampler_offset
);
507 memset(sampler
, 0, sizeof(*sampler
));
509 sampler
->ss0
.min_filter
= BRW_MAPFILTER_LINEAR
;
510 sampler
->ss0
.mip_filter
= BRW_MIPFILTER_NONE
;
511 sampler
->ss0
.mag_filter
= BRW_MAPFILTER_LINEAR
;
513 sampler
->ss1
.r_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
514 sampler
->ss1
.s_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
515 sampler
->ss1
.t_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
517 sampler
->ss0
.min_mag_neq
= 1;
521 sampler
->ss0
.lod_bias
= 0;
523 sampler
->ss0
.lod_preclamp
= 1; /* OpenGL mode */
524 sampler
->ss0
.default_color_mode
= 0; /* OpenGL/DX10 mode */
526 /* Set BaseMipLevel, MaxLOD, MinLOD:
528 * XXX: I don't think that using firstLevel, lastLevel works,
529 * because we always setup the surface state as if firstLevel ==
530 * level zero. Probably have to subtract firstLevel from each of
533 sampler
->ss0
.base_level
= U_FIXED(0, 1);
535 sampler
->ss1
.max_lod
= U_FIXED(0, 6);
536 sampler
->ss1
.min_lod
= U_FIXED(0, 6);
538 sampler
->ss3
.non_normalized_coord
= 1;
540 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN
|
541 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN
|
542 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN
;
543 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG
|
544 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG
|
545 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG
;
547 return sampler_offset
;
552 * 3DSTATE_SAMPLER_STATE_POINTERS. See upload_sampler_state_pointers().
555 gen6_blorp_emit_sampler_state_pointers(struct brw_context
*brw
,
556 const brw_blorp_params
*params
,
557 uint32_t sampler_offset
)
559 struct intel_context
*intel
= &brw
->intel
;
562 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS
<< 16 |
563 VS_SAMPLER_STATE_CHANGE
|
564 GS_SAMPLER_STATE_CHANGE
|
565 PS_SAMPLER_STATE_CHANGE
|
567 OUT_BATCH(0); /* VS */
568 OUT_BATCH(0); /* GS */
569 OUT_BATCH(sampler_offset
);
576 * Disable vertex shader.
579 gen6_blorp_emit_vs_disable(struct brw_context
*brw
,
580 const brw_blorp_params
*params
)
582 struct intel_context
*intel
= &brw
->intel
;
584 if (intel
->gen
== 6) {
585 /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section
586 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
588 * [DevSNB] A pipeline flush must be programmed prior to a
589 * 3DSTATE_VS command that causes the VS Function Enable to
590 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
591 * command with CS stall bit set and a post sync operation.
593 intel_emit_post_sync_nonzero_flush(intel
);
597 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
609 * Disable the geometry shader.
612 gen6_blorp_emit_gs_disable(struct brw_context
*brw
,
613 const brw_blorp_params
*params
)
615 struct intel_context
*intel
= &brw
->intel
;
618 OUT_BATCH(_3DSTATE_GS
<< 16 | (7 - 2));
631 * Disable the clipper.
633 * The BLORP op emits a rectangle primitive, which requires clipping to
634 * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
635 * Section 1.3 "3D Primitives Overview":
637 * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
638 * Mode should be set to a value other than CLIPMODE_NORMAL.
640 * Also disable perspective divide. This doesn't change the clipper's
641 * output, but does spare a few electrons.
644 gen6_blorp_emit_clip_disable(struct brw_context
*brw
,
645 const brw_blorp_params
*params
)
647 struct intel_context
*intel
= &brw
->intel
;
650 OUT_BATCH(_3DSTATE_CLIP
<< 16 | (4 - 2));
652 OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE
);
660 * Disable ViewportTransformEnable (dw2.1)
662 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
663 * Primitives Overview":
664 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
665 * use of screen- space coordinates).
667 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
668 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
670 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
671 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
672 * SOLID: Any triangle or rectangle object found to be front-facing
673 * is rendered as a solid object. This setting is required when
674 * (rendering rectangle (RECTLIST) objects.
677 gen6_blorp_emit_sf_config(struct brw_context
*brw
,
678 const brw_blorp_params
*params
)
680 struct intel_context
*intel
= &brw
->intel
;
683 OUT_BATCH(_3DSTATE_SF
<< 16 | (20 - 2));
684 OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT
| /* only position */
685 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT
|
686 0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT
);
687 OUT_BATCH(0); /* dw2 */
688 OUT_BATCH(params
->num_samples
> 1 ? GEN6_SF_MSRAST_ON_PATTERN
: 0);
689 for (int i
= 0; i
< 16; ++i
)
696 * Enable or disable thread dispatch and set the HiZ op appropriately.
699 gen6_blorp_emit_wm_config(struct brw_context
*brw
,
700 const brw_blorp_params
*params
,
701 uint32_t prog_offset
,
702 brw_blorp_prog_data
*prog_data
)
704 struct intel_context
*intel
= &brw
->intel
;
705 uint32_t dw2
, dw4
, dw5
, dw6
;
707 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
708 * nonzero to prevent the GPU from hanging. See the valid ranges in the
709 * BSpec, Volume 2a.11 Windower, Section 3DSTATE_WM, Dword 5.25:31
710 * "Maximum Number Of Threads".
712 * To be safe (and to minimize extraneous code) we go ahead and fully
713 * configure the WM state whether or not there is a WM program.
716 dw2
= dw4
= dw5
= dw6
= 0;
717 switch (params
->hiz_op
) {
718 case GEN6_HIZ_OP_DEPTH_CLEAR
:
719 dw4
|= GEN6_WM_DEPTH_CLEAR
;
721 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
722 dw4
|= GEN6_WM_DEPTH_RESOLVE
;
724 case GEN6_HIZ_OP_HIZ_RESOLVE
:
725 dw4
|= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE
;
727 case GEN6_HIZ_OP_NONE
:
733 dw4
|= GEN6_WM_STATISTICS_ENABLE
;
734 dw5
|= GEN6_WM_LINE_AA_WIDTH_1_0
;
735 dw5
|= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5
;
736 dw5
|= (brw
->max_wm_threads
- 1) << GEN6_WM_MAX_THREADS_SHIFT
;
737 dw6
|= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
; /* No interp */
738 dw6
|= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT
; /* No inputs from SF */
739 if (params
->use_wm_prog
) {
740 dw2
|= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT
; /* Up to 4 samplers */
741 dw4
|= prog_data
->first_curbe_grf
<< GEN6_WM_DISPATCH_START_GRF_SHIFT_0
;
742 dw5
|= GEN6_WM_16_DISPATCH_ENABLE
;
743 dw5
|= GEN6_WM_KILL_ENABLE
; /* TODO: temporarily smash on */
744 dw5
|= GEN6_WM_DISPATCH_ENABLE
; /* We are rendering */
747 if (params
->num_samples
> 1) {
748 dw6
|= GEN6_WM_MSRAST_ON_PATTERN
;
749 if (prog_data
&& prog_data
->persample_msaa_dispatch
)
750 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
752 dw6
|= GEN6_WM_MSDISPMODE_PERPIXEL
;
754 dw6
|= GEN6_WM_MSRAST_OFF_PIXEL
;
755 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
759 OUT_BATCH(_3DSTATE_WM
<< 16 | (9 - 2));
760 OUT_BATCH(params
->use_wm_prog
? prog_offset
: 0);
762 OUT_BATCH(0); /* No scratch needed */
766 OUT_BATCH(0); /* No other programs */
767 OUT_BATCH(0); /* No other programs */
773 gen6_blorp_emit_constant_ps(struct brw_context
*brw
,
774 const brw_blorp_params
*params
,
775 uint32_t wm_push_const_offset
)
777 struct intel_context
*intel
= &brw
->intel
;
779 /* Make sure the push constants fill an exact integer number of
782 assert(sizeof(brw_blorp_wm_push_constants
) % 32 == 0);
784 /* There must be at least one register worth of push constant data. */
785 assert(BRW_BLORP_NUM_PUSH_CONST_REGS
> 0);
787 /* Enable push constant buffer 0. */
789 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 |
790 GEN6_CONSTANT_BUFFER_0_ENABLE
|
792 OUT_BATCH(wm_push_const_offset
+ (BRW_BLORP_NUM_PUSH_CONST_REGS
- 1));
801 * 3DSTATE_BINDING_TABLE_POINTERS
804 gen6_blorp_emit_binding_table_pointers(struct brw_context
*brw
,
805 const brw_blorp_params
*params
,
806 uint32_t wm_bind_bo_offset
)
808 struct intel_context
*intel
= &brw
->intel
;
811 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
812 GEN6_BINDING_TABLE_MODIFY_PS
|
814 OUT_BATCH(0); /* vs -- ignored */
815 OUT_BATCH(0); /* gs -- ignored */
816 OUT_BATCH(wm_bind_bo_offset
); /* wm/ps */
822 gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw
,
823 const brw_blorp_params
*params
)
825 struct intel_context
*intel
= &brw
->intel
;
826 uint32_t draw_x
, draw_y
;
827 uint32_t tile_mask_x
, tile_mask_y
;
829 gen6_blorp_compute_tile_masks(params
, &tile_mask_x
, &tile_mask_y
);
830 params
->depth
.get_draw_offsets(&draw_x
, &draw_y
);
832 /* 3DSTATE_DEPTH_BUFFER */
834 uint32_t width
, height
;
835 params
->depth
.get_miplevel_dims(&width
, &height
);
837 uint32_t tile_x
= draw_x
& tile_mask_x
;
838 uint32_t tile_y
= draw_y
& tile_mask_y
;
840 intel_region_get_aligned_offset(params
->depth
.mt
->region
,
841 draw_x
& ~tile_mask_x
,
842 draw_y
& ~tile_mask_y
);
844 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
845 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
846 * Coordinate Offset X/Y":
848 * "The 3 LSBs of both offsets must be zero to ensure correct
851 * We have no guarantee that tile_x and tile_y are correctly aligned,
852 * since they are determined by the mipmap layout, which is only aligned
855 * So, to avoid hanging the GPU, just smash the low order 3 bits of
856 * tile_x and tile_y to 0. This is a temporary workaround until we come
857 * up with a better solution.
862 intel_emit_post_sync_nonzero_flush(intel
);
863 intel_emit_depth_stall_flushes(intel
);
866 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
867 uint32_t pitch_bytes
=
868 params
->depth
.mt
->region
->pitch
* params
->depth
.mt
->region
->cpp
;
869 OUT_BATCH((pitch_bytes
- 1) |
870 params
->depth_format
<< 18 |
871 1 << 21 | /* separate stencil enable */
872 1 << 22 | /* hiz enable */
873 BRW_TILEWALK_YMAJOR
<< 26 |
874 1 << 27 | /* y-tiled */
875 BRW_SURFACE_2D
<< 29);
876 OUT_RELOC(params
->depth
.mt
->region
->bo
,
877 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
879 OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1 |
880 (width
+ tile_x
- 1) << 6 |
881 (height
+ tile_y
- 1) << 19);
889 /* 3DSTATE_HIER_DEPTH_BUFFER */
891 struct intel_region
*hiz_region
= params
->depth
.mt
->hiz_mt
->region
;
892 uint32_t hiz_offset
=
893 intel_region_get_aligned_offset(hiz_region
,
894 draw_x
& ~tile_mask_x
,
895 (draw_y
& ~tile_mask_y
) / 2);
898 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
899 OUT_BATCH(hiz_region
->pitch
* hiz_region
->cpp
- 1);
900 OUT_RELOC(hiz_region
->bo
,
901 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
906 /* 3DSTATE_STENCIL_BUFFER */
909 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
918 gen6_blorp_emit_depth_disable(struct brw_context
*brw
,
919 const brw_blorp_params
*params
)
921 struct intel_context
*intel
= &brw
->intel
;
924 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
925 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
926 (BRW_SURFACE_NULL
<< 29));
936 /* 3DSTATE_CLEAR_PARAMS
938 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
939 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
940 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
943 gen6_blorp_emit_clear_params(struct brw_context
*brw
,
944 const brw_blorp_params
*params
)
946 struct intel_context
*intel
= &brw
->intel
;
949 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
950 GEN5_DEPTH_CLEAR_VALID
|
952 OUT_BATCH(params
->depth
.mt
? params
->depth
.mt
->depth_clear_value
: 0);
957 /* 3DSTATE_DRAWING_RECTANGLE */
959 gen6_blorp_emit_drawing_rectangle(struct brw_context
*brw
,
960 const brw_blorp_params
*params
)
962 struct intel_context
*intel
= &brw
->intel
;
965 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
967 OUT_BATCH(((params
->x1
- 1) & 0xffff) |
968 ((params
->y1
- 1) << 16));
973 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
975 gen6_blorp_emit_viewport_state(struct brw_context
*brw
,
976 const brw_blorp_params
*params
)
978 struct intel_context
*intel
= &brw
->intel
;
979 struct brw_cc_viewport
*ccv
;
980 uint32_t cc_vp_offset
;
982 ccv
= (struct brw_cc_viewport
*)brw_state_batch(brw
, AUB_TRACE_CC_VP_STATE
,
986 ccv
->min_depth
= 0.0;
987 ccv
->max_depth
= 1.0;
990 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS
<< 16 | (4 - 2) |
991 GEN6_CC_VIEWPORT_MODIFY
);
992 OUT_BATCH(0); /* clip VP */
993 OUT_BATCH(0); /* SF VP */
994 OUT_BATCH(cc_vp_offset
);
1001 gen6_blorp_emit_primitive(struct brw_context
*brw
,
1002 const brw_blorp_params
*params
)
1004 struct intel_context
*intel
= &brw
->intel
;
1007 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
1008 _3DPRIM_RECTLIST
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
1009 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
);
1010 OUT_BATCH(3); /* vertex count per instance */
1012 OUT_BATCH(1); /* instance count */
1020 * \brief Execute a blit or render pass operation.
1022 * To execute the operation, this function manually constructs and emits a
1023 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1024 * constructing and after emitting the batch.
1026 * This function alters no GL state.
1029 gen6_blorp_exec(struct intel_context
*intel
,
1030 const brw_blorp_params
*params
)
1032 struct gl_context
*ctx
= &intel
->ctx
;
1033 struct brw_context
*brw
= brw_context(ctx
);
1034 brw_blorp_prog_data
*prog_data
= NULL
;
1035 uint32_t cc_blend_state_offset
= 0;
1036 uint32_t cc_state_offset
= 0;
1037 uint32_t depthstencil_offset
;
1038 uint32_t wm_push_const_offset
= 0;
1039 uint32_t wm_bind_bo_offset
= 0;
1041 uint32_t prog_offset
= params
->get_wm_prog(brw
, &prog_data
);
1042 gen6_blorp_emit_batch_head(brw
, params
);
1043 gen6_emit_3dstate_multisample(brw
, params
->num_samples
);
1044 gen6_emit_3dstate_sample_mask(brw
, params
->num_samples
, 1.0, false);
1045 gen6_blorp_emit_state_base_address(brw
, params
);
1046 gen6_blorp_emit_vertices(brw
, params
);
1047 gen6_blorp_emit_urb_config(brw
, params
);
1048 if (params
->use_wm_prog
) {
1049 cc_blend_state_offset
= gen6_blorp_emit_blend_state(brw
, params
);
1050 cc_state_offset
= gen6_blorp_emit_cc_state(brw
, params
);
1052 depthstencil_offset
= gen6_blorp_emit_depth_stencil_state(brw
, params
);
1053 gen6_blorp_emit_cc_state_pointers(brw
, params
, cc_blend_state_offset
,
1054 depthstencil_offset
, cc_state_offset
);
1055 if (params
->use_wm_prog
) {
1056 uint32_t wm_surf_offset_renderbuffer
;
1057 uint32_t wm_surf_offset_texture
;
1058 uint32_t sampler_offset
;
1059 wm_push_const_offset
= gen6_blorp_emit_wm_constants(brw
, params
);
1060 wm_surf_offset_renderbuffer
=
1061 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->dst
,
1062 I915_GEM_DOMAIN_RENDER
,
1063 I915_GEM_DOMAIN_RENDER
);
1064 wm_surf_offset_texture
=
1065 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->src
,
1066 I915_GEM_DOMAIN_SAMPLER
, 0);
1068 gen6_blorp_emit_binding_table(brw
, params
,
1069 wm_surf_offset_renderbuffer
,
1070 wm_surf_offset_texture
);
1071 sampler_offset
= gen6_blorp_emit_sampler_state(brw
, params
);
1072 gen6_blorp_emit_sampler_state_pointers(brw
, params
, sampler_offset
);
1074 gen6_blorp_emit_vs_disable(brw
, params
);
1075 gen6_blorp_emit_gs_disable(brw
, params
);
1076 gen6_blorp_emit_clip_disable(brw
, params
);
1077 gen6_blorp_emit_sf_config(brw
, params
);
1078 if (params
->use_wm_prog
)
1079 gen6_blorp_emit_constant_ps(brw
, params
, wm_push_const_offset
);
1080 gen6_blorp_emit_wm_config(brw
, params
, prog_offset
, prog_data
);
1081 if (params
->use_wm_prog
)
1082 gen6_blorp_emit_binding_table_pointers(brw
, params
, wm_bind_bo_offset
);
1083 gen6_blorp_emit_viewport_state(brw
, params
);
1085 if (params
->depth
.mt
)
1086 gen6_blorp_emit_depth_stencil_config(brw
, params
);
1088 gen6_blorp_emit_depth_disable(brw
, params
);
1089 gen6_blorp_emit_clear_params(brw
, params
);
1090 gen6_blorp_emit_drawing_rectangle(brw
, params
);
1091 gen6_blorp_emit_primitive(brw
, params
);
1093 /* See comments above at first invocation of intel_flush() in
1094 * gen6_blorp_emit_batch_head().
1099 brw
->state
.dirty
.brw
= ~0;
1100 brw
->state
.dirty
.cache
= ~0;