src/mesa/drivers/dri/i965/gen6_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_mipmap_tree.h"
  28
  29 #include "brw_context.h"
  30 #include "brw_state.h"
  31
  32 #include "brw_blorp.h"
  33
  34 /**
  35  * CMD_STATE_BASE_ADDRESS
  36  *
  37  * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS:
  38  *     The following commands must be reissued following any change to the
  39  *     base addresses:
  40  *         3DSTATE_CC_POINTERS
  41  *         3DSTATE_BINDING_TABLE_POINTERS
  42  *         3DSTATE_SAMPLER_STATE_POINTERS
  43  *         3DSTATE_VIEWPORT_STATE_POINTERS
  44  *         MEDIA_STATE_POINTERS
  45  */
  46 void
  47 gen6_blorp_emit_state_base_address(struct brw_context *brw,
  48                                    const brw_blorp_params *params)
  49 {
  50    uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
  51
  52    BEGIN_BATCH(10);
  53    OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
  54    OUT_BATCH(mocs << 8 | /* GeneralStateMemoryObjectControlState */
  55              mocs << 4 | /* StatelessDataPortAccessMemoryObjectControlState */
  56              1); /* GeneralStateBaseAddressModifyEnable */
  57
  58    /* SurfaceStateBaseAddress */
  59    OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
  60    /* DynamicStateBaseAddress */
  61    OUT_RELOC(brw->batch.bo, (I915_GEM_DOMAIN_RENDER |
  62                                I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
  63    OUT_BATCH(1); /* IndirectObjectBaseAddress */
  64    if (params->use_wm_prog) {
  65       OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
  66                 1); /* Instruction base address: shader kernels */
  67    } else {
  68       OUT_BATCH(1); /* InstructionBaseAddress */
  69    }
  70    OUT_BATCH(1); /* GeneralStateUpperBound */
  71    /* Dynamic state upper bound.  Although the documentation says that
  72     * programming it to zero will cause it to be ignored, that is a lie.
  73     * If this isn't programmed to a real bound, the sampler border color
  74     * pointer is rejected, causing border color to mysteriously fail.
  75     */
  76    OUT_BATCH(0xfffff001);
  77    OUT_BATCH(1); /* IndirectObjectUpperBound*/
  78    OUT_BATCH(1); /* InstructionAccessUpperBound */
  79    ADVANCE_BATCH();
  80 }
  81
  82 static void
  83 gen6_blorp_emit_vertex_buffer_state(struct brw_context *brw,
  84                                     unsigned num_elems,
  85                                     unsigned vbo_size,
  86                                     uint32_t vertex_offset)
  87 {
  88    /* 3DSTATE_VERTEX_BUFFERS */
  89    const int num_buffers = 1;
  90    const int batch_length = 1 + 4 * num_buffers;
  91
  92    uint32_t dw0 = GEN6_VB0_ACCESS_VERTEXDATA |
  93                   (num_elems * sizeof(float)) << BRW_VB0_PITCH_SHIFT;
  94
  95    if (brw->gen >= 7)
  96       dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
  97
  98    switch (brw->gen) {
  99    case 7:
 100       dw0 |= GEN7_MOCS_L3 << 16;
 101       break;
 102    case 8:
 103       dw0 |= BDW_MOCS_WB << 16;
 104       break;
 105    case 9:
 106       dw0 |= SKL_MOCS_WB << 16;
 107       break;
 108    }
 109
 110    BEGIN_BATCH(batch_length);
 111    OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
 112    OUT_BATCH(dw0);
 113    if (brw->gen >= 8) {
 114       OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0, vertex_offset);
 115       OUT_BATCH(vbo_size);
 116    } else {
 117       /* start address */
 118       OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
 119                 vertex_offset);
 120       /* end address */
 121       OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
 122                 vertex_offset + vbo_size - 1);
 123       OUT_BATCH(0);
 124    }
 125    ADVANCE_BATCH();
 126 }
 127
 128 void
 129 gen6_blorp_emit_vertices(struct brw_context *brw,
 130                          const brw_blorp_params *params)
 131 {
 132    uint32_t vertex_offset;
 133
 134    /* Setup VBO for the rectangle primitive..
 135     *
 136     * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
 137     * vertices. The vertices reside in screen space with DirectX coordinates
 138     * (that is, (0, 0) is the upper left corner).
 139     *
 140     *   v2 ------ implied
 141     *    |        |
 142     *    |        |
 143     *   v0 ----- v1
 144     *
 145     * Since the VS is disabled, the clipper loads each VUE directly from
 146     * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
 147     * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
 148     *   dw0: Reserved, MBZ.
 149     *   dw1: Render Target Array Index. The HiZ op does not use indexed
 150     *        vertices, so set the dword to 0.
 151     *   dw2: Viewport Index. The HiZ op disables viewport mapping and
 152     *        scissoring, so set the dword to 0.
 153     *   dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
 154     *        set the dword to 0.
 155     *   dw4: Vertex Position X.
 156     *   dw5: Vertex Position Y.
 157     *   dw6: Vertex Position Z.
 158     *   dw7: Vertex Position W.
 159     *
 160     * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
 161     * "Vertex URB Entry (VUE) Formats".
 162     */
 163    {
 164       float *vertex_data;
 165
 166       const float vertices[] = {
 167          /* v0 */ 0, 0, 0, 0, (float)params->x0, (float)params->y1, 0, 1,
 168          /* v1 */ 0, 0, 0, 0, (float)params->x1, (float)params->y1, 0, 1,
 169          /* v2 */ 0, 0, 0, 0, (float)params->x0, (float)params->y0, 0, 1,
 170       };
 171
 172       vertex_data = (float *) brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER,
 173                                               sizeof(vertices), 32,
 174                                               &vertex_offset);
 175       memcpy(vertex_data, vertices, sizeof(vertices));
 176
 177       const unsigned blorp_num_vue_elems = 8;
 178       gen6_blorp_emit_vertex_buffer_state(brw, blorp_num_vue_elems,
 179                                           sizeof(vertices), vertex_offset);
 180    }
 181
 182    /* 3DSTATE_VERTEX_ELEMENTS
 183     *
 184     * Fetch dwords 0 - 7 from each VUE. See the comments above where
 185     * the vertex_bo is filled with data.
 186     */
 187    {
 188       const int num_elements = 2;
 189       const int batch_length = 1 + 2 * num_elements;
 190
 191       BEGIN_BATCH(batch_length);
 192       OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (batch_length - 2));
 193       /* Element 0 */
 194       OUT_BATCH(GEN6_VE0_VALID |
 195                 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT |
 196                 0 << BRW_VE0_SRC_OFFSET_SHIFT);
 197       OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT |
 198                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_1_SHIFT |
 199                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_2_SHIFT |
 200                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_3_SHIFT);
 201       /* Element 1 */
 202       OUT_BATCH(GEN6_VE0_VALID |
 203                 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT |
 204                 16 << BRW_VE0_SRC_OFFSET_SHIFT);
 205       OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT |
 206                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_1_SHIFT |
 207                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_2_SHIFT |
 208                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_3_SHIFT);
 209       ADVANCE_BATCH();
 210    }
 211 }
 212
 213
 214 /* 3DSTATE_URB
 215  *
 216  * Assign the entire URB to the VS. Even though the VS disabled, URB space
 217  * is still needed because the clipper loads the VUE's from the URB. From
 218  * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
 219  * Dword 1.15:0 "VS Number of URB Entries":
 220  *     This field is always used (even if VS Function Enable is DISABLED).
 221  *
 222  * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
 223  * safely ignore it because this batch contains only one draw call.
 224  *     Because of URB corruption caused by allocating a previous GS unit
 225  *     URB entry to the VS unit, software is required to send a “GS NULL
 226  *     Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
 227  *     plus a dummy DRAW call before any case where VS will be taking over
 228  *     GS URB space.
 229  */
 230 static void
 231 gen6_blorp_emit_urb_config(struct brw_context *brw,
 232                            const brw_blorp_params *params)
 233 {
 234    BEGIN_BATCH(3);
 235    OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2));
 236    OUT_BATCH(brw->urb.max_vs_entries << GEN6_URB_VS_ENTRIES_SHIFT);
 237    OUT_BATCH(0);
 238    ADVANCE_BATCH();
 239 }
 240
 241
 242 /* BLEND_STATE */
 243 uint32_t
 244 gen6_blorp_emit_blend_state(struct brw_context *brw,
 245                             const brw_blorp_params *params)
 246 {
 247    uint32_t cc_blend_state_offset;
 248
 249    assume(params->num_draw_buffers);
 250
 251    const unsigned size = params->num_draw_buffers *
 252                          sizeof(struct gen6_blend_state);
 253    struct gen6_blend_state *blend = (struct gen6_blend_state *)
 254       brw_state_batch(brw, AUB_TRACE_BLEND_STATE, size, 64,
 255                       &cc_blend_state_offset);
 256
 257    memset(blend, 0, size);
 258
 259    for (unsigned i = 0; i < params->num_draw_buffers; ++i) {
 260       blend[i].blend1.pre_blend_clamp_enable = 1;
 261       blend[i].blend1.post_blend_clamp_enable = 1;
 262       blend[i].blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
 263
 264       blend[i].blend1.write_disable_r = params->color_write_disable[0];
 265       blend[i].blend1.write_disable_g = params->color_write_disable[1];
 266       blend[i].blend1.write_disable_b = params->color_write_disable[2];
 267       blend[i].blend1.write_disable_a = params->color_write_disable[3];
 268    }
 269
 270    return cc_blend_state_offset;
 271 }
 272
 273
 274 /* CC_STATE */
 275 uint32_t
 276 gen6_blorp_emit_cc_state(struct brw_context *brw)
 277 {
 278    uint32_t cc_state_offset;
 279
 280    struct gen6_color_calc_state *cc = (struct gen6_color_calc_state *)
 281       brw_state_batch(brw, AUB_TRACE_CC_STATE,
 282                       sizeof(gen6_color_calc_state), 64,
 283                       &cc_state_offset);
 284    memset(cc, 0, sizeof(*cc));
 285
 286    return cc_state_offset;
 287 }
 288
 289
 290 /**
 291  * \param out_offset is relative to
 292  *        CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 293  */
 294 uint32_t
 295 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 296                                     const brw_blorp_params *params)
 297 {
 298    uint32_t depthstencil_offset;
 299
 300    struct gen6_depth_stencil_state *state;
 301    state = (struct gen6_depth_stencil_state *)
 302       brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
 303                       sizeof(*state), 64,
 304                       &depthstencil_offset);
 305    memset(state, 0, sizeof(*state));
 306
 307    /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
 308     *   - 7.5.3.1 Depth Buffer Clear
 309     *   - 7.5.3.2 Depth Buffer Resolve
 310     *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 311     */
 312    state->ds2.depth_write_enable = 1;
 313    if (params->hiz_op == GEN6_HIZ_OP_DEPTH_RESOLVE) {
 314       state->ds2.depth_test_enable = 1;
 315       state->ds2.depth_test_func = BRW_COMPAREFUNCTION_NEVER;
 316    }
 317
 318    return depthstencil_offset;
 319 }
 320
 321
 322 /* 3DSTATE_CC_STATE_POINTERS
 323  *
 324  * The pointer offsets are relative to
 325  * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 326  *
 327  * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
 328  */
 329 static void
 330 gen6_blorp_emit_cc_state_pointers(struct brw_context *brw,
 331                                   const brw_blorp_params *params,
 332                                   uint32_t cc_blend_state_offset,
 333                                   uint32_t depthstencil_offset,
 334                                   uint32_t cc_state_offset)
 335 {
 336    BEGIN_BATCH(4);
 337    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
 338    OUT_BATCH(cc_blend_state_offset | 1); /* BLEND_STATE offset */
 339    OUT_BATCH(depthstencil_offset | 1); /* DEPTH_STENCIL_STATE offset */
 340    OUT_BATCH(cc_state_offset | 1); /* COLOR_CALC_STATE offset */
 341    ADVANCE_BATCH();
 342 }
 343
 344
 345 /* WM push constants */
 346 uint32_t
 347 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 348                              const brw_blorp_params *params)
 349 {
 350    uint32_t wm_push_const_offset;
 351
 352    void *constants = brw_state_batch(brw, AUB_TRACE_WM_CONSTANTS,
 353                                      sizeof(params->wm_push_consts),
 354                                      32, &wm_push_const_offset);
 355    memcpy(constants, &params->wm_push_consts,
 356           sizeof(params->wm_push_consts));
 357
 358    return wm_push_const_offset;
 359 }
 360
 361
 362 /* SURFACE_STATE for renderbuffer or texture surface (see
 363  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 364  */
 365 static uint32_t
 366 gen6_blorp_emit_surface_state(struct brw_context *brw,
 367                               const brw_blorp_params *params,
 368                               const brw_blorp_surface_info *surface,
 369                               uint32_t read_domains, uint32_t write_domain)
 370 {
 371    uint32_t wm_surf_offset;
 372    uint32_t width = surface->width;
 373    uint32_t height = surface->height;
 374    if (surface->num_samples > 1) {
 375       /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
 376        * in samples.  But SURFACE_STATE wants them in pixels, so we need to
 377        * divide them each by 2.
 378        */
 379       width /= 2;
 380       height /= 2;
 381    }
 382    struct intel_mipmap_tree *mt = surface->mt;
 383    uint32_t tile_x, tile_y;
 384
 385    uint32_t *surf = (uint32_t *)
 386       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 387                       &wm_surf_offset);
 388
 389    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 390               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 391               BRW_SURFACE_CUBEFACE_ENABLES |
 392               surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT);
 393
 394    /* reloc */
 395    surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) +
 396               mt->bo->offset64);
 397
 398    surf[2] = (0 << BRW_SURFACE_LOD_SHIFT |
 399               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 400               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 401
 402    uint32_t tiling = surface->map_stencil_as_y_tiled
 403       ? BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y
 404       : brw_get_surface_tiling_bits(mt->tiling);
 405    uint32_t pitch_bytes = mt->pitch;
 406    if (surface->map_stencil_as_y_tiled)
 407       pitch_bytes *= 2;
 408    surf[3] = (tiling |
 409               0 << BRW_SURFACE_DEPTH_SHIFT |
 410               (pitch_bytes - 1) << BRW_SURFACE_PITCH_SHIFT);
 411
 412    surf[4] = brw_get_surface_num_multisamples(surface->num_samples);
 413
 414    /* Note that the low bits of these fields are missing, so
 415     * there's the possibility of getting in trouble.
 416     */
 417    assert(tile_x % 4 == 0);
 418    assert(tile_y % 2 == 0);
 419    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 420               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
 421               (surface->mt->valign == 4 ?
 422                BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
 423
 424    /* Emit relocation to surface contents */
 425    drm_intel_bo_emit_reloc(brw->batch.bo,
 426                            wm_surf_offset + 4,
 427                            mt->bo,
 428                            surf[1] - mt->bo->offset64,
 429                            read_domains, write_domain);
 430
 431    return wm_surf_offset;
 432 }
 433
 434
 435 /* BINDING_TABLE.  See brw_wm_binding_table(). */
 436 uint32_t
 437 gen6_blorp_emit_binding_table(struct brw_context *brw,
 438                               uint32_t wm_surf_offset_renderbuffer,
 439                               uint32_t wm_surf_offset_texture)
 440 {
 441    uint32_t wm_bind_bo_offset;
 442    uint32_t *bind = (uint32_t *)
 443       brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
 444                       sizeof(uint32_t) *
 445                       BRW_BLORP_NUM_BINDING_TABLE_ENTRIES,
 446                       32, /* alignment */
 447                       &wm_bind_bo_offset);
 448    bind[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX] =
 449       wm_surf_offset_renderbuffer;
 450    bind[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX] = wm_surf_offset_texture;
 451
 452    return wm_bind_bo_offset;
 453 }
 454
 455
 456 /**
 457  * SAMPLER_STATE.  See brw_update_sampler_state().
 458  */
 459 uint32_t
 460 gen6_blorp_emit_sampler_state(struct brw_context *brw,
 461                               unsigned tex_filter, unsigned max_lod,
 462                               bool non_normalized_coords)
 463 {
 464    uint32_t sampler_offset;
 465    uint32_t *sampler_state = (uint32_t *)
 466       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE, 16, 32, &sampler_offset);
 467
 468    unsigned address_rounding = BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 469                                BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 470                                BRW_ADDRESS_ROUNDING_ENABLE_R_MIN |
 471                                BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 472                                BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 473                                BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 474
 475    /* XXX: I don't think that using firstLevel, lastLevel works,
 476     * because we always setup the surface state as if firstLevel ==
 477     * level zero.  Probably have to subtract firstLevel from each of
 478     * these:
 479     */
 480    brw_emit_sampler_state(brw,
 481                           sampler_state,
 482                           sampler_offset,
 483                           tex_filter, /* min filter */
 484                           tex_filter, /* mag filter */
 485                           BRW_MIPFILTER_NONE,
 486                           BRW_ANISORATIO_2,
 487                           address_rounding,
 488                           BRW_TEXCOORDMODE_CLAMP,
 489                           BRW_TEXCOORDMODE_CLAMP,
 490                           BRW_TEXCOORDMODE_CLAMP,
 491                           0, /* min LOD */
 492                           max_lod,
 493                           0, /* LOD bias */
 494                           0, /* shadow function */
 495                           non_normalized_coords,
 496                           0); /* border color offset - unused */
 497
 498    return sampler_offset;
 499 }
 500
 501
 502 /**
 503  * 3DSTATE_SAMPLER_STATE_POINTERS.  See upload_sampler_state_pointers().
 504  */
 505 static void
 506 gen6_blorp_emit_sampler_state_pointers(struct brw_context *brw,
 507                                        uint32_t sampler_offset)
 508 {
 509    BEGIN_BATCH(4);
 510    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS << 16 |
 511              VS_SAMPLER_STATE_CHANGE |
 512              GS_SAMPLER_STATE_CHANGE |
 513              PS_SAMPLER_STATE_CHANGE |
 514              (4 - 2));
 515    OUT_BATCH(0); /* VS */
 516    OUT_BATCH(0); /* GS */
 517    OUT_BATCH(sampler_offset);
 518    ADVANCE_BATCH();
 519 }
 520
 521
 522 /* 3DSTATE_VS
 523  *
 524  * Disable vertex shader.
 525  */
 526 void
 527 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 528                            const brw_blorp_params *params)
 529 {
 530    /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
 531     * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
 532     *
 533     *   [DevSNB] A pipeline flush must be programmed prior to a
 534     *   3DSTATE_VS command that causes the VS Function Enable to
 535     *   toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
 536     *   command with CS stall bit set and a post sync operation.
 537     *
 538     * We've already done one at the start of the BLORP operation.
 539     */
 540
 541    /* Disable the push constant buffers. */
 542    BEGIN_BATCH(5);
 543    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
 544    OUT_BATCH(0);
 545    OUT_BATCH(0);
 546    OUT_BATCH(0);
 547    OUT_BATCH(0);
 548    ADVANCE_BATCH();
 549
 550    BEGIN_BATCH(6);
 551    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 552    OUT_BATCH(0);
 553    OUT_BATCH(0);
 554    OUT_BATCH(0);
 555    OUT_BATCH(0);
 556    OUT_BATCH(0);
 557    ADVANCE_BATCH();
 558 }
 559
 560
 561 /* 3DSTATE_GS
 562  *
 563  * Disable the geometry shader.
 564  */
 565 void
 566 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 567                            const brw_blorp_params *params)
 568 {
 569    /* Disable all the constant buffers. */
 570    BEGIN_BATCH(5);
 571    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (5 - 2));
 572    OUT_BATCH(0);
 573    OUT_BATCH(0);
 574    OUT_BATCH(0);
 575    OUT_BATCH(0);
 576    ADVANCE_BATCH();
 577
 578    BEGIN_BATCH(7);
 579    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 580    OUT_BATCH(0);
 581    OUT_BATCH(0);
 582    OUT_BATCH(0);
 583    OUT_BATCH(0);
 584    OUT_BATCH(0);
 585    OUT_BATCH(0);
 586    ADVANCE_BATCH();
 587    brw->gs.enabled = false;
 588 }
 589
 590
 591 /* 3DSTATE_CLIP
 592  *
 593  * Disable the clipper.
 594  *
 595  * The BLORP op emits a rectangle primitive, which requires clipping to
 596  * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
 597  * Section 1.3 "3D Primitives Overview":
 598  *    RECTLIST:
 599  *    Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
 600  *    Mode should be set to a value other than CLIPMODE_NORMAL.
 601  *
 602  * Also disable perspective divide. This doesn't change the clipper's
 603  * output, but does spare a few electrons.
 604  */
 605 void
 606 gen6_blorp_emit_clip_disable(struct brw_context *brw)
 607 {
 608    BEGIN_BATCH(4);
 609    OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2));
 610    OUT_BATCH(0);
 611    OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE);
 612    OUT_BATCH(0);
 613    ADVANCE_BATCH();
 614 }
 615
 616
 617 /* 3DSTATE_SF
 618  *
 619  * Disable ViewportTransformEnable (dw2.1)
 620  *
 621  * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 622  * Primitives Overview":
 623  *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 624  *     use of screen- space coordinates).
 625  *
 626  * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
 627  * and BackFaceFillMode (dw2.5:6) to SOLID(0).
 628  *
 629  * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 630  * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 631  *     SOLID: Any triangle or rectangle object found to be front-facing
 632  *     is rendered as a solid object. This setting is required when
 633  *     (rendering rectangle (RECTLIST) objects.
 634  */
 635 static void
 636 gen6_blorp_emit_sf_config(struct brw_context *brw,
 637                           const brw_blorp_params *params)
 638 {
 639    BEGIN_BATCH(20);
 640    OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2));
 641    OUT_BATCH(params->num_varyings << GEN6_SF_NUM_OUTPUTS_SHIFT |
 642              1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
 643              BRW_SF_URB_ENTRY_READ_OFFSET <<
 644                 GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT);
 645    OUT_BATCH(0); /* dw2 */
 646    OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 647    for (int i = 0; i < 16; ++i)
 648       OUT_BATCH(0);
 649    ADVANCE_BATCH();
 650 }
 651
 652
 653 /**
 654  * Enable or disable thread dispatch and set the HiZ op appropriately.
 655  */
 656 static void
 657 gen6_blorp_emit_wm_config(struct brw_context *brw,
 658                           const brw_blorp_params *params,
 659                           uint32_t prog_offset,
 660                           brw_blorp_prog_data *prog_data)
 661 {
 662    uint32_t dw2, dw4, dw5, dw6;
 663
 664    /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
 665     * nonzero to prevent the GPU from hanging.  While the documentation doesn't
 666     * mention this explicitly, it notes that the valid range for the field is
 667     * [1,39] = [2,40] threads, which excludes zero.
 668     *
 669     * To be safe (and to minimize extraneous code) we go ahead and fully
 670     * configure the WM state whether or not there is a WM program.
 671     */
 672
 673    dw2 = dw4 = dw5 = dw6 = 0;
 674    switch (params->hiz_op) {
 675    case GEN6_HIZ_OP_DEPTH_CLEAR:
 676       dw4 |= GEN6_WM_DEPTH_CLEAR;
 677       break;
 678    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 679       dw4 |= GEN6_WM_DEPTH_RESOLVE;
 680       break;
 681    case GEN6_HIZ_OP_HIZ_RESOLVE:
 682       dw4 |= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE;
 683       break;
 684    case GEN6_HIZ_OP_NONE:
 685       break;
 686    default:
 687       unreachable("not reached");
 688    }
 689    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
 690    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
 691    dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 692    dw6 |= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 693    dw6 |= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT; /* No inputs from SF */
 694    if (params->use_wm_prog) {
 695       dw2 |= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 696       dw4 |= prog_data->first_curbe_grf << GEN6_WM_DISPATCH_START_GRF_SHIFT_0;
 697       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
 698       dw5 |= GEN6_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 699       dw5 |= GEN6_WM_DISPATCH_ENABLE; /* We are rendering */
 700    }
 701
 702    if (params->dst.num_samples > 1) {
 703       dw6 |= GEN6_WM_MSRAST_ON_PATTERN;
 704       if (prog_data && prog_data->persample_msaa_dispatch)
 705          dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
 706       else
 707          dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL;
 708    } else {
 709       dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
 710       dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
 711    }
 712
 713    BEGIN_BATCH(9);
 714    OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
 715    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 716    OUT_BATCH(dw2);
 717    OUT_BATCH(0); /* No scratch needed */
 718    OUT_BATCH(dw4);
 719    OUT_BATCH(dw5);
 720    OUT_BATCH(dw6);
 721    OUT_BATCH(0); /* No other programs */
 722    OUT_BATCH(0); /* No other programs */
 723    ADVANCE_BATCH();
 724 }
 725
 726
 727 static void
 728 gen6_blorp_emit_constant_ps(struct brw_context *brw,
 729                             const brw_blorp_params *params,
 730                             uint32_t wm_push_const_offset)
 731 {
 732    /* Make sure the push constants fill an exact integer number of
 733     * registers.
 734     */
 735    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 736
 737    /* There must be at least one register worth of push constant data. */
 738    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 739
 740    /* Enable push constant buffer 0. */
 741    BEGIN_BATCH(5);
 742    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 743              GEN6_CONSTANT_BUFFER_0_ENABLE |
 744              (5 - 2));
 745    OUT_BATCH(wm_push_const_offset + (BRW_BLORP_NUM_PUSH_CONST_REGS - 1));
 746    OUT_BATCH(0);
 747    OUT_BATCH(0);
 748    OUT_BATCH(0);
 749    ADVANCE_BATCH();
 750 }
 751
 752 static void
 753 gen6_blorp_emit_constant_ps_disable(struct brw_context *brw,
 754                                     const brw_blorp_params *params)
 755 {
 756    /* Disable the push constant buffers. */
 757    BEGIN_BATCH(5);
 758    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
 759    OUT_BATCH(0);
 760    OUT_BATCH(0);
 761    OUT_BATCH(0);
 762    OUT_BATCH(0);
 763    ADVANCE_BATCH();
 764 }
 765
 766 /**
 767  * 3DSTATE_BINDING_TABLE_POINTERS
 768  */
 769 static void
 770 gen6_blorp_emit_binding_table_pointers(struct brw_context *brw,
 771                                        uint32_t wm_bind_bo_offset)
 772 {
 773    BEGIN_BATCH(4);
 774    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
 775              GEN6_BINDING_TABLE_MODIFY_PS |
 776              (4 - 2));
 777    OUT_BATCH(0); /* vs -- ignored */
 778    OUT_BATCH(0); /* gs -- ignored */
 779    OUT_BATCH(wm_bind_bo_offset); /* wm/ps */
 780    ADVANCE_BATCH();
 781 }
 782
 783
 784 static void
 785 gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
 786                                      const brw_blorp_params *params)
 787 {
 788    uint32_t surfwidth, surfheight;
 789    uint32_t surftype;
 790    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
 791    GLenum gl_target = params->depth.mt->target;
 792    unsigned int lod;
 793
 794    switch (gl_target) {
 795    case GL_TEXTURE_CUBE_MAP_ARRAY:
 796    case GL_TEXTURE_CUBE_MAP:
 797       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 798        * situation, but experiments show that gl_Layer doesn't work when we do
 799        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 800        * equivalent.
 801        */
 802       surftype = BRW_SURFACE_2D;
 803       depth *= 6;
 804       break;
 805    default:
 806       surftype = translate_tex_target(gl_target);
 807       break;
 808    }
 809
 810    const unsigned min_array_element = params->depth.layer;
 811
 812    lod = params->depth.level - params->depth.mt->first_level;
 813
 814    if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
 815       /* HIZ ops for lod 0 may set the width & height a little
 816        * larger to allow the fast depth clear to fit the hardware
 817        * alignment requirements. (8x4)
 818        */
 819       surfwidth = params->depth.width;
 820       surfheight = params->depth.height;
 821    } else {
 822       surfwidth = params->depth.mt->logical_width0;
 823       surfheight = params->depth.mt->logical_height0;
 824    }
 825
 826    /* 3DSTATE_DEPTH_BUFFER */
 827    {
 828       brw_emit_depth_stall_flushes(brw);
 829
 830       BEGIN_BATCH(7);
 831       /* 3DSTATE_DEPTH_BUFFER dw0 */
 832       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 833
 834       /* 3DSTATE_DEPTH_BUFFER dw1 */
 835       OUT_BATCH((params->depth.mt->pitch - 1) |
 836                 params->depth_format << 18 |
 837                 1 << 21 | /* separate stencil enable */
 838                 1 << 22 | /* hiz enable */
 839                 BRW_TILEWALK_YMAJOR << 26 |
 840                 1 << 27 | /* y-tiled */
 841                 surftype << 29);
 842
 843       /* 3DSTATE_DEPTH_BUFFER dw2 */
 844       OUT_RELOC(params->depth.mt->bo,
 845                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 846                 0);
 847
 848       /* 3DSTATE_DEPTH_BUFFER dw3 */
 849       OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1 |
 850                 (surfwidth - 1) << 6 |
 851                 (surfheight - 1) << 19 |
 852                 lod << 2);
 853
 854       /* 3DSTATE_DEPTH_BUFFER dw4 */
 855       OUT_BATCH((depth - 1) << 21 |
 856                 min_array_element << 10 |
 857                 (depth - 1) << 1);
 858
 859       /* 3DSTATE_DEPTH_BUFFER dw5 */
 860       OUT_BATCH(0);
 861
 862       /* 3DSTATE_DEPTH_BUFFER dw6 */
 863       OUT_BATCH(0);
 864       ADVANCE_BATCH();
 865    }
 866
 867    /* 3DSTATE_HIER_DEPTH_BUFFER */
 868    {
 869       struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_buf->mt;
 870       uint32_t offset = 0;
 871
 872       if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 873          offset = intel_miptree_get_aligned_offset(hiz_mt,
 874                                                    hiz_mt->level[lod].level_x,
 875                                                    hiz_mt->level[lod].level_y,
 876                                                    false);
 877       }
 878
 879       BEGIN_BATCH(3);
 880       OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 881       OUT_BATCH(hiz_mt->pitch - 1);
 882       OUT_RELOC(hiz_mt->bo,
 883                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 884                 offset);
 885       ADVANCE_BATCH();
 886    }
 887
 888    /* 3DSTATE_STENCIL_BUFFER */
 889    {
 890       BEGIN_BATCH(3);
 891       OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 892       OUT_BATCH(0);
 893       OUT_BATCH(0);
 894       ADVANCE_BATCH();
 895    }
 896 }
 897
 898
 899 static void
 900 gen6_blorp_emit_depth_disable(struct brw_context *brw,
 901                               const brw_blorp_params *params)
 902 {
 903    brw_emit_depth_stall_flushes(brw);
 904
 905    BEGIN_BATCH(7);
 906    OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 907    OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 908              (BRW_SURFACE_NULL << 29));
 909    OUT_BATCH(0);
 910    OUT_BATCH(0);
 911    OUT_BATCH(0);
 912    OUT_BATCH(0);
 913    OUT_BATCH(0);
 914    ADVANCE_BATCH();
 915
 916    BEGIN_BATCH(3);
 917    OUT_BATCH(_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
 918    OUT_BATCH(0);
 919    OUT_BATCH(0);
 920    ADVANCE_BATCH();
 921
 922    BEGIN_BATCH(3);
 923    OUT_BATCH(_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 924    OUT_BATCH(0);
 925    OUT_BATCH(0);
 926    ADVANCE_BATCH();
 927 }
 928
 929
 930 /* 3DSTATE_CLEAR_PARAMS
 931  *
 932  * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
 933  *   [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
 934  *   packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
 935  */
 936 static void
 937 gen6_blorp_emit_clear_params(struct brw_context *brw,
 938                              const brw_blorp_params *params)
 939 {
 940    BEGIN_BATCH(2);
 941    OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
 942              GEN5_DEPTH_CLEAR_VALID |
 943              (2 - 2));
 944    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 945    ADVANCE_BATCH();
 946 }
 947
 948
 949 /* 3DSTATE_DRAWING_RECTANGLE */
 950 void
 951 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 952                                   const brw_blorp_params *params)
 953 {
 954    BEGIN_BATCH(4);
 955    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
 956    OUT_BATCH(0);
 957    OUT_BATCH(((MAX2(params->x1, params->x0) - 1) & 0xffff) |
 958              ((MAX2(params->y1, params->y0) - 1) << 16));
 959    OUT_BATCH(0);
 960    ADVANCE_BATCH();
 961 }
 962
 963 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
 964 void
 965 gen6_blorp_emit_viewport_state(struct brw_context *brw,
 966                                const brw_blorp_params *params)
 967 {
 968    struct brw_cc_viewport *ccv;
 969    uint32_t cc_vp_offset;
 970
 971    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 972                                                    sizeof(*ccv), 32,
 973                                                    &cc_vp_offset);
 974
 975    ccv->min_depth = 0.0;
 976    ccv->max_depth = 1.0;
 977
 978    BEGIN_BATCH(4);
 979    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS << 16 | (4 - 2) |
 980              GEN6_CC_VIEWPORT_MODIFY);
 981    OUT_BATCH(0); /* clip VP */
 982    OUT_BATCH(0); /* SF VP */
 983    OUT_BATCH(cc_vp_offset);
 984    ADVANCE_BATCH();
 985 }
 986
 987
 988 /* 3DPRIMITIVE */
 989 static void
 990 gen6_blorp_emit_primitive(struct brw_context *brw,
 991                           const brw_blorp_params *params)
 992 {
 993    BEGIN_BATCH(6);
 994    OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) |
 995              _3DPRIM_RECTLIST << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT |
 996              GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
 997    OUT_BATCH(3); /* vertex count per instance */
 998    OUT_BATCH(0);
 999    OUT_BATCH(params->num_layers); /* instance count */
1000    OUT_BATCH(0);
1001    OUT_BATCH(0);
1002    ADVANCE_BATCH();
1003 }
1004
1005 /**
1006  * \brief Execute a blit or render pass operation.
1007  *
1008  * To execute the operation, this function manually constructs and emits a
1009  * batch to draw a rectangle primitive. The batchbuffer is flushed before
1010  * constructing and after emitting the batch.
1011  *
1012  * This function alters no GL state.
1013  */
1014 void
1015 gen6_blorp_exec(struct brw_context *brw,
1016                 const brw_blorp_params *params)
1017 {
1018    brw_blorp_prog_data *prog_data = NULL;
1019    uint32_t cc_blend_state_offset = 0;
1020    uint32_t cc_state_offset = 0;
1021    uint32_t depthstencil_offset;
1022    uint32_t wm_push_const_offset = 0;
1023    uint32_t wm_bind_bo_offset = 0;
1024
1025    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
1026
1027    /* Emit workaround flushes when we switch from drawing to blorping. */
1028    brw_emit_post_sync_nonzero_flush(brw);
1029
1030    gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
1031    gen6_emit_3dstate_sample_mask(brw,
1032                                  params->dst.num_samples > 1 ?
1033                                  (1 << params->dst.num_samples) - 1 : 1);
1034    gen6_blorp_emit_state_base_address(brw, params);
1035    gen6_blorp_emit_vertices(brw, params);
1036    gen6_blorp_emit_urb_config(brw, params);
1037    if (params->use_wm_prog) {
1038       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
1039       cc_state_offset = gen6_blorp_emit_cc_state(brw);
1040    }
1041    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
1042    gen6_blorp_emit_cc_state_pointers(brw, params, cc_blend_state_offset,
1043                                      depthstencil_offset, cc_state_offset);
1044    if (params->use_wm_prog) {
1045       uint32_t wm_surf_offset_renderbuffer;
1046       uint32_t wm_surf_offset_texture = 0;
1047       uint32_t sampler_offset;
1048       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
1049       intel_miptree_used_for_rendering(params->dst.mt);
1050       wm_surf_offset_renderbuffer =
1051          gen6_blorp_emit_surface_state(brw, params, &params->dst,
1052                                        I915_GEM_DOMAIN_RENDER,
1053                                        I915_GEM_DOMAIN_RENDER);
1054       if (params->src.mt) {
1055          wm_surf_offset_texture =
1056             gen6_blorp_emit_surface_state(brw, params, &params->src,
1057                                           I915_GEM_DOMAIN_SAMPLER, 0);
1058       }
1059       wm_bind_bo_offset =
1060          gen6_blorp_emit_binding_table(brw,
1061                                        wm_surf_offset_renderbuffer,
1062                                        wm_surf_offset_texture);
1063       sampler_offset =
1064          gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
1065       gen6_blorp_emit_sampler_state_pointers(brw, sampler_offset);
1066    }
1067    gen6_blorp_emit_vs_disable(brw, params);
1068    gen6_blorp_emit_gs_disable(brw, params);
1069    gen6_blorp_emit_clip_disable(brw);
1070    gen6_blorp_emit_sf_config(brw, params);
1071    if (params->use_wm_prog)
1072       gen6_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
1073    else
1074       gen6_blorp_emit_constant_ps_disable(brw, params);
1075    gen6_blorp_emit_wm_config(brw, params, prog_offset, prog_data);
1076    if (params->use_wm_prog)
1077       gen6_blorp_emit_binding_table_pointers(brw, wm_bind_bo_offset);
1078    gen6_blorp_emit_viewport_state(brw, params);
1079
1080    if (params->depth.mt)
1081       gen6_blorp_emit_depth_stencil_config(brw, params);
1082    else
1083       gen6_blorp_emit_depth_disable(brw, params);
1084    gen6_blorp_emit_clear_params(brw, params);
1085    gen6_blorp_emit_drawing_rectangle(brw, params);
1086    gen6_blorp_emit_primitive(brw, params);
1087 }
1088