src/mesa/drivers/dri/i965/gen6_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen6_blorp.h"
  36
  37 /**
  38  * \name Constants for BLORP VBO
  39  * \{
  40  */
  41 #define GEN6_BLORP_NUM_VERTICES 3
  42 #define GEN6_BLORP_NUM_VUE_ELEMS 8
  43 #define GEN6_BLORP_VBO_SIZE (GEN6_BLORP_NUM_VERTICES \
  44                              * GEN6_BLORP_NUM_VUE_ELEMS \
  45                              * sizeof(float))
  46 /** \} */
  47
  48 /**
  49  * CMD_STATE_BASE_ADDRESS
  50  *
  51  * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS:
  52  *     The following commands must be reissued following any change to the
  53  *     base addresses:
  54  *         3DSTATE_CC_POINTERS
  55  *         3DSTATE_BINDING_TABLE_POINTERS
  56  *         3DSTATE_SAMPLER_STATE_POINTERS
  57  *         3DSTATE_VIEWPORT_STATE_POINTERS
  58  *         MEDIA_STATE_POINTERS
  59  */
  60 void
  61 gen6_blorp_emit_state_base_address(struct brw_context *brw,
  62                                    const brw_blorp_params *params)
  63 {
  64    uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
  65
  66    BEGIN_BATCH(10);
  67    OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
  68    OUT_BATCH(mocs << 8 | /* GeneralStateMemoryObjectControlState */
  69              mocs << 4 | /* StatelessDataPortAccessMemoryObjectControlState */
  70              1); /* GeneralStateBaseAddressModifyEnable */
  71
  72    /* SurfaceStateBaseAddress */
  73    OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
  74    /* DynamicStateBaseAddress */
  75    OUT_RELOC(brw->batch.bo, (I915_GEM_DOMAIN_RENDER |
  76                                I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
  77    OUT_BATCH(1); /* IndirectObjectBaseAddress */
  78    if (params->use_wm_prog) {
  79       OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
  80                 1); /* Instruction base address: shader kernels */
  81    } else {
  82       OUT_BATCH(1); /* InstructionBaseAddress */
  83    }
  84    OUT_BATCH(1); /* GeneralStateUpperBound */
  85    /* Dynamic state upper bound.  Although the documentation says that
  86     * programming it to zero will cause it to be ignored, that is a lie.
  87     * If this isn't programmed to a real bound, the sampler border color
  88     * pointer is rejected, causing border color to mysteriously fail.
  89     */
  90    OUT_BATCH(0xfffff001);
  91    OUT_BATCH(1); /* IndirectObjectUpperBound*/
  92    OUT_BATCH(1); /* InstructionAccessUpperBound */
  93    ADVANCE_BATCH();
  94 }
  95
  96
  97 void
  98 gen6_blorp_emit_vertices(struct brw_context *brw,
  99                          const brw_blorp_params *params)
 100 {
 101    uint32_t vertex_offset;
 102
 103    /* Setup VBO for the rectangle primitive..
 104     *
 105     * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
 106     * vertices. The vertices reside in screen space with DirectX coordinates
 107     * (that is, (0, 0) is the upper left corner).
 108     *
 109     *   v2 ------ implied
 110     *    |        |
 111     *    |        |
 112     *   v0 ----- v1
 113     *
 114     * Since the VS is disabled, the clipper loads each VUE directly from
 115     * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
 116     * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
 117     *   dw0: Reserved, MBZ.
 118     *   dw1: Render Target Array Index. The HiZ op does not use indexed
 119     *        vertices, so set the dword to 0.
 120     *   dw2: Viewport Index. The HiZ op disables viewport mapping and
 121     *        scissoring, so set the dword to 0.
 122     *   dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
 123     *        set the dword to 0.
 124     *   dw4: Vertex Position X.
 125     *   dw5: Vertex Position Y.
 126     *   dw6: Vertex Position Z.
 127     *   dw7: Vertex Position W.
 128     *
 129     * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
 130     * "Vertex URB Entry (VUE) Formats".
 131     */
 132    {
 133       float *vertex_data;
 134
 135       const float vertices[GEN6_BLORP_VBO_SIZE] = {
 136          /* v0 */ 0, 0, 0, 0,     (float) params->x0, (float) params->y1, 0, 1,
 137          /* v1 */ 0, 0, 0, 0,     (float) params->x1, (float) params->y1, 0, 1,
 138          /* v2 */ 0, 0, 0, 0,     (float) params->x0, (float) params->y0, 0, 1,
 139       };
 140
 141       vertex_data = (float *) brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER,
 142                                               GEN6_BLORP_VBO_SIZE, 32,
 143                                               &vertex_offset);
 144       memcpy(vertex_data, vertices, GEN6_BLORP_VBO_SIZE);
 145    }
 146
 147    /* 3DSTATE_VERTEX_BUFFERS */
 148    {
 149       const int num_buffers = 1;
 150       const int batch_length = 1 + 4 * num_buffers;
 151
 152       uint32_t dw0 = GEN6_VB0_ACCESS_VERTEXDATA |
 153                      (GEN6_BLORP_NUM_VUE_ELEMS * sizeof(float)) << BRW_VB0_PITCH_SHIFT;
 154
 155       if (brw->gen >= 7)
 156          dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
 157
 158       if (brw->gen == 7)
 159          dw0 |= GEN7_MOCS_L3 << 16;
 160
 161       BEGIN_BATCH(batch_length);
 162       OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
 163       OUT_BATCH(dw0);
 164       /* start address */
 165       OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
 166                 vertex_offset);
 167       /* end address */
 168       OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
 169                 vertex_offset + GEN6_BLORP_VBO_SIZE - 1);
 170       OUT_BATCH(0);
 171       ADVANCE_BATCH();
 172    }
 173
 174    /* 3DSTATE_VERTEX_ELEMENTS
 175     *
 176     * Fetch dwords 0 - 7 from each VUE. See the comments above where
 177     * the vertex_bo is filled with data.
 178     */
 179    {
 180       const int num_elements = 2;
 181       const int batch_length = 1 + 2 * num_elements;
 182
 183       BEGIN_BATCH(batch_length);
 184       OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (batch_length - 2));
 185       /* Element 0 */
 186       OUT_BATCH(GEN6_VE0_VALID |
 187                 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT |
 188                 0 << BRW_VE0_SRC_OFFSET_SHIFT);
 189       OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT |
 190                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_1_SHIFT |
 191                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_2_SHIFT |
 192                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_3_SHIFT);
 193       /* Element 1 */
 194       OUT_BATCH(GEN6_VE0_VALID |
 195                 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT |
 196                 16 << BRW_VE0_SRC_OFFSET_SHIFT);
 197       OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT |
 198                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_1_SHIFT |
 199                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_2_SHIFT |
 200                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_3_SHIFT);
 201       ADVANCE_BATCH();
 202    }
 203 }
 204
 205
 206 /* 3DSTATE_URB
 207  *
 208  * Assign the entire URB to the VS. Even though the VS disabled, URB space
 209  * is still needed because the clipper loads the VUE's from the URB. From
 210  * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
 211  * Dword 1.15:0 "VS Number of URB Entries":
 212  *     This field is always used (even if VS Function Enable is DISABLED).
 213  *
 214  * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
 215  * safely ignore it because this batch contains only one draw call.
 216  *     Because of URB corruption caused by allocating a previous GS unit
 217  *     URB entry to the VS unit, software is required to send a “GS NULL
 218  *     Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
 219  *     plus a dummy DRAW call before any case where VS will be taking over
 220  *     GS URB space.
 221  */
 222 static void
 223 gen6_blorp_emit_urb_config(struct brw_context *brw,
 224                            const brw_blorp_params *params)
 225 {
 226    BEGIN_BATCH(3);
 227    OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2));
 228    OUT_BATCH(brw->urb.max_vs_entries << GEN6_URB_VS_ENTRIES_SHIFT);
 229    OUT_BATCH(0);
 230    ADVANCE_BATCH();
 231 }
 232
 233
 234 /* BLEND_STATE */
 235 uint32_t
 236 gen6_blorp_emit_blend_state(struct brw_context *brw,
 237                             const brw_blorp_params *params)
 238 {
 239    uint32_t cc_blend_state_offset;
 240
 241    struct gen6_blend_state *blend = (struct gen6_blend_state *)
 242       brw_state_batch(brw, AUB_TRACE_BLEND_STATE,
 243                       sizeof(struct gen6_blend_state), 64,
 244                       &cc_blend_state_offset);
 245
 246    memset(blend, 0, sizeof(*blend));
 247
 248    blend->blend1.pre_blend_clamp_enable = 1;
 249    blend->blend1.post_blend_clamp_enable = 1;
 250    blend->blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
 251
 252    blend->blend1.write_disable_r = params->color_write_disable[0];
 253    blend->blend1.write_disable_g = params->color_write_disable[1];
 254    blend->blend1.write_disable_b = params->color_write_disable[2];
 255    blend->blend1.write_disable_a = params->color_write_disable[3];
 256
 257    return cc_blend_state_offset;
 258 }
 259
 260
 261 /* CC_STATE */
 262 uint32_t
 263 gen6_blorp_emit_cc_state(struct brw_context *brw,
 264                          const brw_blorp_params *params)
 265 {
 266    uint32_t cc_state_offset;
 267
 268    struct gen6_color_calc_state *cc = (struct gen6_color_calc_state *)
 269       brw_state_batch(brw, AUB_TRACE_CC_STATE,
 270                       sizeof(gen6_color_calc_state), 64,
 271                       &cc_state_offset);
 272    memset(cc, 0, sizeof(*cc));
 273
 274    return cc_state_offset;
 275 }
 276
 277
 278 /**
 279  * \param out_offset is relative to
 280  *        CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 281  */
 282 uint32_t
 283 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 284                                     const brw_blorp_params *params)
 285 {
 286    uint32_t depthstencil_offset;
 287
 288    struct gen6_depth_stencil_state *state;
 289    state = (struct gen6_depth_stencil_state *)
 290       brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
 291                       sizeof(*state), 64,
 292                       &depthstencil_offset);
 293    memset(state, 0, sizeof(*state));
 294
 295    /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
 296     *   - 7.5.3.1 Depth Buffer Clear
 297     *   - 7.5.3.2 Depth Buffer Resolve
 298     *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 299     */
 300    state->ds2.depth_write_enable = 1;
 301    if (params->hiz_op == GEN6_HIZ_OP_DEPTH_RESOLVE) {
 302       state->ds2.depth_test_enable = 1;
 303       state->ds2.depth_test_func = BRW_COMPAREFUNCTION_NEVER;
 304    }
 305
 306    return depthstencil_offset;
 307 }
 308
 309
 310 /* 3DSTATE_CC_STATE_POINTERS
 311  *
 312  * The pointer offsets are relative to
 313  * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 314  *
 315  * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
 316  */
 317 static void
 318 gen6_blorp_emit_cc_state_pointers(struct brw_context *brw,
 319                                   const brw_blorp_params *params,
 320                                   uint32_t cc_blend_state_offset,
 321                                   uint32_t depthstencil_offset,
 322                                   uint32_t cc_state_offset)
 323 {
 324    BEGIN_BATCH(4);
 325    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
 326    OUT_BATCH(cc_blend_state_offset | 1); /* BLEND_STATE offset */
 327    OUT_BATCH(depthstencil_offset | 1); /* DEPTH_STENCIL_STATE offset */
 328    OUT_BATCH(cc_state_offset | 1); /* COLOR_CALC_STATE offset */
 329    ADVANCE_BATCH();
 330 }
 331
 332
 333 /* WM push constants */
 334 uint32_t
 335 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 336                              const brw_blorp_params *params)
 337 {
 338    uint32_t wm_push_const_offset;
 339
 340    void *constants = brw_state_batch(brw, AUB_TRACE_WM_CONSTANTS,
 341                                      sizeof(params->wm_push_consts),
 342                                      32, &wm_push_const_offset);
 343    memcpy(constants, &params->wm_push_consts,
 344           sizeof(params->wm_push_consts));
 345
 346    return wm_push_const_offset;
 347 }
 348
 349
 350 /* SURFACE_STATE for renderbuffer or texture surface (see
 351  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 352  */
 353 static uint32_t
 354 gen6_blorp_emit_surface_state(struct brw_context *brw,
 355                               const brw_blorp_params *params,
 356                               const brw_blorp_surface_info *surface,
 357                               uint32_t read_domains, uint32_t write_domain)
 358 {
 359    uint32_t wm_surf_offset;
 360    uint32_t width = surface->width;
 361    uint32_t height = surface->height;
 362    if (surface->num_samples > 1) {
 363       /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
 364        * in samples.  But SURFACE_STATE wants them in pixels, so we need to
 365        * divide them each by 2.
 366        */
 367       width /= 2;
 368       height /= 2;
 369    }
 370    struct intel_mipmap_tree *mt = surface->mt;
 371    uint32_t tile_x, tile_y;
 372
 373    uint32_t *surf = (uint32_t *)
 374       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 375                       &wm_surf_offset);
 376
 377    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 378               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 379               BRW_SURFACE_CUBEFACE_ENABLES |
 380               surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT);
 381
 382    /* reloc */
 383    surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) +
 384               mt->bo->offset64);
 385
 386    surf[2] = (0 << BRW_SURFACE_LOD_SHIFT |
 387               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 388               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 389
 390    uint32_t tiling = surface->map_stencil_as_y_tiled
 391       ? BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y
 392       : brw_get_surface_tiling_bits(mt->tiling);
 393    uint32_t pitch_bytes = mt->pitch;
 394    if (surface->map_stencil_as_y_tiled)
 395       pitch_bytes *= 2;
 396    surf[3] = (tiling |
 397               0 << BRW_SURFACE_DEPTH_SHIFT |
 398               (pitch_bytes - 1) << BRW_SURFACE_PITCH_SHIFT);
 399
 400    surf[4] = brw_get_surface_num_multisamples(surface->num_samples);
 401
 402    /* Note that the low bits of these fields are missing, so
 403     * there's the possibility of getting in trouble.
 404     */
 405    assert(tile_x % 4 == 0);
 406    assert(tile_y % 2 == 0);
 407    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 408               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
 409               (surface->mt->align_h == 4 ?
 410                BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
 411
 412    /* Emit relocation to surface contents */
 413    drm_intel_bo_emit_reloc(brw->batch.bo,
 414                            wm_surf_offset + 4,
 415                            mt->bo,
 416                            surf[1] - mt->bo->offset64,
 417                            read_domains, write_domain);
 418
 419    return wm_surf_offset;
 420 }
 421
 422
 423 /* BINDING_TABLE.  See brw_wm_binding_table(). */
 424 uint32_t
 425 gen6_blorp_emit_binding_table(struct brw_context *brw,
 426                               const brw_blorp_params *params,
 427                               uint32_t wm_surf_offset_renderbuffer,
 428                               uint32_t wm_surf_offset_texture)
 429 {
 430    uint32_t wm_bind_bo_offset;
 431    uint32_t *bind = (uint32_t *)
 432       brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
 433                       sizeof(uint32_t) *
 434                       BRW_BLORP_NUM_BINDING_TABLE_ENTRIES,
 435                       32, /* alignment */
 436                       &wm_bind_bo_offset);
 437    bind[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX] =
 438       wm_surf_offset_renderbuffer;
 439    bind[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX] = wm_surf_offset_texture;
 440
 441    return wm_bind_bo_offset;
 442 }
 443
 444
 445 /**
 446  * SAMPLER_STATE.  See brw_update_sampler_state().
 447  */
 448 uint32_t
 449 gen6_blorp_emit_sampler_state(struct brw_context *brw,
 450                               const brw_blorp_params *params)
 451 {
 452    uint32_t sampler_offset;
 453    uint32_t *sampler_state = (uint32_t *)
 454       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE, 16, 32, &sampler_offset);
 455
 456    unsigned address_rounding = BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 457                                BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 458                                BRW_ADDRESS_ROUNDING_ENABLE_R_MIN |
 459                                BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 460                                BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 461                                BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 462
 463    /* XXX: I don't think that using firstLevel, lastLevel works,
 464     * because we always setup the surface state as if firstLevel ==
 465     * level zero.  Probably have to subtract firstLevel from each of
 466     * these:
 467     */
 468    brw_emit_sampler_state(brw,
 469                           sampler_state,
 470                           sampler_offset,
 471                           BRW_MAPFILTER_LINEAR, /* min filter */
 472                           BRW_MAPFILTER_LINEAR, /* mag filter */
 473                           BRW_MIPFILTER_NONE,
 474                           BRW_ANISORATIO_2,
 475                           address_rounding,
 476                           BRW_TEXCOORDMODE_CLAMP,
 477                           BRW_TEXCOORDMODE_CLAMP,
 478                           BRW_TEXCOORDMODE_CLAMP,
 479                           0, /* min LOD */
 480                           0, /* max LOD */
 481                           0, /* LOD bias */
 482                           0, /* base miplevel */
 483                           0, /* shadow function */
 484                           true, /* non-normalized coordinates */
 485                           0); /* border color offset - unused */
 486
 487    return sampler_offset;
 488 }
 489
 490
 491 /**
 492  * 3DSTATE_SAMPLER_STATE_POINTERS.  See upload_sampler_state_pointers().
 493  */
 494 static void
 495 gen6_blorp_emit_sampler_state_pointers(struct brw_context *brw,
 496                                        const brw_blorp_params *params,
 497                                        uint32_t sampler_offset)
 498 {
 499    BEGIN_BATCH(4);
 500    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS << 16 |
 501              VS_SAMPLER_STATE_CHANGE |
 502              GS_SAMPLER_STATE_CHANGE |
 503              PS_SAMPLER_STATE_CHANGE |
 504              (4 - 2));
 505    OUT_BATCH(0); /* VS */
 506    OUT_BATCH(0); /* GS */
 507    OUT_BATCH(sampler_offset);
 508    ADVANCE_BATCH();
 509 }
 510
 511
 512 /* 3DSTATE_VS
 513  *
 514  * Disable vertex shader.
 515  */
 516 void
 517 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 518                            const brw_blorp_params *params)
 519 {
 520    if (brw->gen == 6) {
 521       /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
 522        * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
 523        *
 524        *   [DevSNB] A pipeline flush must be programmed prior to a
 525        *   3DSTATE_VS command that causes the VS Function Enable to
 526        *   toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
 527        *   command with CS stall bit set and a post sync operation.
 528        */
 529       intel_emit_post_sync_nonzero_flush(brw);
 530    }
 531
 532    /* Disable the push constant buffers. */
 533    BEGIN_BATCH(5);
 534    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
 535    OUT_BATCH(0);
 536    OUT_BATCH(0);
 537    OUT_BATCH(0);
 538    OUT_BATCH(0);
 539    ADVANCE_BATCH();
 540
 541    BEGIN_BATCH(6);
 542    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 543    OUT_BATCH(0);
 544    OUT_BATCH(0);
 545    OUT_BATCH(0);
 546    OUT_BATCH(0);
 547    OUT_BATCH(0);
 548    ADVANCE_BATCH();
 549 }
 550
 551
 552 /* 3DSTATE_GS
 553  *
 554  * Disable the geometry shader.
 555  */
 556 void
 557 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 558                            const brw_blorp_params *params)
 559 {
 560    /* Disable all the constant buffers. */
 561    BEGIN_BATCH(5);
 562    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (5 - 2));
 563    OUT_BATCH(0);
 564    OUT_BATCH(0);
 565    OUT_BATCH(0);
 566    OUT_BATCH(0);
 567    ADVANCE_BATCH();
 568
 569    BEGIN_BATCH(7);
 570    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 571    OUT_BATCH(0);
 572    OUT_BATCH(0);
 573    OUT_BATCH(0);
 574    OUT_BATCH(0);
 575    OUT_BATCH(0);
 576    OUT_BATCH(0);
 577    ADVANCE_BATCH();
 578    brw->gs.enabled = false;
 579 }
 580
 581
 582 /* 3DSTATE_CLIP
 583  *
 584  * Disable the clipper.
 585  *
 586  * The BLORP op emits a rectangle primitive, which requires clipping to
 587  * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
 588  * Section 1.3 "3D Primitives Overview":
 589  *    RECTLIST:
 590  *    Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
 591  *    Mode should be set to a value other than CLIPMODE_NORMAL.
 592  *
 593  * Also disable perspective divide. This doesn't change the clipper's
 594  * output, but does spare a few electrons.
 595  */
 596 void
 597 gen6_blorp_emit_clip_disable(struct brw_context *brw,
 598                              const brw_blorp_params *params)
 599 {
 600    BEGIN_BATCH(4);
 601    OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2));
 602    OUT_BATCH(0);
 603    OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE);
 604    OUT_BATCH(0);
 605    ADVANCE_BATCH();
 606 }
 607
 608
 609 /* 3DSTATE_SF
 610  *
 611  * Disable ViewportTransformEnable (dw2.1)
 612  *
 613  * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 614  * Primitives Overview":
 615  *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 616  *     use of screen- space coordinates).
 617  *
 618  * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
 619  * and BackFaceFillMode (dw2.5:6) to SOLID(0).
 620  *
 621  * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 622  * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 623  *     SOLID: Any triangle or rectangle object found to be front-facing
 624  *     is rendered as a solid object. This setting is required when
 625  *     (rendering rectangle (RECTLIST) objects.
 626  */
 627 static void
 628 gen6_blorp_emit_sf_config(struct brw_context *brw,
 629                           const brw_blorp_params *params)
 630 {
 631    BEGIN_BATCH(20);
 632    OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2));
 633    OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT | /* only position */
 634              1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
 635              0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT);
 636    OUT_BATCH(0); /* dw2 */
 637    OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 638    for (int i = 0; i < 16; ++i)
 639       OUT_BATCH(0);
 640    ADVANCE_BATCH();
 641 }
 642
 643
 644 /**
 645  * Enable or disable thread dispatch and set the HiZ op appropriately.
 646  */
 647 static void
 648 gen6_blorp_emit_wm_config(struct brw_context *brw,
 649                           const brw_blorp_params *params,
 650                           uint32_t prog_offset,
 651                           brw_blorp_prog_data *prog_data)
 652 {
 653    uint32_t dw2, dw4, dw5, dw6;
 654
 655    /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
 656     * nonzero to prevent the GPU from hanging.  While the documentation doesn't
 657     * mention this explicitly, it notes that the valid range for the field is
 658     * [1,39] = [2,40] threads, which excludes zero.
 659     *
 660     * To be safe (and to minimize extraneous code) we go ahead and fully
 661     * configure the WM state whether or not there is a WM program.
 662     */
 663
 664    dw2 = dw4 = dw5 = dw6 = 0;
 665    switch (params->hiz_op) {
 666    case GEN6_HIZ_OP_DEPTH_CLEAR:
 667       dw4 |= GEN6_WM_DEPTH_CLEAR;
 668       break;
 669    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 670       dw4 |= GEN6_WM_DEPTH_RESOLVE;
 671       break;
 672    case GEN6_HIZ_OP_HIZ_RESOLVE:
 673       dw4 |= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE;
 674       break;
 675    case GEN6_HIZ_OP_NONE:
 676       break;
 677    default:
 678       unreachable("not reached");
 679    }
 680    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
 681    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
 682    dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 683    dw6 |= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 684    dw6 |= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT; /* No inputs from SF */
 685    if (params->use_wm_prog) {
 686       dw2 |= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 687       dw4 |= prog_data->first_curbe_grf << GEN6_WM_DISPATCH_START_GRF_SHIFT_0;
 688       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
 689       dw5 |= GEN6_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 690       dw5 |= GEN6_WM_DISPATCH_ENABLE; /* We are rendering */
 691    }
 692
 693    if (params->dst.num_samples > 1) {
 694       dw6 |= GEN6_WM_MSRAST_ON_PATTERN;
 695       if (prog_data && prog_data->persample_msaa_dispatch)
 696          dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
 697       else
 698          dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL;
 699    } else {
 700       dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
 701       dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
 702    }
 703
 704    BEGIN_BATCH(9);
 705    OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
 706    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 707    OUT_BATCH(dw2);
 708    OUT_BATCH(0); /* No scratch needed */
 709    OUT_BATCH(dw4);
 710    OUT_BATCH(dw5);
 711    OUT_BATCH(dw6);
 712    OUT_BATCH(0); /* No other programs */
 713    OUT_BATCH(0); /* No other programs */
 714    ADVANCE_BATCH();
 715 }
 716
 717
 718 static void
 719 gen6_blorp_emit_constant_ps(struct brw_context *brw,
 720                             const brw_blorp_params *params,
 721                             uint32_t wm_push_const_offset)
 722 {
 723    /* Make sure the push constants fill an exact integer number of
 724     * registers.
 725     */
 726    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 727
 728    /* There must be at least one register worth of push constant data. */
 729    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 730
 731    /* Enable push constant buffer 0. */
 732    BEGIN_BATCH(5);
 733    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 734              GEN6_CONSTANT_BUFFER_0_ENABLE |
 735              (5 - 2));
 736    OUT_BATCH(wm_push_const_offset + (BRW_BLORP_NUM_PUSH_CONST_REGS - 1));
 737    OUT_BATCH(0);
 738    OUT_BATCH(0);
 739    OUT_BATCH(0);
 740    ADVANCE_BATCH();
 741 }
 742
 743 static void
 744 gen6_blorp_emit_constant_ps_disable(struct brw_context *brw,
 745                                     const brw_blorp_params *params)
 746 {
 747    /* Disable the push constant buffers. */
 748    BEGIN_BATCH(5);
 749    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
 750    OUT_BATCH(0);
 751    OUT_BATCH(0);
 752    OUT_BATCH(0);
 753    OUT_BATCH(0);
 754    ADVANCE_BATCH();
 755 }
 756
 757 /**
 758  * 3DSTATE_BINDING_TABLE_POINTERS
 759  */
 760 static void
 761 gen6_blorp_emit_binding_table_pointers(struct brw_context *brw,
 762                                        const brw_blorp_params *params,
 763                                        uint32_t wm_bind_bo_offset)
 764 {
 765    BEGIN_BATCH(4);
 766    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
 767              GEN6_BINDING_TABLE_MODIFY_PS |
 768              (4 - 2));
 769    OUT_BATCH(0); /* vs -- ignored */
 770    OUT_BATCH(0); /* gs -- ignored */
 771    OUT_BATCH(wm_bind_bo_offset); /* wm/ps */
 772    ADVANCE_BATCH();
 773 }
 774
 775
 776 static void
 777 gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
 778                                      const brw_blorp_params *params)
 779 {
 780    uint32_t surfwidth, surfheight;
 781    uint32_t surftype;
 782    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
 783    GLenum gl_target = params->depth.mt->target;
 784    unsigned int lod;
 785
 786    switch (gl_target) {
 787    case GL_TEXTURE_CUBE_MAP_ARRAY:
 788    case GL_TEXTURE_CUBE_MAP:
 789       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 790        * situation, but experiments show that gl_Layer doesn't work when we do
 791        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 792        * equivalent.
 793        */
 794       surftype = BRW_SURFACE_2D;
 795       depth *= 6;
 796       break;
 797    default:
 798       surftype = translate_tex_target(gl_target);
 799       break;
 800    }
 801
 802    const unsigned min_array_element = params->depth.layer;
 803
 804    lod = params->depth.level - params->depth.mt->first_level;
 805
 806    if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
 807       /* HIZ ops for lod 0 may set the width & height a little
 808        * larger to allow the fast depth clear to fit the hardware
 809        * alignment requirements. (8x4)
 810        */
 811       surfwidth = params->depth.width;
 812       surfheight = params->depth.height;
 813    } else {
 814       surfwidth = params->depth.mt->logical_width0;
 815       surfheight = params->depth.mt->logical_height0;
 816    }
 817
 818    /* 3DSTATE_DEPTH_BUFFER */
 819    {
 820       intel_emit_post_sync_nonzero_flush(brw);
 821       intel_emit_depth_stall_flushes(brw);
 822
 823       BEGIN_BATCH(7);
 824       /* 3DSTATE_DEPTH_BUFFER dw0 */
 825       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 826
 827       /* 3DSTATE_DEPTH_BUFFER dw1 */
 828       OUT_BATCH((params->depth.mt->pitch - 1) |
 829                 params->depth_format << 18 |
 830                 1 << 21 | /* separate stencil enable */
 831                 1 << 22 | /* hiz enable */
 832                 BRW_TILEWALK_YMAJOR << 26 |
 833                 1 << 27 | /* y-tiled */
 834                 surftype << 29);
 835
 836       /* 3DSTATE_DEPTH_BUFFER dw2 */
 837       OUT_RELOC(params->depth.mt->bo,
 838                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 839                 0);
 840
 841       /* 3DSTATE_DEPTH_BUFFER dw3 */
 842       OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1 |
 843                 (surfwidth - 1) << 6 |
 844                 (surfheight - 1) << 19 |
 845                 lod << 2);
 846
 847       /* 3DSTATE_DEPTH_BUFFER dw4 */
 848       OUT_BATCH((depth - 1) << 21 |
 849                 min_array_element << 10 |
 850                 (depth - 1) << 1);
 851
 852       /* 3DSTATE_DEPTH_BUFFER dw5 */
 853       OUT_BATCH(0);
 854
 855       /* 3DSTATE_DEPTH_BUFFER dw6 */
 856       OUT_BATCH(0);
 857       ADVANCE_BATCH();
 858    }
 859
 860    /* 3DSTATE_HIER_DEPTH_BUFFER */
 861    {
 862       struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_mt;
 863       uint32_t offset = 0;
 864
 865       if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 866          offset = intel_miptree_get_aligned_offset(hiz_mt,
 867                                                    hiz_mt->level[lod].level_x,
 868                                                    hiz_mt->level[lod].level_y,
 869                                                    false);
 870       }
 871
 872       BEGIN_BATCH(3);
 873       OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 874       OUT_BATCH(hiz_mt->pitch - 1);
 875       OUT_RELOC(hiz_mt->bo,
 876                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 877                 offset);
 878       ADVANCE_BATCH();
 879    }
 880
 881    /* 3DSTATE_STENCIL_BUFFER */
 882    {
 883       BEGIN_BATCH(3);
 884       OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 885       OUT_BATCH(0);
 886       OUT_BATCH(0);
 887       ADVANCE_BATCH();
 888    }
 889 }
 890
 891
 892 static void
 893 gen6_blorp_emit_depth_disable(struct brw_context *brw,
 894                               const brw_blorp_params *params)
 895 {
 896    intel_emit_post_sync_nonzero_flush(brw);
 897    intel_emit_depth_stall_flushes(brw);
 898
 899    BEGIN_BATCH(7);
 900    OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 901    OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 902              (BRW_SURFACE_NULL << 29));
 903    OUT_BATCH(0);
 904    OUT_BATCH(0);
 905    OUT_BATCH(0);
 906    OUT_BATCH(0);
 907    OUT_BATCH(0);
 908    ADVANCE_BATCH();
 909
 910    BEGIN_BATCH(3);
 911    OUT_BATCH(_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
 912    OUT_BATCH(0);
 913    OUT_BATCH(0);
 914    ADVANCE_BATCH();
 915
 916    BEGIN_BATCH(3);
 917    OUT_BATCH(_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 918    OUT_BATCH(0);
 919    OUT_BATCH(0);
 920    ADVANCE_BATCH();
 921 }
 922
 923
 924 /* 3DSTATE_CLEAR_PARAMS
 925  *
 926  * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
 927  *   [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
 928  *   packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
 929  */
 930 static void
 931 gen6_blorp_emit_clear_params(struct brw_context *brw,
 932                              const brw_blorp_params *params)
 933 {
 934    BEGIN_BATCH(2);
 935    OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
 936              GEN5_DEPTH_CLEAR_VALID |
 937              (2 - 2));
 938    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 939    ADVANCE_BATCH();
 940 }
 941
 942
 943 /* 3DSTATE_DRAWING_RECTANGLE */
 944 void
 945 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 946                                   const brw_blorp_params *params)
 947 {
 948    if (brw->gen == 6)
 949       intel_emit_post_sync_nonzero_flush(brw);
 950
 951    BEGIN_BATCH(4);
 952    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
 953    OUT_BATCH(0);
 954    OUT_BATCH(((params->x1 - 1) & 0xffff) |
 955              ((params->y1 - 1) << 16));
 956    OUT_BATCH(0);
 957    ADVANCE_BATCH();
 958 }
 959
 960 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
 961 void
 962 gen6_blorp_emit_viewport_state(struct brw_context *brw,
 963                                const brw_blorp_params *params)
 964 {
 965    struct brw_cc_viewport *ccv;
 966    uint32_t cc_vp_offset;
 967
 968    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 969                                                    sizeof(*ccv), 32,
 970                                                    &cc_vp_offset);
 971
 972    ccv->min_depth = 0.0;
 973    ccv->max_depth = 1.0;
 974
 975    BEGIN_BATCH(4);
 976    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS << 16 | (4 - 2) |
 977              GEN6_CC_VIEWPORT_MODIFY);
 978    OUT_BATCH(0); /* clip VP */
 979    OUT_BATCH(0); /* SF VP */
 980    OUT_BATCH(cc_vp_offset);
 981    ADVANCE_BATCH();
 982 }
 983
 984
 985 /* 3DPRIMITIVE */
 986 static void
 987 gen6_blorp_emit_primitive(struct brw_context *brw,
 988                           const brw_blorp_params *params)
 989 {
 990    BEGIN_BATCH(6);
 991    OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) |
 992              _3DPRIM_RECTLIST << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT |
 993              GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
 994    OUT_BATCH(3); /* vertex count per instance */
 995    OUT_BATCH(0);
 996    OUT_BATCH(1); /* instance count */
 997    OUT_BATCH(0);
 998    OUT_BATCH(0);
 999    ADVANCE_BATCH();
1000
1001    /* Only used on Sandybridge; harmless to set elsewhere. */
1002    brw->batch.need_workaround_flush = true;
1003 }
1004
1005 /**
1006  * \brief Execute a blit or render pass operation.
1007  *
1008  * To execute the operation, this function manually constructs and emits a
1009  * batch to draw a rectangle primitive. The batchbuffer is flushed before
1010  * constructing and after emitting the batch.
1011  *
1012  * This function alters no GL state.
1013  */
1014 void
1015 gen6_blorp_exec(struct brw_context *brw,
1016                 const brw_blorp_params *params)
1017 {
1018    brw_blorp_prog_data *prog_data = NULL;
1019    uint32_t cc_blend_state_offset = 0;
1020    uint32_t cc_state_offset = 0;
1021    uint32_t depthstencil_offset;
1022    uint32_t wm_push_const_offset = 0;
1023    uint32_t wm_bind_bo_offset = 0;
1024
1025    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
1026
1027    /* Emit workaround flushes when we switch from drawing to blorping. */
1028    brw->batch.need_workaround_flush = true;
1029
1030    gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
1031    gen6_emit_3dstate_sample_mask(brw,
1032                                  params->dst.num_samples > 1 ?
1033                                  (1 << params->dst.num_samples) - 1 : 1);
1034    gen6_blorp_emit_state_base_address(brw, params);
1035    gen6_blorp_emit_vertices(brw, params);
1036    gen6_blorp_emit_urb_config(brw, params);
1037    if (params->use_wm_prog) {
1038       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
1039       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
1040    }
1041    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
1042    gen6_blorp_emit_cc_state_pointers(brw, params, cc_blend_state_offset,
1043                                      depthstencil_offset, cc_state_offset);
1044    if (params->use_wm_prog) {
1045       uint32_t wm_surf_offset_renderbuffer;
1046       uint32_t wm_surf_offset_texture = 0;
1047       uint32_t sampler_offset;
1048       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
1049       intel_miptree_used_for_rendering(params->dst.mt);
1050       wm_surf_offset_renderbuffer =
1051          gen6_blorp_emit_surface_state(brw, params, &params->dst,
1052                                        I915_GEM_DOMAIN_RENDER,
1053                                        I915_GEM_DOMAIN_RENDER);
1054       if (params->src.mt) {
1055          wm_surf_offset_texture =
1056             gen6_blorp_emit_surface_state(brw, params, &params->src,
1057                                           I915_GEM_DOMAIN_SAMPLER, 0);
1058       }
1059       wm_bind_bo_offset =
1060          gen6_blorp_emit_binding_table(brw, params,
1061                                        wm_surf_offset_renderbuffer,
1062                                        wm_surf_offset_texture);
1063       sampler_offset = gen6_blorp_emit_sampler_state(brw, params);
1064       gen6_blorp_emit_sampler_state_pointers(brw, params, sampler_offset);
1065    }
1066    gen6_blorp_emit_vs_disable(brw, params);
1067    gen6_blorp_emit_gs_disable(brw, params);
1068    gen6_blorp_emit_clip_disable(brw, params);
1069    gen6_blorp_emit_sf_config(brw, params);
1070    if (params->use_wm_prog)
1071       gen6_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
1072    else
1073       gen6_blorp_emit_constant_ps_disable(brw, params);
1074    gen6_blorp_emit_wm_config(brw, params, prog_offset, prog_data);
1075    if (params->use_wm_prog)
1076       gen6_blorp_emit_binding_table_pointers(brw, params, wm_bind_bo_offset);
1077    gen6_blorp_emit_viewport_state(brw, params);
1078
1079    if (params->depth.mt)
1080       gen6_blorp_emit_depth_stencil_config(brw, params);
1081    else
1082       gen6_blorp_emit_depth_disable(brw, params);
1083    gen6_blorp_emit_clear_params(brw, params);
1084    gen6_blorp_emit_drawing_rectangle(brw, params);
1085    gen6_blorp_emit_primitive(brw, params);
1086 }
1087