2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
28 #include "intel_mipmap_tree.h"
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_state.h"
34 #include "brw_blorp.h"
35 #include "gen6_blorp.h"
38 * \name Constants for BLORP VBO
41 #define GEN6_BLORP_NUM_VERTICES 3
42 #define GEN6_BLORP_NUM_VUE_ELEMS 8
43 #define GEN6_BLORP_VBO_SIZE (GEN6_BLORP_NUM_VERTICES \
44 * GEN6_BLORP_NUM_VUE_ELEMS \
49 gen6_blorp_emit_batch_head(struct brw_context
*brw
,
50 const brw_blorp_params
*params
)
52 /* To ensure that the batch contains only the resolve, flush the batch
53 * before beginning and after finishing emitting the resolve packets.
55 intel_batchbuffer_flush(brw
);
60 * CMD_STATE_BASE_ADDRESS
62 * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS:
63 * The following commands must be reissued following any change to the
66 * 3DSTATE_BINDING_TABLE_POINTERS
67 * 3DSTATE_SAMPLER_STATE_POINTERS
68 * 3DSTATE_VIEWPORT_STATE_POINTERS
69 * MEDIA_STATE_POINTERS
72 gen6_blorp_emit_state_base_address(struct brw_context
*brw
,
73 const brw_blorp_params
*params
)
75 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
78 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
79 OUT_BATCH(mocs
<< 8 | /* GeneralStateMemoryObjectControlState */
80 mocs
<< 4 | /* StatelessDataPortAccessMemoryObjectControlState */
81 1); /* GeneralStateBaseAddressModifyEnable */
83 /* SurfaceStateBaseAddress */
84 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
85 /* DynamicStateBaseAddress */
86 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
87 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
88 OUT_BATCH(1); /* IndirectObjectBaseAddress */
89 if (params
->use_wm_prog
) {
90 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
91 1); /* Instruction base address: shader kernels */
93 OUT_BATCH(1); /* InstructionBaseAddress */
95 OUT_BATCH(1); /* GeneralStateUpperBound */
96 /* Dynamic state upper bound. Although the documentation says that
97 * programming it to zero will cause it to be ignored, that is a lie.
98 * If this isn't programmed to a real bound, the sampler border color
99 * pointer is rejected, causing border color to mysteriously fail.
101 OUT_BATCH(0xfffff001);
102 OUT_BATCH(1); /* IndirectObjectUpperBound*/
103 OUT_BATCH(1); /* InstructionAccessUpperBound */
109 gen6_blorp_emit_vertices(struct brw_context
*brw
,
110 const brw_blorp_params
*params
)
112 uint32_t vertex_offset
;
114 /* Setup VBO for the rectangle primitive..
116 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
117 * vertices. The vertices reside in screen space with DirectX coordinates
118 * (that is, (0, 0) is the upper left corner).
125 * Since the VS is disabled, the clipper loads each VUE directly from
126 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
127 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
128 * dw0: Reserved, MBZ.
129 * dw1: Render Target Array Index. The HiZ op does not use indexed
130 * vertices, so set the dword to 0.
131 * dw2: Viewport Index. The HiZ op disables viewport mapping and
132 * scissoring, so set the dword to 0.
133 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
134 * set the dword to 0.
135 * dw4: Vertex Position X.
136 * dw5: Vertex Position Y.
137 * dw6: Vertex Position Z.
138 * dw7: Vertex Position W.
140 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
141 * "Vertex URB Entry (VUE) Formats".
146 const float vertices
[GEN6_BLORP_VBO_SIZE
] = {
147 /* v0 */ 0, 0, 0, 0, (float) params
->x0
, (float) params
->y1
, 0, 1,
148 /* v1 */ 0, 0, 0, 0, (float) params
->x1
, (float) params
->y1
, 0, 1,
149 /* v2 */ 0, 0, 0, 0, (float) params
->x0
, (float) params
->y0
, 0, 1,
152 vertex_data
= (float *) brw_state_batch(brw
, AUB_TRACE_VERTEX_BUFFER
,
153 GEN6_BLORP_VBO_SIZE
, 32,
155 memcpy(vertex_data
, vertices
, GEN6_BLORP_VBO_SIZE
);
158 /* 3DSTATE_VERTEX_BUFFERS */
160 const int num_buffers
= 1;
161 const int batch_length
= 1 + 4 * num_buffers
;
163 uint32_t dw0
= GEN6_VB0_ACCESS_VERTEXDATA
|
164 (GEN6_BLORP_NUM_VUE_ELEMS
* sizeof(float)) << BRW_VB0_PITCH_SHIFT
;
167 dw0
|= GEN7_VB0_ADDRESS_MODIFYENABLE
;
170 dw0
|= GEN7_MOCS_L3
<< 16;
172 BEGIN_BATCH(batch_length
);
173 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS
<< 16) | (batch_length
- 2));
176 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
179 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
180 vertex_offset
+ GEN6_BLORP_VBO_SIZE
- 1);
185 /* 3DSTATE_VERTEX_ELEMENTS
187 * Fetch dwords 0 - 7 from each VUE. See the comments above where
188 * the vertex_bo is filled with data.
191 const int num_elements
= 2;
192 const int batch_length
= 1 + 2 * num_elements
;
194 BEGIN_BATCH(batch_length
);
195 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (batch_length
- 2));
197 OUT_BATCH(GEN6_VE0_VALID
|
198 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
199 0 << BRW_VE0_SRC_OFFSET_SHIFT
);
200 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
201 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
202 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
203 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
205 OUT_BATCH(GEN6_VE0_VALID
|
206 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
207 16 << BRW_VE0_SRC_OFFSET_SHIFT
);
208 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
209 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
210 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
211 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
219 * Assign the entire URB to the VS. Even though the VS disabled, URB space
220 * is still needed because the clipper loads the VUE's from the URB. From
221 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
222 * Dword 1.15:0 "VS Number of URB Entries":
223 * This field is always used (even if VS Function Enable is DISABLED).
225 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
226 * safely ignore it because this batch contains only one draw call.
227 * Because of URB corruption caused by allocating a previous GS unit
228 * URB entry to the VS unit, software is required to send a “GS NULL
229 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
230 * plus a dummy DRAW call before any case where VS will be taking over
234 gen6_blorp_emit_urb_config(struct brw_context
*brw
,
235 const brw_blorp_params
*params
)
238 OUT_BATCH(_3DSTATE_URB
<< 16 | (3 - 2));
239 OUT_BATCH(brw
->urb
.max_vs_entries
<< GEN6_URB_VS_ENTRIES_SHIFT
);
247 gen6_blorp_emit_blend_state(struct brw_context
*brw
,
248 const brw_blorp_params
*params
)
250 uint32_t cc_blend_state_offset
;
252 struct gen6_blend_state
*blend
= (struct gen6_blend_state
*)
253 brw_state_batch(brw
, AUB_TRACE_BLEND_STATE
,
254 sizeof(struct gen6_blend_state
), 64,
255 &cc_blend_state_offset
);
257 memset(blend
, 0, sizeof(*blend
));
259 blend
->blend1
.pre_blend_clamp_enable
= 1;
260 blend
->blend1
.post_blend_clamp_enable
= 1;
261 blend
->blend1
.clamp_range
= BRW_RENDERTARGET_CLAMPRANGE_FORMAT
;
263 blend
->blend1
.write_disable_r
= params
->color_write_disable
[0];
264 blend
->blend1
.write_disable_g
= params
->color_write_disable
[1];
265 blend
->blend1
.write_disable_b
= params
->color_write_disable
[2];
266 blend
->blend1
.write_disable_a
= params
->color_write_disable
[3];
268 /* When blitting from an XRGB source to a ARGB destination, we need to
269 * interpret the missing channel as 1.0. Blending can do that for us:
270 * we simply use the RGB values from the fragment shader ("source RGB"),
271 * but smash the alpha channel to 1.
273 if (params
->src
.mt
&&
274 _mesa_get_format_bits(params
->dst
.mt
->format
, GL_ALPHA_BITS
) > 0 &&
275 _mesa_get_format_bits(params
->src
.mt
->format
, GL_ALPHA_BITS
) == 0) {
276 blend
->blend0
.blend_enable
= 1;
277 blend
->blend0
.ia_blend_enable
= 1;
279 blend
->blend0
.blend_func
= BRW_BLENDFUNCTION_ADD
;
280 blend
->blend0
.ia_blend_func
= BRW_BLENDFUNCTION_ADD
;
282 blend
->blend0
.source_blend_factor
= BRW_BLENDFACTOR_SRC_COLOR
;
283 blend
->blend0
.dest_blend_factor
= BRW_BLENDFACTOR_ZERO
;
284 blend
->blend0
.ia_source_blend_factor
= BRW_BLENDFACTOR_ONE
;
285 blend
->blend0
.ia_dest_blend_factor
= BRW_BLENDFACTOR_ZERO
;
288 return cc_blend_state_offset
;
294 gen6_blorp_emit_cc_state(struct brw_context
*brw
,
295 const brw_blorp_params
*params
)
297 uint32_t cc_state_offset
;
299 struct gen6_color_calc_state
*cc
= (struct gen6_color_calc_state
*)
300 brw_state_batch(brw
, AUB_TRACE_CC_STATE
,
301 sizeof(gen6_color_calc_state
), 64,
303 memset(cc
, 0, sizeof(*cc
));
305 return cc_state_offset
;
310 * \param out_offset is relative to
311 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
314 gen6_blorp_emit_depth_stencil_state(struct brw_context
*brw
,
315 const brw_blorp_params
*params
)
317 uint32_t depthstencil_offset
;
319 struct gen6_depth_stencil_state
*state
;
320 state
= (struct gen6_depth_stencil_state
*)
321 brw_state_batch(brw
, AUB_TRACE_DEPTH_STENCIL_STATE
,
323 &depthstencil_offset
);
324 memset(state
, 0, sizeof(*state
));
326 /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
327 * - 7.5.3.1 Depth Buffer Clear
328 * - 7.5.3.2 Depth Buffer Resolve
329 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
331 state
->ds2
.depth_write_enable
= 1;
332 if (params
->hiz_op
== GEN6_HIZ_OP_DEPTH_RESOLVE
) {
333 state
->ds2
.depth_test_enable
= 1;
334 state
->ds2
.depth_test_func
= BRW_COMPAREFUNCTION_NEVER
;
337 return depthstencil_offset
;
341 /* 3DSTATE_CC_STATE_POINTERS
343 * The pointer offsets are relative to
344 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
346 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
349 gen6_blorp_emit_cc_state_pointers(struct brw_context
*brw
,
350 const brw_blorp_params
*params
,
351 uint32_t cc_blend_state_offset
,
352 uint32_t depthstencil_offset
,
353 uint32_t cc_state_offset
)
356 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (4 - 2));
357 OUT_BATCH(cc_blend_state_offset
| 1); /* BLEND_STATE offset */
358 OUT_BATCH(depthstencil_offset
| 1); /* DEPTH_STENCIL_STATE offset */
359 OUT_BATCH(cc_state_offset
| 1); /* COLOR_CALC_STATE offset */
364 /* WM push constants */
366 gen6_blorp_emit_wm_constants(struct brw_context
*brw
,
367 const brw_blorp_params
*params
)
369 uint32_t wm_push_const_offset
;
371 void *constants
= brw_state_batch(brw
, AUB_TRACE_WM_CONSTANTS
,
372 sizeof(params
->wm_push_consts
),
373 32, &wm_push_const_offset
);
374 memcpy(constants
, ¶ms
->wm_push_consts
,
375 sizeof(params
->wm_push_consts
));
377 return wm_push_const_offset
;
381 /* SURFACE_STATE for renderbuffer or texture surface (see
382 * brw_update_renderbuffer_surface and brw_update_texture_surface)
385 gen6_blorp_emit_surface_state(struct brw_context
*brw
,
386 const brw_blorp_params
*params
,
387 const brw_blorp_surface_info
*surface
,
388 uint32_t read_domains
, uint32_t write_domain
)
390 uint32_t wm_surf_offset
;
391 uint32_t width
= surface
->width
;
392 uint32_t height
= surface
->height
;
393 if (surface
->num_samples
> 1) {
394 /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
395 * in samples. But SURFACE_STATE wants them in pixels, so we need to
396 * divide them each by 2.
401 struct intel_region
*region
= surface
->mt
->region
;
402 uint32_t tile_x
, tile_y
;
404 uint32_t *surf
= (uint32_t *)
405 brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
408 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
409 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
410 BRW_SURFACE_CUBEFACE_ENABLES
|
411 surface
->brw_surfaceformat
<< BRW_SURFACE_FORMAT_SHIFT
);
414 surf
[1] = (surface
->compute_tile_offsets(&tile_x
, &tile_y
) +
417 surf
[2] = (0 << BRW_SURFACE_LOD_SHIFT
|
418 (width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
419 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
421 uint32_t tiling
= surface
->map_stencil_as_y_tiled
422 ? BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
423 : brw_get_surface_tiling_bits(region
->tiling
);
424 uint32_t pitch_bytes
= region
->pitch
;
425 if (surface
->map_stencil_as_y_tiled
)
428 0 << BRW_SURFACE_DEPTH_SHIFT
|
429 (pitch_bytes
- 1) << BRW_SURFACE_PITCH_SHIFT
);
431 surf
[4] = brw_get_surface_num_multisamples(surface
->num_samples
);
433 /* Note that the low bits of these fields are missing, so
434 * there's the possibility of getting in trouble.
436 assert(tile_x
% 4 == 0);
437 assert(tile_y
% 2 == 0);
438 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
439 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
440 (surface
->mt
->align_h
== 4 ?
441 BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
443 /* Emit relocation to surface contents */
444 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
447 surf
[1] - region
->bo
->offset
,
448 read_domains
, write_domain
);
450 return wm_surf_offset
;
454 /* BINDING_TABLE. See brw_wm_binding_table(). */
456 gen6_blorp_emit_binding_table(struct brw_context
*brw
,
457 const brw_blorp_params
*params
,
458 uint32_t wm_surf_offset_renderbuffer
,
459 uint32_t wm_surf_offset_texture
)
461 uint32_t wm_bind_bo_offset
;
462 uint32_t *bind
= (uint32_t *)
463 brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
465 BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
,
468 bind
[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
] =
469 wm_surf_offset_renderbuffer
;
470 bind
[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
] = wm_surf_offset_texture
;
472 return wm_bind_bo_offset
;
477 * SAMPLER_STATE. See brw_update_sampler_state().
480 gen6_blorp_emit_sampler_state(struct brw_context
*brw
,
481 const brw_blorp_params
*params
)
483 uint32_t sampler_offset
;
485 struct brw_sampler_state
*sampler
= (struct brw_sampler_state
*)
486 brw_state_batch(brw
, AUB_TRACE_SAMPLER_STATE
,
487 sizeof(struct brw_sampler_state
),
488 32, &sampler_offset
);
489 memset(sampler
, 0, sizeof(*sampler
));
491 sampler
->ss0
.min_filter
= BRW_MAPFILTER_LINEAR
;
492 sampler
->ss0
.mip_filter
= BRW_MIPFILTER_NONE
;
493 sampler
->ss0
.mag_filter
= BRW_MAPFILTER_LINEAR
;
495 sampler
->ss1
.r_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
496 sampler
->ss1
.s_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
497 sampler
->ss1
.t_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
499 sampler
->ss0
.min_mag_neq
= 1;
503 sampler
->ss0
.lod_bias
= 0;
505 sampler
->ss0
.lod_preclamp
= 1; /* OpenGL mode */
506 sampler
->ss0
.default_color_mode
= 0; /* OpenGL/DX10 mode */
508 /* Set BaseMipLevel, MaxLOD, MinLOD:
510 * XXX: I don't think that using firstLevel, lastLevel works,
511 * because we always setup the surface state as if firstLevel ==
512 * level zero. Probably have to subtract firstLevel from each of
515 sampler
->ss0
.base_level
= U_FIXED(0, 1);
517 sampler
->ss1
.max_lod
= U_FIXED(0, 6);
518 sampler
->ss1
.min_lod
= U_FIXED(0, 6);
520 sampler
->ss3
.non_normalized_coord
= 1;
522 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN
|
523 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN
|
524 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN
;
525 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG
|
526 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG
|
527 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG
;
529 return sampler_offset
;
534 * 3DSTATE_SAMPLER_STATE_POINTERS. See upload_sampler_state_pointers().
537 gen6_blorp_emit_sampler_state_pointers(struct brw_context
*brw
,
538 const brw_blorp_params
*params
,
539 uint32_t sampler_offset
)
542 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS
<< 16 |
543 VS_SAMPLER_STATE_CHANGE
|
544 GS_SAMPLER_STATE_CHANGE
|
545 PS_SAMPLER_STATE_CHANGE
|
547 OUT_BATCH(0); /* VS */
548 OUT_BATCH(0); /* GS */
549 OUT_BATCH(sampler_offset
);
556 * Disable vertex shader.
559 gen6_blorp_emit_vs_disable(struct brw_context
*brw
,
560 const brw_blorp_params
*params
)
563 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
564 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
566 * [DevSNB] A pipeline flush must be programmed prior to a
567 * 3DSTATE_VS command that causes the VS Function Enable to
568 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
569 * command with CS stall bit set and a post sync operation.
571 intel_emit_post_sync_nonzero_flush(brw
);
574 /* Disable the push constant buffers. */
576 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 | (5 - 2));
584 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
596 * Disable the geometry shader.
599 gen6_blorp_emit_gs_disable(struct brw_context
*brw
,
600 const brw_blorp_params
*params
)
602 /* Disable all the constant buffers. */
604 OUT_BATCH(_3DSTATE_CONSTANT_GS
<< 16 | (5 - 2));
612 OUT_BATCH(_3DSTATE_GS
<< 16 | (7 - 2));
625 * Disable the clipper.
627 * The BLORP op emits a rectangle primitive, which requires clipping to
628 * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
629 * Section 1.3 "3D Primitives Overview":
631 * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
632 * Mode should be set to a value other than CLIPMODE_NORMAL.
634 * Also disable perspective divide. This doesn't change the clipper's
635 * output, but does spare a few electrons.
638 gen6_blorp_emit_clip_disable(struct brw_context
*brw
,
639 const brw_blorp_params
*params
)
642 OUT_BATCH(_3DSTATE_CLIP
<< 16 | (4 - 2));
644 OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE
);
652 * Disable ViewportTransformEnable (dw2.1)
654 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
655 * Primitives Overview":
656 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
657 * use of screen- space coordinates).
659 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
660 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
662 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
663 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
664 * SOLID: Any triangle or rectangle object found to be front-facing
665 * is rendered as a solid object. This setting is required when
666 * (rendering rectangle (RECTLIST) objects.
669 gen6_blorp_emit_sf_config(struct brw_context
*brw
,
670 const brw_blorp_params
*params
)
673 OUT_BATCH(_3DSTATE_SF
<< 16 | (20 - 2));
674 OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT
| /* only position */
675 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT
|
676 0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT
);
677 OUT_BATCH(0); /* dw2 */
678 OUT_BATCH(params
->num_samples
> 1 ? GEN6_SF_MSRAST_ON_PATTERN
: 0);
679 for (int i
= 0; i
< 16; ++i
)
686 * Enable or disable thread dispatch and set the HiZ op appropriately.
689 gen6_blorp_emit_wm_config(struct brw_context
*brw
,
690 const brw_blorp_params
*params
,
691 uint32_t prog_offset
,
692 brw_blorp_prog_data
*prog_data
)
694 uint32_t dw2
, dw4
, dw5
, dw6
;
696 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
697 * nonzero to prevent the GPU from hanging. While the documentation doesn't
698 * mention this explicitly, it notes that the valid range for the field is
699 * [1,39] = [2,40] threads, which excludes zero.
701 * To be safe (and to minimize extraneous code) we go ahead and fully
702 * configure the WM state whether or not there is a WM program.
705 dw2
= dw4
= dw5
= dw6
= 0;
706 switch (params
->hiz_op
) {
707 case GEN6_HIZ_OP_DEPTH_CLEAR
:
708 dw4
|= GEN6_WM_DEPTH_CLEAR
;
710 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
711 dw4
|= GEN6_WM_DEPTH_RESOLVE
;
713 case GEN6_HIZ_OP_HIZ_RESOLVE
:
714 dw4
|= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE
;
716 case GEN6_HIZ_OP_NONE
:
722 dw5
|= GEN6_WM_LINE_AA_WIDTH_1_0
;
723 dw5
|= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5
;
724 dw5
|= (brw
->max_wm_threads
- 1) << GEN6_WM_MAX_THREADS_SHIFT
;
725 dw6
|= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
; /* No interp */
726 dw6
|= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT
; /* No inputs from SF */
727 if (params
->use_wm_prog
) {
728 dw2
|= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT
; /* Up to 4 samplers */
729 dw4
|= prog_data
->first_curbe_grf
<< GEN6_WM_DISPATCH_START_GRF_SHIFT_0
;
730 dw5
|= GEN6_WM_16_DISPATCH_ENABLE
;
731 dw5
|= GEN6_WM_KILL_ENABLE
; /* TODO: temporarily smash on */
732 dw5
|= GEN6_WM_DISPATCH_ENABLE
; /* We are rendering */
735 if (params
->num_samples
> 1) {
736 dw6
|= GEN6_WM_MSRAST_ON_PATTERN
;
737 if (prog_data
&& prog_data
->persample_msaa_dispatch
)
738 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
740 dw6
|= GEN6_WM_MSDISPMODE_PERPIXEL
;
742 dw6
|= GEN6_WM_MSRAST_OFF_PIXEL
;
743 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
747 OUT_BATCH(_3DSTATE_WM
<< 16 | (9 - 2));
748 OUT_BATCH(params
->use_wm_prog
? prog_offset
: 0);
750 OUT_BATCH(0); /* No scratch needed */
754 OUT_BATCH(0); /* No other programs */
755 OUT_BATCH(0); /* No other programs */
761 gen6_blorp_emit_constant_ps(struct brw_context
*brw
,
762 const brw_blorp_params
*params
,
763 uint32_t wm_push_const_offset
)
765 /* Make sure the push constants fill an exact integer number of
768 assert(sizeof(brw_blorp_wm_push_constants
) % 32 == 0);
770 /* There must be at least one register worth of push constant data. */
771 assert(BRW_BLORP_NUM_PUSH_CONST_REGS
> 0);
773 /* Enable push constant buffer 0. */
775 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 |
776 GEN6_CONSTANT_BUFFER_0_ENABLE
|
778 OUT_BATCH(wm_push_const_offset
+ (BRW_BLORP_NUM_PUSH_CONST_REGS
- 1));
786 gen6_blorp_emit_constant_ps_disable(struct brw_context
*brw
,
787 const brw_blorp_params
*params
)
789 /* Disable the push constant buffers. */
791 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 | (5 - 2));
800 * 3DSTATE_BINDING_TABLE_POINTERS
803 gen6_blorp_emit_binding_table_pointers(struct brw_context
*brw
,
804 const brw_blorp_params
*params
,
805 uint32_t wm_bind_bo_offset
)
808 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
809 GEN6_BINDING_TABLE_MODIFY_PS
|
811 OUT_BATCH(0); /* vs -- ignored */
812 OUT_BATCH(0); /* gs -- ignored */
813 OUT_BATCH(wm_bind_bo_offset
); /* wm/ps */
819 gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw
,
820 const brw_blorp_params
*params
)
822 struct gl_context
*ctx
= &brw
->ctx
;
823 uint32_t draw_x
= params
->depth
.x_offset
;
824 uint32_t draw_y
= params
->depth
.y_offset
;
825 uint32_t tile_mask_x
, tile_mask_y
;
827 brw_get_depthstencil_tile_masks(params
->depth
.mt
,
831 &tile_mask_x
, &tile_mask_y
);
833 /* 3DSTATE_DEPTH_BUFFER */
835 uint32_t tile_x
= draw_x
& tile_mask_x
;
836 uint32_t tile_y
= draw_y
& tile_mask_y
;
838 intel_region_get_aligned_offset(params
->depth
.mt
->region
,
839 draw_x
& ~tile_mask_x
,
840 draw_y
& ~tile_mask_y
, false);
842 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
843 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
844 * Coordinate Offset X/Y":
846 * "The 3 LSBs of both offsets must be zero to ensure correct
849 * We have no guarantee that tile_x and tile_y are correctly aligned,
850 * since they are determined by the mipmap layout, which is only aligned
853 * So, to avoid hanging the GPU, just smash the low order 3 bits of
854 * tile_x and tile_y to 0. This is a temporary workaround until we come
855 * up with a better solution.
857 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
858 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
859 "Truncating offset, bad rendering may occur.\n");
863 intel_emit_post_sync_nonzero_flush(brw
);
864 intel_emit_depth_stall_flushes(brw
);
867 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
868 OUT_BATCH((params
->depth
.mt
->region
->pitch
- 1) |
869 params
->depth_format
<< 18 |
870 1 << 21 | /* separate stencil enable */
871 1 << 22 | /* hiz enable */
872 BRW_TILEWALK_YMAJOR
<< 26 |
873 1 << 27 | /* y-tiled */
874 BRW_SURFACE_2D
<< 29);
875 OUT_RELOC(params
->depth
.mt
->region
->bo
,
876 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
878 OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1 |
879 (params
->depth
.width
+ tile_x
- 1) << 6 |
880 (params
->depth
.height
+ tile_y
- 1) << 19);
888 /* 3DSTATE_HIER_DEPTH_BUFFER */
890 struct intel_region
*hiz_region
= params
->depth
.mt
->hiz_mt
->region
;
891 uint32_t hiz_offset
=
892 intel_region_get_aligned_offset(hiz_region
,
893 draw_x
& ~tile_mask_x
,
894 (draw_y
& ~tile_mask_y
) / 2, false);
897 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
898 OUT_BATCH(hiz_region
->pitch
- 1);
899 OUT_RELOC(hiz_region
->bo
,
900 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
905 /* 3DSTATE_STENCIL_BUFFER */
908 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
917 gen6_blorp_emit_depth_disable(struct brw_context
*brw
,
918 const brw_blorp_params
*params
)
920 intel_emit_post_sync_nonzero_flush(brw
);
921 intel_emit_depth_stall_flushes(brw
);
924 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
925 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
926 (BRW_SURFACE_NULL
<< 29));
936 /* 3DSTATE_CLEAR_PARAMS
938 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
939 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
940 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
943 gen6_blorp_emit_clear_params(struct brw_context
*brw
,
944 const brw_blorp_params
*params
)
947 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
948 GEN5_DEPTH_CLEAR_VALID
|
950 OUT_BATCH(params
->depth
.mt
? params
->depth
.mt
->depth_clear_value
: 0);
955 /* 3DSTATE_DRAWING_RECTANGLE */
957 gen6_blorp_emit_drawing_rectangle(struct brw_context
*brw
,
958 const brw_blorp_params
*params
)
961 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
963 OUT_BATCH(((params
->x1
- 1) & 0xffff) |
964 ((params
->y1
- 1) << 16));
969 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
971 gen6_blorp_emit_viewport_state(struct brw_context
*brw
,
972 const brw_blorp_params
*params
)
974 struct brw_cc_viewport
*ccv
;
975 uint32_t cc_vp_offset
;
977 ccv
= (struct brw_cc_viewport
*)brw_state_batch(brw
, AUB_TRACE_CC_VP_STATE
,
981 ccv
->min_depth
= 0.0;
982 ccv
->max_depth
= 1.0;
985 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS
<< 16 | (4 - 2) |
986 GEN6_CC_VIEWPORT_MODIFY
);
987 OUT_BATCH(0); /* clip VP */
988 OUT_BATCH(0); /* SF VP */
989 OUT_BATCH(cc_vp_offset
);
996 gen6_blorp_emit_primitive(struct brw_context
*brw
,
997 const brw_blorp_params
*params
)
1000 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
1001 _3DPRIM_RECTLIST
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
1002 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
);
1003 OUT_BATCH(3); /* vertex count per instance */
1005 OUT_BATCH(1); /* instance count */
1013 * \brief Execute a blit or render pass operation.
1015 * To execute the operation, this function manually constructs and emits a
1016 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1017 * constructing and after emitting the batch.
1019 * This function alters no GL state.
1022 gen6_blorp_exec(struct brw_context
*brw
,
1023 const brw_blorp_params
*params
)
1025 brw_blorp_prog_data
*prog_data
= NULL
;
1026 uint32_t cc_blend_state_offset
= 0;
1027 uint32_t cc_state_offset
= 0;
1028 uint32_t depthstencil_offset
;
1029 uint32_t wm_push_const_offset
= 0;
1030 uint32_t wm_bind_bo_offset
= 0;
1032 uint32_t prog_offset
= params
->get_wm_prog(brw
, &prog_data
);
1033 gen6_blorp_emit_batch_head(brw
, params
);
1034 gen6_emit_3dstate_multisample(brw
, params
->num_samples
);
1035 gen6_emit_3dstate_sample_mask(brw
, params
->num_samples
, 1.0, false, ~0u);
1036 gen6_blorp_emit_state_base_address(brw
, params
);
1037 gen6_blorp_emit_vertices(brw
, params
);
1038 gen6_blorp_emit_urb_config(brw
, params
);
1039 if (params
->use_wm_prog
) {
1040 cc_blend_state_offset
= gen6_blorp_emit_blend_state(brw
, params
);
1041 cc_state_offset
= gen6_blorp_emit_cc_state(brw
, params
);
1043 depthstencil_offset
= gen6_blorp_emit_depth_stencil_state(brw
, params
);
1044 gen6_blorp_emit_cc_state_pointers(brw
, params
, cc_blend_state_offset
,
1045 depthstencil_offset
, cc_state_offset
);
1046 if (params
->use_wm_prog
) {
1047 uint32_t wm_surf_offset_renderbuffer
;
1048 uint32_t wm_surf_offset_texture
= 0;
1049 uint32_t sampler_offset
;
1050 wm_push_const_offset
= gen6_blorp_emit_wm_constants(brw
, params
);
1051 intel_miptree_used_for_rendering(params
->dst
.mt
);
1052 wm_surf_offset_renderbuffer
=
1053 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->dst
,
1054 I915_GEM_DOMAIN_RENDER
,
1055 I915_GEM_DOMAIN_RENDER
);
1056 if (params
->src
.mt
) {
1057 wm_surf_offset_texture
=
1058 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->src
,
1059 I915_GEM_DOMAIN_SAMPLER
, 0);
1062 gen6_blorp_emit_binding_table(brw
, params
,
1063 wm_surf_offset_renderbuffer
,
1064 wm_surf_offset_texture
);
1065 sampler_offset
= gen6_blorp_emit_sampler_state(brw
, params
);
1066 gen6_blorp_emit_sampler_state_pointers(brw
, params
, sampler_offset
);
1068 gen6_blorp_emit_vs_disable(brw
, params
);
1069 gen6_blorp_emit_gs_disable(brw
, params
);
1070 gen6_blorp_emit_clip_disable(brw
, params
);
1071 gen6_blorp_emit_sf_config(brw
, params
);
1072 if (params
->use_wm_prog
)
1073 gen6_blorp_emit_constant_ps(brw
, params
, wm_push_const_offset
);
1075 gen6_blorp_emit_constant_ps_disable(brw
, params
);
1076 gen6_blorp_emit_wm_config(brw
, params
, prog_offset
, prog_data
);
1077 if (params
->use_wm_prog
)
1078 gen6_blorp_emit_binding_table_pointers(brw
, params
, wm_bind_bo_offset
);
1079 gen6_blorp_emit_viewport_state(brw
, params
);
1081 if (params
->depth
.mt
)
1082 gen6_blorp_emit_depth_stencil_config(brw
, params
);
1084 gen6_blorp_emit_depth_disable(brw
, params
);
1085 gen6_blorp_emit_clear_params(brw
, params
);
1086 gen6_blorp_emit_drawing_rectangle(brw
, params
);
1087 gen6_blorp_emit_primitive(brw
, params
);