2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_mipmap_tree.h"
29 #include "brw_context.h"
30 #include "brw_state.h"
32 #include "brw_blorp.h"
35 gen6_blorp_emit_vertex_buffer_state(struct brw_context
*brw
,
38 uint32_t vertex_offset
)
40 /* 3DSTATE_VERTEX_BUFFERS */
41 const int num_buffers
= 1;
42 const int batch_length
= 1 + 4 * num_buffers
;
44 uint32_t dw0
= GEN6_VB0_ACCESS_VERTEXDATA
|
45 (num_elems
* sizeof(float)) << BRW_VB0_PITCH_SHIFT
;
48 dw0
|= GEN7_VB0_ADDRESS_MODIFYENABLE
;
52 dw0
|= GEN7_MOCS_L3
<< 16;
55 dw0
|= BDW_MOCS_WB
<< 16;
58 dw0
|= SKL_MOCS_WB
<< 16;
62 BEGIN_BATCH(batch_length
);
63 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS
<< 16) | (batch_length
- 2));
66 OUT_RELOC64(brw
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0, vertex_offset
);
70 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
73 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
74 vertex_offset
+ vbo_size
- 1);
81 gen6_blorp_emit_vertices(struct brw_context
*brw
,
82 const struct brw_blorp_params
*params
)
84 uint32_t vertex_offset
;
86 /* Setup VBO for the rectangle primitive..
88 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
89 * vertices. The vertices reside in screen space with DirectX coordinates
90 * (that is, (0, 0) is the upper left corner).
97 * Since the VS is disabled, the clipper loads each VUE directly from
98 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
99 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
100 * dw0: Reserved, MBZ.
101 * dw1: Render Target Array Index. The HiZ op does not use indexed
102 * vertices, so set the dword to 0.
103 * dw2: Viewport Index. The HiZ op disables viewport mapping and
104 * scissoring, so set the dword to 0.
105 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
106 * set the dword to 0.
107 * dw4: Vertex Position X.
108 * dw5: Vertex Position Y.
109 * dw6: Vertex Position Z.
110 * dw7: Vertex Position W.
112 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
113 * "Vertex URB Entry (VUE) Formats".
115 * Only vertex position X and Y are going to be variable, Z is fixed to
116 * zero and W to one. Header words dw0-3 are all zero. There is no need to
117 * include the fixed values in the vertex buffer. Vertex fetcher can be
118 * instructed to fill vertex elements with constant values of one and zero
119 * instead of reading them from the buffer. See the vertex element setup
125 const float vertices
[] = {
126 /* v0 */ (float)params
->x0
, (float)params
->y1
,
127 /* v1 */ (float)params
->x1
, (float)params
->y1
,
128 /* v2 */ (float)params
->x0
, (float)params
->y0
,
131 vertex_data
= (float *) brw_state_batch(brw
, AUB_TRACE_VERTEX_BUFFER
,
132 sizeof(vertices
), 32,
134 memcpy(vertex_data
, vertices
, sizeof(vertices
));
136 const unsigned blorp_num_vue_elems
= 2;
137 gen6_blorp_emit_vertex_buffer_state(brw
, blorp_num_vue_elems
,
138 sizeof(vertices
), vertex_offset
);
141 /* 3DSTATE_VERTEX_ELEMENTS
143 * Fetch dwords 0 - 7 from each VUE. See the comments above where
144 * the vertex_bo is filled with data.
147 const int num_elements
= 2;
148 const int batch_length
= 1 + 2 * num_elements
;
150 BEGIN_BATCH(batch_length
);
151 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (batch_length
- 2));
153 OUT_BATCH(GEN6_VE0_VALID
|
154 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
155 0 << BRW_VE0_SRC_OFFSET_SHIFT
);
156 OUT_BATCH(BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_0_SHIFT
|
157 BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
|
158 BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
|
159 BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_3_SHIFT
);
161 OUT_BATCH(GEN6_VE0_VALID
|
162 BRW_SURFACEFORMAT_R32G32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
163 0 << BRW_VE0_SRC_OFFSET_SHIFT
);
164 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
165 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
166 BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
|
167 BRW_VE1_COMPONENT_STORE_1_FLT
<< BRW_VE1_COMPONENT_3_SHIFT
);
175 * Assign the entire URB to the VS. Even though the VS disabled, URB space
176 * is still needed because the clipper loads the VUE's from the URB. From
177 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
178 * Dword 1.15:0 "VS Number of URB Entries":
179 * This field is always used (even if VS Function Enable is DISABLED).
181 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
182 * safely ignore it because this batch contains only one draw call.
183 * Because of URB corruption caused by allocating a previous GS unit
184 * URB entry to the VS unit, software is required to send a “GS NULL
185 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
186 * plus a dummy DRAW call before any case where VS will be taking over
190 gen6_blorp_emit_urb_config(struct brw_context
*brw
,
191 const struct brw_blorp_params
*params
)
194 OUT_BATCH(_3DSTATE_URB
<< 16 | (3 - 2));
195 OUT_BATCH(brw
->urb
.max_vs_entries
<< GEN6_URB_VS_ENTRIES_SHIFT
);
203 gen6_blorp_emit_blend_state(struct brw_context
*brw
,
204 const struct brw_blorp_params
*params
)
206 uint32_t cc_blend_state_offset
;
208 assume(params
->num_draw_buffers
);
210 const unsigned size
= params
->num_draw_buffers
*
211 sizeof(struct gen6_blend_state
);
212 struct gen6_blend_state
*blend
= (struct gen6_blend_state
*)
213 brw_state_batch(brw
, AUB_TRACE_BLEND_STATE
, size
, 64,
214 &cc_blend_state_offset
);
216 memset(blend
, 0, size
);
218 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
219 blend
[i
].blend1
.pre_blend_clamp_enable
= 1;
220 blend
[i
].blend1
.post_blend_clamp_enable
= 1;
221 blend
[i
].blend1
.clamp_range
= BRW_RENDERTARGET_CLAMPRANGE_FORMAT
;
223 blend
[i
].blend1
.write_disable_r
= params
->color_write_disable
[0];
224 blend
[i
].blend1
.write_disable_g
= params
->color_write_disable
[1];
225 blend
[i
].blend1
.write_disable_b
= params
->color_write_disable
[2];
226 blend
[i
].blend1
.write_disable_a
= params
->color_write_disable
[3];
229 return cc_blend_state_offset
;
235 gen6_blorp_emit_cc_state(struct brw_context
*brw
)
237 uint32_t cc_state_offset
;
239 struct gen6_color_calc_state
*cc
= (struct gen6_color_calc_state
*)
240 brw_state_batch(brw
, AUB_TRACE_CC_STATE
,
241 sizeof(gen6_color_calc_state
), 64,
243 memset(cc
, 0, sizeof(*cc
));
245 return cc_state_offset
;
250 * \param out_offset is relative to
251 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
254 gen6_blorp_emit_depth_stencil_state(struct brw_context
*brw
,
255 const struct brw_blorp_params
*params
)
257 uint32_t depthstencil_offset
;
259 struct gen6_depth_stencil_state
*state
;
260 state
= (struct gen6_depth_stencil_state
*)
261 brw_state_batch(brw
, AUB_TRACE_DEPTH_STENCIL_STATE
,
263 &depthstencil_offset
);
264 memset(state
, 0, sizeof(*state
));
266 /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
267 * - 7.5.3.1 Depth Buffer Clear
268 * - 7.5.3.2 Depth Buffer Resolve
269 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
271 state
->ds2
.depth_write_enable
= 1;
272 if (params
->hiz_op
== GEN6_HIZ_OP_DEPTH_RESOLVE
) {
273 state
->ds2
.depth_test_enable
= 1;
274 state
->ds2
.depth_test_func
= BRW_COMPAREFUNCTION_NEVER
;
277 return depthstencil_offset
;
281 /* 3DSTATE_CC_STATE_POINTERS
283 * The pointer offsets are relative to
284 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
286 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
289 gen6_blorp_emit_cc_state_pointers(struct brw_context
*brw
,
290 const struct brw_blorp_params
*params
,
291 uint32_t cc_blend_state_offset
,
292 uint32_t depthstencil_offset
,
293 uint32_t cc_state_offset
)
296 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (4 - 2));
297 OUT_BATCH(cc_blend_state_offset
| 1); /* BLEND_STATE offset */
298 OUT_BATCH(depthstencil_offset
| 1); /* DEPTH_STENCIL_STATE offset */
299 OUT_BATCH(cc_state_offset
| 1); /* COLOR_CALC_STATE offset */
304 /* WM push constants */
306 gen6_blorp_emit_wm_constants(struct brw_context
*brw
,
307 const struct brw_blorp_params
*params
)
309 uint32_t wm_push_const_offset
;
311 void *constants
= brw_state_batch(brw
, AUB_TRACE_WM_CONSTANTS
,
312 sizeof(params
->wm_push_consts
),
313 32, &wm_push_const_offset
);
314 memcpy(constants
, ¶ms
->wm_push_consts
,
315 sizeof(params
->wm_push_consts
));
317 return wm_push_const_offset
;
321 /* SURFACE_STATE for renderbuffer or texture surface (see
322 * brw_update_renderbuffer_surface and brw_update_texture_surface)
325 gen6_blorp_emit_surface_state(struct brw_context
*brw
,
326 const struct brw_blorp_params
*params
,
327 const struct brw_blorp_surface_info
*surface
,
328 uint32_t read_domains
, uint32_t write_domain
)
330 uint32_t wm_surf_offset
;
331 uint32_t width
= surface
->width
;
332 uint32_t height
= surface
->height
;
333 if (surface
->num_samples
> 1) {
334 /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
335 * in samples. But SURFACE_STATE wants them in pixels, so we need to
336 * divide them each by 2.
341 struct intel_mipmap_tree
*mt
= surface
->mt
;
342 uint32_t tile_x
, tile_y
;
344 uint32_t *surf
= (uint32_t *)
345 brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
348 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
349 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
350 BRW_SURFACE_CUBEFACE_ENABLES
|
351 surface
->brw_surfaceformat
<< BRW_SURFACE_FORMAT_SHIFT
);
354 surf
[1] = (brw_blorp_compute_tile_offsets(surface
, &tile_x
, &tile_y
) +
357 surf
[2] = (0 << BRW_SURFACE_LOD_SHIFT
|
358 (width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
359 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
361 uint32_t tiling
= surface
->map_stencil_as_y_tiled
362 ? BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
363 : brw_get_surface_tiling_bits(mt
->tiling
);
364 uint32_t pitch_bytes
= mt
->pitch
;
365 if (surface
->map_stencil_as_y_tiled
)
368 0 << BRW_SURFACE_DEPTH_SHIFT
|
369 (pitch_bytes
- 1) << BRW_SURFACE_PITCH_SHIFT
);
371 surf
[4] = brw_get_surface_num_multisamples(surface
->num_samples
);
373 /* Note that the low bits of these fields are missing, so
374 * there's the possibility of getting in trouble.
376 assert(tile_x
% 4 == 0);
377 assert(tile_y
% 2 == 0);
378 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
379 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
380 (surface
->mt
->valign
== 4 ?
381 BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
383 /* Emit relocation to surface contents */
384 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
387 surf
[1] - mt
->bo
->offset64
,
388 read_domains
, write_domain
);
390 return wm_surf_offset
;
394 /* BINDING_TABLE. See brw_wm_binding_table(). */
396 gen6_blorp_emit_binding_table(struct brw_context
*brw
,
397 uint32_t wm_surf_offset_renderbuffer
,
398 uint32_t wm_surf_offset_texture
)
400 uint32_t wm_bind_bo_offset
;
401 uint32_t *bind
= (uint32_t *)
402 brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
404 BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
,
407 bind
[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
] =
408 wm_surf_offset_renderbuffer
;
409 bind
[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
] = wm_surf_offset_texture
;
411 return wm_bind_bo_offset
;
416 * SAMPLER_STATE. See brw_update_sampler_state().
419 gen6_blorp_emit_sampler_state(struct brw_context
*brw
,
420 unsigned tex_filter
, unsigned max_lod
,
421 bool non_normalized_coords
)
423 uint32_t sampler_offset
;
424 uint32_t *sampler_state
= (uint32_t *)
425 brw_state_batch(brw
, AUB_TRACE_SAMPLER_STATE
, 16, 32, &sampler_offset
);
427 unsigned address_rounding
= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN
|
428 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN
|
429 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN
|
430 BRW_ADDRESS_ROUNDING_ENABLE_U_MAG
|
431 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG
|
432 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG
;
434 /* XXX: I don't think that using firstLevel, lastLevel works,
435 * because we always setup the surface state as if firstLevel ==
436 * level zero. Probably have to subtract firstLevel from each of
439 brw_emit_sampler_state(brw
,
442 tex_filter
, /* min filter */
443 tex_filter
, /* mag filter */
447 BRW_TEXCOORDMODE_CLAMP
,
448 BRW_TEXCOORDMODE_CLAMP
,
449 BRW_TEXCOORDMODE_CLAMP
,
453 0, /* shadow function */
454 non_normalized_coords
,
455 0); /* border color offset - unused */
457 return sampler_offset
;
462 * 3DSTATE_SAMPLER_STATE_POINTERS. See upload_sampler_state_pointers().
465 gen6_blorp_emit_sampler_state_pointers(struct brw_context
*brw
,
466 uint32_t sampler_offset
)
469 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS
<< 16 |
470 VS_SAMPLER_STATE_CHANGE
|
471 GS_SAMPLER_STATE_CHANGE
|
472 PS_SAMPLER_STATE_CHANGE
|
474 OUT_BATCH(0); /* VS */
475 OUT_BATCH(0); /* GS */
476 OUT_BATCH(sampler_offset
);
483 * Disable vertex shader.
486 gen6_blorp_emit_vs_disable(struct brw_context
*brw
,
487 const struct brw_blorp_params
*params
)
489 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
490 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
492 * [DevSNB] A pipeline flush must be programmed prior to a
493 * 3DSTATE_VS command that causes the VS Function Enable to
494 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
495 * command with CS stall bit set and a post sync operation.
497 * We've already done one at the start of the BLORP operation.
500 /* Disable the push constant buffers. */
502 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 | (5 - 2));
510 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
522 * Disable the geometry shader.
525 gen6_blorp_emit_gs_disable(struct brw_context
*brw
,
526 const struct brw_blorp_params
*params
)
528 /* Disable all the constant buffers. */
530 OUT_BATCH(_3DSTATE_CONSTANT_GS
<< 16 | (5 - 2));
538 OUT_BATCH(_3DSTATE_GS
<< 16 | (7 - 2));
546 brw
->gs
.enabled
= false;
552 * Disable the clipper.
554 * The BLORP op emits a rectangle primitive, which requires clipping to
555 * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
556 * Section 1.3 "3D Primitives Overview":
558 * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
559 * Mode should be set to a value other than CLIPMODE_NORMAL.
561 * Also disable perspective divide. This doesn't change the clipper's
562 * output, but does spare a few electrons.
565 gen6_blorp_emit_clip_disable(struct brw_context
*brw
)
568 OUT_BATCH(_3DSTATE_CLIP
<< 16 | (4 - 2));
570 OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE
);
578 * Disable ViewportTransformEnable (dw2.1)
580 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
581 * Primitives Overview":
582 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
583 * use of screen- space coordinates).
585 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
586 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
588 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
589 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
590 * SOLID: Any triangle or rectangle object found to be front-facing
591 * is rendered as a solid object. This setting is required when
592 * (rendering rectangle (RECTLIST) objects.
595 gen6_blorp_emit_sf_config(struct brw_context
*brw
,
596 const struct brw_blorp_params
*params
)
599 OUT_BATCH(_3DSTATE_SF
<< 16 | (20 - 2));
600 OUT_BATCH(params
->num_varyings
<< GEN6_SF_NUM_OUTPUTS_SHIFT
|
601 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT
|
602 BRW_SF_URB_ENTRY_READ_OFFSET
<<
603 GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT
);
604 OUT_BATCH(0); /* dw2 */
605 OUT_BATCH(params
->dst
.num_samples
> 1 ? GEN6_SF_MSRAST_ON_PATTERN
: 0);
606 for (int i
= 0; i
< 16; ++i
)
613 * Enable or disable thread dispatch and set the HiZ op appropriately.
616 gen6_blorp_emit_wm_config(struct brw_context
*brw
,
617 const struct brw_blorp_params
*params
)
619 const struct brw_blorp_prog_data
*prog_data
= params
->wm_prog_data
;
620 uint32_t dw2
, dw4
, dw5
, dw6
;
622 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
623 * nonzero to prevent the GPU from hanging. While the documentation doesn't
624 * mention this explicitly, it notes that the valid range for the field is
625 * [1,39] = [2,40] threads, which excludes zero.
627 * To be safe (and to minimize extraneous code) we go ahead and fully
628 * configure the WM state whether or not there is a WM program.
631 dw2
= dw4
= dw5
= dw6
= 0;
632 switch (params
->hiz_op
) {
633 case GEN6_HIZ_OP_DEPTH_CLEAR
:
634 dw4
|= GEN6_WM_DEPTH_CLEAR
;
636 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
637 dw4
|= GEN6_WM_DEPTH_RESOLVE
;
639 case GEN6_HIZ_OP_HIZ_RESOLVE
:
640 dw4
|= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE
;
642 case GEN6_HIZ_OP_NONE
:
645 unreachable("not reached");
647 dw5
|= GEN6_WM_LINE_AA_WIDTH_1_0
;
648 dw5
|= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5
;
649 dw5
|= (brw
->max_wm_threads
- 1) << GEN6_WM_MAX_THREADS_SHIFT
;
650 dw6
|= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
; /* No interp */
651 dw6
|= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT
; /* No inputs from SF */
652 if (params
->wm_prog_data
) {
653 dw4
|= prog_data
->first_curbe_grf
<< GEN6_WM_DISPATCH_START_GRF_SHIFT_0
;
654 dw5
|= GEN6_WM_16_DISPATCH_ENABLE
;
655 dw5
|= GEN6_WM_DISPATCH_ENABLE
; /* We are rendering */
658 if (params
->src
.mt
) {
659 dw5
|= GEN6_WM_KILL_ENABLE
; /* TODO: temporarily smash on */
660 dw2
|= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT
; /* Up to 4 samplers */
663 if (params
->dst
.num_samples
> 1) {
664 dw6
|= GEN6_WM_MSRAST_ON_PATTERN
;
665 if (prog_data
&& prog_data
->persample_msaa_dispatch
)
666 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
668 dw6
|= GEN6_WM_MSDISPMODE_PERPIXEL
;
670 dw6
|= GEN6_WM_MSRAST_OFF_PIXEL
;
671 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
675 OUT_BATCH(_3DSTATE_WM
<< 16 | (9 - 2));
676 OUT_BATCH(params
->wm_prog_kernel
);
678 OUT_BATCH(0); /* No scratch needed */
682 OUT_BATCH(0); /* No other programs */
683 OUT_BATCH(0); /* No other programs */
689 gen6_blorp_emit_constant_ps(struct brw_context
*brw
,
690 const struct brw_blorp_params
*params
,
691 uint32_t wm_push_const_offset
)
693 /* Make sure the push constants fill an exact integer number of
696 assert(sizeof(struct brw_blorp_wm_push_constants
) % 32 == 0);
698 /* There must be at least one register worth of push constant data. */
699 assert(BRW_BLORP_NUM_PUSH_CONST_REGS
> 0);
701 /* Enable push constant buffer 0. */
703 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 |
704 GEN6_CONSTANT_BUFFER_0_ENABLE
|
706 OUT_BATCH(wm_push_const_offset
+ (BRW_BLORP_NUM_PUSH_CONST_REGS
- 1));
714 gen6_blorp_emit_constant_ps_disable(struct brw_context
*brw
,
715 const struct brw_blorp_params
*params
)
717 /* Disable the push constant buffers. */
719 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 | (5 - 2));
728 * 3DSTATE_BINDING_TABLE_POINTERS
731 gen6_blorp_emit_binding_table_pointers(struct brw_context
*brw
,
732 uint32_t wm_bind_bo_offset
)
735 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
736 GEN6_BINDING_TABLE_MODIFY_PS
|
738 OUT_BATCH(0); /* vs -- ignored */
739 OUT_BATCH(0); /* gs -- ignored */
740 OUT_BATCH(wm_bind_bo_offset
); /* wm/ps */
746 gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw
,
747 const struct brw_blorp_params
*params
)
749 uint32_t surfwidth
, surfheight
;
751 unsigned int depth
= MAX2(params
->depth
.mt
->logical_depth0
, 1);
752 GLenum gl_target
= params
->depth
.mt
->target
;
756 case GL_TEXTURE_CUBE_MAP_ARRAY
:
757 case GL_TEXTURE_CUBE_MAP
:
758 /* The PRM claims that we should use BRW_SURFACE_CUBE for this
759 * situation, but experiments show that gl_Layer doesn't work when we do
760 * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
763 surftype
= BRW_SURFACE_2D
;
767 surftype
= translate_tex_target(gl_target
);
771 const unsigned min_array_element
= params
->depth
.layer
;
773 lod
= params
->depth
.level
- params
->depth
.mt
->first_level
;
775 if (params
->hiz_op
!= GEN6_HIZ_OP_NONE
&& lod
== 0) {
776 /* HIZ ops for lod 0 may set the width & height a little
777 * larger to allow the fast depth clear to fit the hardware
778 * alignment requirements. (8x4)
780 surfwidth
= params
->depth
.width
;
781 surfheight
= params
->depth
.height
;
783 surfwidth
= params
->depth
.mt
->logical_width0
;
784 surfheight
= params
->depth
.mt
->logical_height0
;
787 /* 3DSTATE_DEPTH_BUFFER */
789 brw_emit_depth_stall_flushes(brw
);
792 /* 3DSTATE_DEPTH_BUFFER dw0 */
793 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
795 /* 3DSTATE_DEPTH_BUFFER dw1 */
796 OUT_BATCH((params
->depth
.mt
->pitch
- 1) |
797 params
->depth_format
<< 18 |
798 1 << 21 | /* separate stencil enable */
799 1 << 22 | /* hiz enable */
800 BRW_TILEWALK_YMAJOR
<< 26 |
801 1 << 27 | /* y-tiled */
804 /* 3DSTATE_DEPTH_BUFFER dw2 */
805 OUT_RELOC(params
->depth
.mt
->bo
,
806 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
809 /* 3DSTATE_DEPTH_BUFFER dw3 */
810 OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1 |
811 (surfwidth
- 1) << 6 |
812 (surfheight
- 1) << 19 |
815 /* 3DSTATE_DEPTH_BUFFER dw4 */
816 OUT_BATCH((depth
- 1) << 21 |
817 min_array_element
<< 10 |
820 /* 3DSTATE_DEPTH_BUFFER dw5 */
823 /* 3DSTATE_DEPTH_BUFFER dw6 */
828 /* 3DSTATE_HIER_DEPTH_BUFFER */
830 struct intel_mipmap_tree
*hiz_mt
= params
->depth
.mt
->hiz_buf
->mt
;
833 if (hiz_mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
834 offset
= intel_miptree_get_aligned_offset(hiz_mt
,
835 hiz_mt
->level
[lod
].level_x
,
836 hiz_mt
->level
[lod
].level_y
,
841 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
842 OUT_BATCH(hiz_mt
->pitch
- 1);
843 OUT_RELOC(hiz_mt
->bo
,
844 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
849 /* 3DSTATE_STENCIL_BUFFER */
852 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
861 gen6_blorp_emit_depth_disable(struct brw_context
*brw
,
862 const struct brw_blorp_params
*params
)
864 brw_emit_depth_stall_flushes(brw
);
867 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
868 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
869 (BRW_SURFACE_NULL
<< 29));
878 OUT_BATCH(_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (3 - 2));
884 OUT_BATCH(_3DSTATE_STENCIL_BUFFER
<< 16 | (3 - 2));
891 /* 3DSTATE_CLEAR_PARAMS
893 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
894 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
895 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
898 gen6_blorp_emit_clear_params(struct brw_context
*brw
,
899 const struct brw_blorp_params
*params
)
902 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
903 GEN5_DEPTH_CLEAR_VALID
|
905 OUT_BATCH(params
->depth
.mt
? params
->depth
.mt
->depth_clear_value
: 0);
910 /* 3DSTATE_DRAWING_RECTANGLE */
912 gen6_blorp_emit_drawing_rectangle(struct brw_context
*brw
,
913 const struct brw_blorp_params
*params
)
916 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
918 OUT_BATCH(((MAX2(params
->x1
, params
->x0
) - 1) & 0xffff) |
919 ((MAX2(params
->y1
, params
->y0
) - 1) << 16));
924 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
926 gen6_blorp_emit_viewport_state(struct brw_context
*brw
,
927 const struct brw_blorp_params
*params
)
929 struct brw_cc_viewport
*ccv
;
930 uint32_t cc_vp_offset
;
932 ccv
= (struct brw_cc_viewport
*)brw_state_batch(brw
, AUB_TRACE_CC_VP_STATE
,
936 ccv
->min_depth
= 0.0;
937 ccv
->max_depth
= 1.0;
940 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS
<< 16 | (4 - 2) |
941 GEN6_CC_VIEWPORT_MODIFY
);
942 OUT_BATCH(0); /* clip VP */
943 OUT_BATCH(0); /* SF VP */
944 OUT_BATCH(cc_vp_offset
);
951 gen6_blorp_emit_primitive(struct brw_context
*brw
,
952 const struct brw_blorp_params
*params
)
955 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
956 _3DPRIM_RECTLIST
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
957 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
);
958 OUT_BATCH(3); /* vertex count per instance */
960 OUT_BATCH(params
->num_layers
); /* instance count */
967 * \brief Execute a blit or render pass operation.
969 * To execute the operation, this function manually constructs and emits a
970 * batch to draw a rectangle primitive. The batchbuffer is flushed before
971 * constructing and after emitting the batch.
973 * This function alters no GL state.
976 gen6_blorp_exec(struct brw_context
*brw
,
977 const struct brw_blorp_params
*params
)
979 uint32_t cc_blend_state_offset
= 0;
980 uint32_t cc_state_offset
= 0;
981 uint32_t depthstencil_offset
;
982 uint32_t wm_push_const_offset
= 0;
983 uint32_t wm_bind_bo_offset
= 0;
985 /* Emit workaround flushes when we switch from drawing to blorping. */
986 brw_emit_post_sync_nonzero_flush(brw
);
988 if (brw_state_base_address
.dirty
.brw
& brw
->ctx
.NewDriverState
)
989 brw_state_base_address
.emit(brw
);
991 gen6_emit_3dstate_multisample(brw
, params
->dst
.num_samples
);
992 gen6_emit_3dstate_sample_mask(brw
,
993 params
->dst
.num_samples
> 1 ?
994 (1 << params
->dst
.num_samples
) - 1 : 1);
995 gen6_blorp_emit_vertices(brw
, params
);
996 gen6_blorp_emit_urb_config(brw
, params
);
997 if (params
->wm_prog_data
) {
998 cc_blend_state_offset
= gen6_blorp_emit_blend_state(brw
, params
);
999 cc_state_offset
= gen6_blorp_emit_cc_state(brw
);
1001 depthstencil_offset
= gen6_blorp_emit_depth_stencil_state(brw
, params
);
1002 gen6_blorp_emit_cc_state_pointers(brw
, params
, cc_blend_state_offset
,
1003 depthstencil_offset
, cc_state_offset
);
1004 if (params
->wm_prog_data
) {
1005 uint32_t wm_surf_offset_renderbuffer
;
1006 uint32_t wm_surf_offset_texture
= 0;
1007 wm_push_const_offset
= gen6_blorp_emit_wm_constants(brw
, params
);
1008 intel_miptree_used_for_rendering(params
->dst
.mt
);
1009 wm_surf_offset_renderbuffer
=
1010 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->dst
,
1011 I915_GEM_DOMAIN_RENDER
,
1012 I915_GEM_DOMAIN_RENDER
);
1013 if (params
->src
.mt
) {
1014 wm_surf_offset_texture
=
1015 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->src
,
1016 I915_GEM_DOMAIN_SAMPLER
, 0);
1019 gen6_blorp_emit_binding_table(brw
,
1020 wm_surf_offset_renderbuffer
,
1021 wm_surf_offset_texture
);
1024 if (params
->src
.mt
) {
1025 const uint32_t sampler_offset
=
1026 gen6_blorp_emit_sampler_state(brw
, BRW_MAPFILTER_LINEAR
, 0, true);
1027 gen6_blorp_emit_sampler_state_pointers(brw
, sampler_offset
);
1029 gen6_blorp_emit_vs_disable(brw
, params
);
1030 gen6_blorp_emit_gs_disable(brw
, params
);
1031 gen6_blorp_emit_clip_disable(brw
);
1032 gen6_blorp_emit_sf_config(brw
, params
);
1033 if (params
->wm_prog_data
)
1034 gen6_blorp_emit_constant_ps(brw
, params
, wm_push_const_offset
);
1036 gen6_blorp_emit_constant_ps_disable(brw
, params
);
1037 gen6_blorp_emit_wm_config(brw
, params
);
1038 if (params
->wm_prog_data
)
1039 gen6_blorp_emit_binding_table_pointers(brw
, wm_bind_bo_offset
);
1040 gen6_blorp_emit_viewport_state(brw
, params
);
1042 if (params
->depth
.mt
)
1043 gen6_blorp_emit_depth_stencil_config(brw
, params
);
1045 gen6_blorp_emit_depth_disable(brw
, params
);
1046 gen6_blorp_emit_clear_params(brw
, params
);
1047 gen6_blorp_emit_drawing_rectangle(brw
, params
);
1048 gen6_blorp_emit_primitive(brw
, params
);