2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
28 #include "intel_mipmap_tree.h"
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_state.h"
34 #include "brw_blorp.h"
35 #include "gen6_blorp.h"
38 * \name Constants for BLORP VBO
41 #define GEN6_BLORP_NUM_VERTICES 3
42 #define GEN6_BLORP_NUM_VUE_ELEMS 8
43 #define GEN6_BLORP_VBO_SIZE (GEN6_BLORP_NUM_VERTICES \
44 * GEN6_BLORP_NUM_VUE_ELEMS \
50 * Compute masks to determine how much of draw_x and draw_y should be
51 * performed using the fine adjustment of "depth coordinate offset X/Y"
52 * (dw5 of 3DSTATE_DEPTH_BUFFER). See the emit_depthbuffer() function for
56 gen6_blorp_compute_tile_masks(const brw_blorp_params
*params
,
57 uint32_t *tile_mask_x
, uint32_t *tile_mask_y
)
59 uint32_t depth_mask_x
, depth_mask_y
, hiz_mask_x
, hiz_mask_y
;
60 intel_region_get_tile_masks(params
->depth
.mt
->region
,
61 &depth_mask_x
, &depth_mask_y
);
62 intel_region_get_tile_masks(params
->depth
.mt
->hiz_mt
->region
,
63 &hiz_mask_x
, &hiz_mask_y
);
65 /* Each HiZ row represents 2 rows of pixels */
66 hiz_mask_y
= hiz_mask_y
<< 1 | 1;
68 *tile_mask_x
= depth_mask_x
| hiz_mask_x
;
69 *tile_mask_y
= depth_mask_y
| hiz_mask_y
;
74 gen6_blorp_emit_batch_head(struct brw_context
*brw
,
75 const brw_blorp_params
*params
)
77 struct gl_context
*ctx
= &brw
->intel
.ctx
;
78 struct intel_context
*intel
= &brw
->intel
;
80 /* To ensure that the batch contains only the resolve, flush the batch
81 * before beginning and after finishing emitting the resolve packets.
83 * Ideally, we would not need to flush for the resolve op. But, I suspect
84 * that it's unsafe for CMD_PIPELINE_SELECT to occur multiple times in
85 * a single batch, and there is no safe way to ensure that other than by
86 * fencing the resolve with flushes. Ideally, we would just detect if
87 * a batch is in progress and do the right thing, but that would require
88 * the ability to *safely* access brw_context::state::dirty::brw
89 * outside of the brw_upload_state() codepath.
93 /* CMD_PIPELINE_SELECT
95 * Select the 3D pipeline, as opposed to the media pipeline.
99 OUT_BATCH(brw
->CMD_PIPELINE_SELECT
<< 16);
106 * CMD_STATE_BASE_ADDRESS
108 * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS:
109 * The following commands must be reissued following any change to the
111 * 3DSTATE_CC_POINTERS
112 * 3DSTATE_BINDING_TABLE_POINTERS
113 * 3DSTATE_SAMPLER_STATE_POINTERS
114 * 3DSTATE_VIEWPORT_STATE_POINTERS
115 * MEDIA_STATE_POINTERS
118 gen6_blorp_emit_state_base_address(struct brw_context
*brw
,
119 const brw_blorp_params
*params
)
121 struct intel_context
*intel
= &brw
->intel
;
124 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
125 OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */
126 /* SurfaceStateBaseAddress */
127 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
128 /* DynamicStateBaseAddress */
129 OUT_RELOC(intel
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
130 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
131 OUT_BATCH(1); /* IndirectObjectBaseAddress */
132 if (params
->use_wm_prog
) {
133 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
134 1); /* Instruction base address: shader kernels */
136 OUT_BATCH(1); /* InstructionBaseAddress */
138 OUT_BATCH(1); /* GeneralStateUpperBound */
139 /* Dynamic state upper bound. Although the documentation says that
140 * programming it to zero will cause it to be ignored, that is a lie.
141 * If this isn't programmed to a real bound, the sampler border color
142 * pointer is rejected, causing border color to mysteriously fail.
144 OUT_BATCH(0xfffff001);
145 OUT_BATCH(1); /* IndirectObjectUpperBound*/
146 OUT_BATCH(1); /* InstructionAccessUpperBound */
152 gen6_blorp_emit_vertices(struct brw_context
*brw
,
153 const brw_blorp_params
*params
)
155 struct intel_context
*intel
= &brw
->intel
;
156 uint32_t vertex_offset
;
158 /* Setup VBO for the rectangle primitive..
160 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
161 * vertices. The vertices reside in screen space with DirectX coordinates
162 * (that is, (0, 0) is the upper left corner).
169 * Since the VS is disabled, the clipper loads each VUE directly from
170 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
171 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
172 * dw0: Reserved, MBZ.
173 * dw1: Render Target Array Index. The HiZ op does not use indexed
174 * vertices, so set the dword to 0.
175 * dw2: Viewport Index. The HiZ op disables viewport mapping and
176 * scissoring, so set the dword to 0.
177 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
178 * set the dword to 0.
179 * dw4: Vertex Position X.
180 * dw5: Vertex Position Y.
181 * dw6: Vertex Position Z.
182 * dw7: Vertex Position W.
184 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
185 * "Vertex URB Entry (VUE) Formats".
190 const float vertices
[GEN6_BLORP_VBO_SIZE
] = {
191 /* v0 */ 0, 0, 0, 0, params
->x0
, params
->y1
, 0, 1,
192 /* v1 */ 0, 0, 0, 0, params
->x1
, params
->y1
, 0, 1,
193 /* v2 */ 0, 0, 0, 0, params
->x0
, params
->y0
, 0, 1,
196 vertex_data
= (float *) brw_state_batch(brw
, AUB_TRACE_VERTEX_BUFFER
,
197 GEN6_BLORP_VBO_SIZE
, 32,
199 memcpy(vertex_data
, vertices
, GEN6_BLORP_VBO_SIZE
);
202 /* 3DSTATE_VERTEX_BUFFERS */
204 const int num_buffers
= 1;
205 const int batch_length
= 1 + 4 * num_buffers
;
207 uint32_t dw0
= GEN6_VB0_ACCESS_VERTEXDATA
|
208 (GEN6_BLORP_NUM_VUE_ELEMS
* sizeof(float)) << BRW_VB0_PITCH_SHIFT
;
211 dw0
|= GEN7_VB0_ADDRESS_MODIFYENABLE
;
213 BEGIN_BATCH(batch_length
);
214 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS
<< 16) | (batch_length
- 2));
217 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
220 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
221 vertex_offset
+ GEN6_BLORP_VBO_SIZE
- 1);
226 /* 3DSTATE_VERTEX_ELEMENTS
228 * Fetch dwords 0 - 7 from each VUE. See the comments above where
229 * the vertex_bo is filled with data.
232 const int num_elements
= 2;
233 const int batch_length
= 1 + 2 * num_elements
;
235 BEGIN_BATCH(batch_length
);
236 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (batch_length
- 2));
238 OUT_BATCH(GEN6_VE0_VALID
|
239 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
240 0 << BRW_VE0_SRC_OFFSET_SHIFT
);
241 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
242 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
243 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
244 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
246 OUT_BATCH(GEN6_VE0_VALID
|
247 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
248 16 << BRW_VE0_SRC_OFFSET_SHIFT
);
249 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
250 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
251 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
252 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
260 * Assign the entire URB to the VS. Even though the VS disabled, URB space
261 * is still needed because the clipper loads the VUE's from the URB. From
262 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
263 * Dword 1.15:0 "VS Number of URB Entries":
264 * This field is always used (even if VS Function Enable is DISABLED).
266 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
267 * safely ignore it because this batch contains only one draw call.
268 * Because of URB corruption caused by allocating a previous GS unit
269 * URB entry to the VS unit, software is required to send a “GS NULL
270 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
271 * plus a dummy DRAW call before any case where VS will be taking over
275 gen6_blorp_emit_urb_config(struct brw_context
*brw
,
276 const brw_blorp_params
*params
)
278 struct intel_context
*intel
= &brw
->intel
;
281 OUT_BATCH(_3DSTATE_URB
<< 16 | (3 - 2));
282 OUT_BATCH(brw
->urb
.max_vs_entries
<< GEN6_URB_VS_ENTRIES_SHIFT
);
290 gen6_blorp_emit_blend_state(struct brw_context
*brw
,
291 const brw_blorp_params
*params
)
293 uint32_t cc_blend_state_offset
;
295 struct gen6_blend_state
*blend
= (struct gen6_blend_state
*)
296 brw_state_batch(brw
, AUB_TRACE_BLEND_STATE
,
297 sizeof(struct gen6_blend_state
), 64,
298 &cc_blend_state_offset
);
300 memset(blend
, 0, sizeof(*blend
));
302 // TODO: handle other formats.
303 blend
->blend1
.pre_blend_clamp_enable
= 1;
304 blend
->blend1
.post_blend_clamp_enable
= 1;
305 blend
->blend1
.clamp_range
= BRW_RENDERTARGET_CLAMPRANGE_FORMAT
;
307 blend
->blend1
.write_disable_r
= false;
308 blend
->blend1
.write_disable_g
= false;
309 blend
->blend1
.write_disable_b
= false;
310 blend
->blend1
.write_disable_a
= false;
312 return cc_blend_state_offset
;
318 gen6_blorp_emit_cc_state(struct brw_context
*brw
,
319 const brw_blorp_params
*params
)
321 uint32_t cc_state_offset
;
323 struct gen6_color_calc_state
*cc
= (struct gen6_color_calc_state
*)
324 brw_state_batch(brw
, AUB_TRACE_CC_STATE
,
325 sizeof(gen6_color_calc_state
), 64,
327 memset(cc
, 0, sizeof(*cc
));
329 return cc_state_offset
;
334 * \param out_offset is relative to
335 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
338 gen6_blorp_emit_depth_stencil_state(struct brw_context
*brw
,
339 const brw_blorp_params
*params
)
341 uint32_t depthstencil_offset
;
343 struct gen6_depth_stencil_state
*state
;
344 state
= (struct gen6_depth_stencil_state
*)
345 brw_state_batch(brw
, AUB_TRACE_DEPTH_STENCIL_STATE
,
347 &depthstencil_offset
);
348 memset(state
, 0, sizeof(*state
));
350 /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
351 * - 7.5.3.1 Depth Buffer Clear
352 * - 7.5.3.2 Depth Buffer Resolve
353 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
355 state
->ds2
.depth_write_enable
= 1;
356 if (params
->hiz_op
== GEN6_HIZ_OP_DEPTH_RESOLVE
) {
357 state
->ds2
.depth_test_enable
= 1;
358 state
->ds2
.depth_test_func
= COMPAREFUNC_NEVER
;
361 return depthstencil_offset
;
365 /* 3DSTATE_CC_STATE_POINTERS
367 * The pointer offsets are relative to
368 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
370 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
373 gen6_blorp_emit_cc_state_pointers(struct brw_context
*brw
,
374 const brw_blorp_params
*params
,
375 uint32_t cc_blend_state_offset
,
376 uint32_t depthstencil_offset
,
377 uint32_t cc_state_offset
)
379 struct intel_context
*intel
= &brw
->intel
;
382 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (4 - 2));
383 OUT_BATCH(cc_blend_state_offset
| 1); /* BLEND_STATE offset */
384 OUT_BATCH(depthstencil_offset
| 1); /* DEPTH_STENCIL_STATE offset */
385 OUT_BATCH(cc_state_offset
| 1); /* COLOR_CALC_STATE offset */
390 /* WM push constants */
392 gen6_blorp_emit_wm_constants(struct brw_context
*brw
,
393 const brw_blorp_params
*params
)
395 uint32_t wm_push_const_offset
;
397 void *constants
= brw_state_batch(brw
, AUB_TRACE_WM_CONSTANTS
,
398 sizeof(params
->wm_push_consts
),
399 32, &wm_push_const_offset
);
400 memcpy(constants
, ¶ms
->wm_push_consts
,
401 sizeof(params
->wm_push_consts
));
403 return wm_push_const_offset
;
407 /* SURFACE_STATE for renderbuffer or texture surface (see
408 * brw_update_renderbuffer_surface and brw_update_texture_surface)
411 gen6_blorp_emit_surface_state(struct brw_context
*brw
,
412 const brw_blorp_params
*params
,
413 const brw_blorp_surface_info
*surface
,
414 uint32_t read_domains
, uint32_t write_domain
)
416 uint32_t wm_surf_offset
;
417 uint32_t width
, height
;
418 surface
->get_miplevel_dims(&width
, &height
);
419 if (surface
->num_samples
> 0) { /* TODO: seems clumsy */
423 if (surface
->map_stencil_as_y_tiled
) {
427 struct intel_region
*region
= surface
->mt
->region
;
429 uint32_t *surf
= (uint32_t *)
430 brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
433 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
434 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
435 BRW_SURFACE_CUBEFACE_ENABLES
|
436 surface
->brw_surfaceformat
<< BRW_SURFACE_FORMAT_SHIFT
);
439 surf
[1] = region
->bo
->offset
; /* No tile offsets needed */
441 surf
[2] = (0 << BRW_SURFACE_LOD_SHIFT
|
442 (width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
443 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
445 uint32_t tiling
= surface
->map_stencil_as_y_tiled
446 ? BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
447 : brw_get_surface_tiling_bits(region
->tiling
);
448 uint32_t pitch_bytes
= region
->pitch
* region
->cpp
;
449 if (surface
->map_stencil_as_y_tiled
)
452 0 << BRW_SURFACE_DEPTH_SHIFT
|
453 (pitch_bytes
- 1) << BRW_SURFACE_PITCH_SHIFT
);
455 surf
[4] = brw_get_surface_num_multisamples(surface
->num_samples
);
457 surf
[5] = (0 << BRW_SURFACE_X_OFFSET_SHIFT
|
458 0 << BRW_SURFACE_Y_OFFSET_SHIFT
|
459 (surface
->mt
->align_h
== 4 ?
460 BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
462 /* Emit relocation to surface contents */
463 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
466 surf
[1] - region
->bo
->offset
,
467 read_domains
, write_domain
);
469 return wm_surf_offset
;
473 /* BINDING_TABLE. See brw_wm_binding_table(). */
475 gen6_blorp_emit_binding_table(struct brw_context
*brw
,
476 const brw_blorp_params
*params
,
477 uint32_t wm_surf_offset_renderbuffer
,
478 uint32_t wm_surf_offset_texture
)
480 uint32_t wm_bind_bo_offset
;
481 uint32_t *bind
= (uint32_t *)
482 brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
484 BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
,
487 bind
[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
] =
488 wm_surf_offset_renderbuffer
;
489 bind
[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
] = wm_surf_offset_texture
;
491 return wm_bind_bo_offset
;
496 * SAMPLER_STATE. See brw_update_sampler_state().
499 gen6_blorp_emit_sampler_state(struct brw_context
*brw
,
500 const brw_blorp_params
*params
)
502 uint32_t sampler_offset
;
504 struct brw_sampler_state
*sampler
= (struct brw_sampler_state
*)
505 brw_state_batch(brw
, AUB_TRACE_SAMPLER_STATE
,
506 sizeof(struct brw_sampler_state
),
507 32, &sampler_offset
);
508 memset(sampler
, 0, sizeof(*sampler
));
510 sampler
->ss0
.min_filter
= BRW_MAPFILTER_LINEAR
;
511 sampler
->ss0
.mip_filter
= BRW_MIPFILTER_NONE
;
512 sampler
->ss0
.mag_filter
= BRW_MAPFILTER_LINEAR
;
514 sampler
->ss1
.r_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
515 sampler
->ss1
.s_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
516 sampler
->ss1
.t_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
518 sampler
->ss0
.min_mag_neq
= 1;
522 sampler
->ss0
.lod_bias
= 0;
524 sampler
->ss0
.lod_preclamp
= 1; /* OpenGL mode */
525 sampler
->ss0
.default_color_mode
= 0; /* OpenGL/DX10 mode */
527 /* Set BaseMipLevel, MaxLOD, MinLOD:
529 * XXX: I don't think that using firstLevel, lastLevel works,
530 * because we always setup the surface state as if firstLevel ==
531 * level zero. Probably have to subtract firstLevel from each of
534 sampler
->ss0
.base_level
= U_FIXED(0, 1);
536 sampler
->ss1
.max_lod
= U_FIXED(0, 6);
537 sampler
->ss1
.min_lod
= U_FIXED(0, 6);
539 sampler
->ss3
.non_normalized_coord
= 1;
541 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN
|
542 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN
|
543 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN
;
544 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG
|
545 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG
|
546 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG
;
548 return sampler_offset
;
553 * 3DSTATE_SAMPLER_STATE_POINTERS. See upload_sampler_state_pointers().
556 gen6_blorp_emit_sampler_state_pointers(struct brw_context
*brw
,
557 const brw_blorp_params
*params
,
558 uint32_t sampler_offset
)
560 struct intel_context
*intel
= &brw
->intel
;
563 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS
<< 16 |
564 VS_SAMPLER_STATE_CHANGE
|
565 GS_SAMPLER_STATE_CHANGE
|
566 PS_SAMPLER_STATE_CHANGE
|
568 OUT_BATCH(0); /* VS */
569 OUT_BATCH(0); /* GS */
570 OUT_BATCH(sampler_offset
);
577 * Disable vertex shader.
580 gen6_blorp_emit_vs_disable(struct brw_context
*brw
,
581 const brw_blorp_params
*params
)
583 struct intel_context
*intel
= &brw
->intel
;
585 if (intel
->gen
== 6) {
586 /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section
587 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
589 * [DevSNB] A pipeline flush must be programmed prior to a
590 * 3DSTATE_VS command that causes the VS Function Enable to
591 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
592 * command with CS stall bit set and a post sync operation.
594 intel_emit_post_sync_nonzero_flush(intel
);
598 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
610 * Disable the geometry shader.
613 gen6_blorp_emit_gs_disable(struct brw_context
*brw
,
614 const brw_blorp_params
*params
)
616 struct intel_context
*intel
= &brw
->intel
;
619 OUT_BATCH(_3DSTATE_GS
<< 16 | (7 - 2));
632 * Disable the clipper.
634 * The BLORP op emits a rectangle primitive, which requires clipping to
635 * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
636 * Section 1.3 "3D Primitives Overview":
638 * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
639 * Mode should be set to a value other than CLIPMODE_NORMAL.
641 * Also disable perspective divide. This doesn't change the clipper's
642 * output, but does spare a few electrons.
645 gen6_blorp_emit_clip_disable(struct brw_context
*brw
,
646 const brw_blorp_params
*params
)
648 struct intel_context
*intel
= &brw
->intel
;
651 OUT_BATCH(_3DSTATE_CLIP
<< 16 | (4 - 2));
653 OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE
);
661 * Disable ViewportTransformEnable (dw2.1)
663 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
664 * Primitives Overview":
665 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
666 * use of screen- space coordinates).
668 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
669 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
671 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
672 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
673 * SOLID: Any triangle or rectangle object found to be front-facing
674 * is rendered as a solid object. This setting is required when
675 * (rendering rectangle (RECTLIST) objects.
678 gen6_blorp_emit_sf_config(struct brw_context
*brw
,
679 const brw_blorp_params
*params
)
681 struct intel_context
*intel
= &brw
->intel
;
684 OUT_BATCH(_3DSTATE_SF
<< 16 | (20 - 2));
685 OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT
| /* only position */
686 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT
|
687 0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT
);
688 OUT_BATCH(0); /* dw2 */
689 OUT_BATCH(params
->num_samples
> 0 ? GEN6_SF_MSRAST_ON_PATTERN
: 0);
690 for (int i
= 0; i
< 16; ++i
)
697 * Enable or disable thread dispatch and set the HiZ op appropriately.
700 gen6_blorp_emit_wm_config(struct brw_context
*brw
,
701 const brw_blorp_params
*params
,
702 uint32_t prog_offset
,
703 brw_blorp_prog_data
*prog_data
)
705 struct intel_context
*intel
= &brw
->intel
;
706 uint32_t dw2
, dw4
, dw5
, dw6
;
708 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
709 * nonzero to prevent the GPU from hanging. See the valid ranges in the
710 * BSpec, Volume 2a.11 Windower, Section 3DSTATE_WM, Dword 5.25:31
711 * "Maximum Number Of Threads".
713 * To be safe (and to minimize extraneous code) we go ahead and fully
714 * configure the WM state whether or not there is a WM program.
717 dw2
= dw4
= dw5
= dw6
= 0;
718 switch (params
->hiz_op
) {
719 case GEN6_HIZ_OP_DEPTH_CLEAR
:
720 dw4
|= GEN6_WM_DEPTH_CLEAR
;
722 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
723 dw4
|= GEN6_WM_DEPTH_RESOLVE
;
725 case GEN6_HIZ_OP_HIZ_RESOLVE
:
726 dw4
|= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE
;
728 case GEN6_HIZ_OP_NONE
:
734 dw4
|= GEN6_WM_STATISTICS_ENABLE
;
735 dw5
|= GEN6_WM_LINE_AA_WIDTH_1_0
;
736 dw5
|= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5
;
737 dw5
|= (brw
->max_wm_threads
- 1) << GEN6_WM_MAX_THREADS_SHIFT
;
738 dw6
|= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
; /* No interp */
739 dw6
|= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT
; /* No inputs from SF */
740 if (params
->use_wm_prog
) {
741 dw2
|= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT
; /* Up to 4 samplers */
742 dw4
|= prog_data
->first_curbe_grf
<< GEN6_WM_DISPATCH_START_GRF_SHIFT_0
;
743 dw5
|= GEN6_WM_16_DISPATCH_ENABLE
;
744 dw5
|= GEN6_WM_KILL_ENABLE
; /* TODO: temporarily smash on */
745 dw5
|= GEN6_WM_DISPATCH_ENABLE
; /* We are rendering */
748 if (params
->num_samples
> 0) {
749 dw6
|= GEN6_WM_MSRAST_ON_PATTERN
;
750 if (prog_data
&& prog_data
->persample_msaa_dispatch
)
751 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
753 dw6
|= GEN6_WM_MSDISPMODE_PERPIXEL
;
755 dw6
|= GEN6_WM_MSRAST_OFF_PIXEL
;
756 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
760 OUT_BATCH(_3DSTATE_WM
<< 16 | (9 - 2));
761 OUT_BATCH(params
->use_wm_prog
? prog_offset
: 0);
763 OUT_BATCH(0); /* No scratch needed */
767 OUT_BATCH(0); /* No other programs */
768 OUT_BATCH(0); /* No other programs */
774 gen6_blorp_emit_constant_ps(struct brw_context
*brw
,
775 const brw_blorp_params
*params
,
776 uint32_t wm_push_const_offset
)
778 struct intel_context
*intel
= &brw
->intel
;
780 /* Make sure the push constants fill an exact integer number of
783 assert(sizeof(brw_blorp_wm_push_constants
) % 32 == 0);
785 /* There must be at least one register worth of push constant data. */
786 assert(BRW_BLORP_NUM_PUSH_CONST_REGS
> 0);
788 /* Enable push constant buffer 0. */
790 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 |
791 GEN6_CONSTANT_BUFFER_0_ENABLE
|
793 OUT_BATCH(wm_push_const_offset
+ (BRW_BLORP_NUM_PUSH_CONST_REGS
- 1));
802 * 3DSTATE_BINDING_TABLE_POINTERS
805 gen6_blorp_emit_binding_table_pointers(struct brw_context
*brw
,
806 const brw_blorp_params
*params
,
807 uint32_t wm_bind_bo_offset
)
809 struct intel_context
*intel
= &brw
->intel
;
812 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
813 GEN6_BINDING_TABLE_MODIFY_PS
|
815 OUT_BATCH(0); /* vs -- ignored */
816 OUT_BATCH(0); /* gs -- ignored */
817 OUT_BATCH(wm_bind_bo_offset
); /* wm/ps */
823 gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw
,
824 const brw_blorp_params
*params
)
826 struct intel_context
*intel
= &brw
->intel
;
827 uint32_t draw_x
, draw_y
;
828 uint32_t tile_mask_x
, tile_mask_y
;
830 gen6_blorp_compute_tile_masks(params
, &tile_mask_x
, &tile_mask_y
);
831 params
->depth
.get_draw_offsets(&draw_x
, &draw_y
);
833 /* 3DSTATE_DEPTH_BUFFER */
835 uint32_t width
, height
;
836 params
->depth
.get_miplevel_dims(&width
, &height
);
838 uint32_t tile_x
= draw_x
& tile_mask_x
;
839 uint32_t tile_y
= draw_y
& tile_mask_y
;
841 intel_region_get_aligned_offset(params
->depth
.mt
->region
,
842 draw_x
& ~tile_mask_x
,
843 draw_y
& ~tile_mask_y
);
845 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
846 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
847 * Coordinate Offset X/Y":
849 * "The 3 LSBs of both offsets must be zero to ensure correct
852 * We have no guarantee that tile_x and tile_y are correctly aligned,
853 * since they are determined by the mipmap layout, which is only aligned
856 * So, to avoid hanging the GPU, just smash the low order 3 bits of
857 * tile_x and tile_y to 0. This is a temporary workaround until we come
858 * up with a better solution.
863 intel_emit_post_sync_nonzero_flush(intel
);
864 intel_emit_depth_stall_flushes(intel
);
867 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
868 uint32_t pitch_bytes
=
869 params
->depth
.mt
->region
->pitch
* params
->depth
.mt
->region
->cpp
;
870 OUT_BATCH((pitch_bytes
- 1) |
871 params
->depth_format
<< 18 |
872 1 << 21 | /* separate stencil enable */
873 1 << 22 | /* hiz enable */
874 BRW_TILEWALK_YMAJOR
<< 26 |
875 1 << 27 | /* y-tiled */
876 BRW_SURFACE_2D
<< 29);
877 OUT_RELOC(params
->depth
.mt
->region
->bo
,
878 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
880 OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1 |
881 (width
+ tile_x
- 1) << 6 |
882 (height
+ tile_y
- 1) << 19);
890 /* 3DSTATE_HIER_DEPTH_BUFFER */
892 struct intel_region
*hiz_region
= params
->depth
.mt
->hiz_mt
->region
;
893 uint32_t hiz_offset
=
894 intel_region_get_aligned_offset(hiz_region
,
895 draw_x
& ~tile_mask_x
,
896 (draw_y
& ~tile_mask_y
) / 2);
899 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
900 OUT_BATCH(hiz_region
->pitch
* hiz_region
->cpp
- 1);
901 OUT_RELOC(hiz_region
->bo
,
902 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
907 /* 3DSTATE_STENCIL_BUFFER */
910 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
919 gen6_blorp_emit_depth_disable(struct brw_context
*brw
,
920 const brw_blorp_params
*params
)
922 struct intel_context
*intel
= &brw
->intel
;
925 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
926 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
927 (BRW_SURFACE_NULL
<< 29));
937 /* 3DSTATE_CLEAR_PARAMS
939 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
940 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
941 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
944 gen6_blorp_emit_clear_params(struct brw_context
*brw
,
945 const brw_blorp_params
*params
)
947 struct intel_context
*intel
= &brw
->intel
;
950 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
951 GEN5_DEPTH_CLEAR_VALID
|
953 OUT_BATCH(params
->depth
.mt
? params
->depth
.mt
->depth_clear_value
: 0);
958 /* 3DSTATE_DRAWING_RECTANGLE */
960 gen6_blorp_emit_drawing_rectangle(struct brw_context
*brw
,
961 const brw_blorp_params
*params
)
963 struct intel_context
*intel
= &brw
->intel
;
966 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
968 OUT_BATCH(((params
->x1
- 1) & 0xffff) |
969 ((params
->y1
- 1) << 16));
974 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
976 gen6_blorp_emit_viewport_state(struct brw_context
*brw
,
977 const brw_blorp_params
*params
)
979 struct intel_context
*intel
= &brw
->intel
;
980 struct brw_cc_viewport
*ccv
;
981 uint32_t cc_vp_offset
;
983 ccv
= (struct brw_cc_viewport
*)brw_state_batch(brw
, AUB_TRACE_CC_VP_STATE
,
987 ccv
->min_depth
= 0.0;
988 ccv
->max_depth
= 1.0;
991 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS
<< 16 | (4 - 2) |
992 GEN6_CC_VIEWPORT_MODIFY
);
993 OUT_BATCH(0); /* clip VP */
994 OUT_BATCH(0); /* SF VP */
995 OUT_BATCH(cc_vp_offset
);
1002 gen6_blorp_emit_primitive(struct brw_context
*brw
,
1003 const brw_blorp_params
*params
)
1005 struct intel_context
*intel
= &brw
->intel
;
1008 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
1009 _3DPRIM_RECTLIST
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
1010 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
);
1011 OUT_BATCH(3); /* vertex count per instance */
1013 OUT_BATCH(1); /* instance count */
1021 * \brief Execute a blit or render pass operation.
1023 * To execute the operation, this function manually constructs and emits a
1024 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1025 * constructing and after emitting the batch.
1027 * This function alters no GL state.
1030 gen6_blorp_exec(struct intel_context
*intel
,
1031 const brw_blorp_params
*params
)
1033 struct gl_context
*ctx
= &intel
->ctx
;
1034 struct brw_context
*brw
= brw_context(ctx
);
1035 brw_blorp_prog_data
*prog_data
= NULL
;
1036 uint32_t cc_blend_state_offset
= 0;
1037 uint32_t cc_state_offset
= 0;
1038 uint32_t depthstencil_offset
;
1039 uint32_t wm_push_const_offset
= 0;
1040 uint32_t wm_bind_bo_offset
= 0;
1042 uint32_t prog_offset
= params
->get_wm_prog(brw
, &prog_data
);
1043 gen6_blorp_emit_batch_head(brw
, params
);
1044 gen6_emit_3dstate_multisample(brw
, params
->num_samples
);
1045 gen6_emit_3dstate_sample_mask(brw
, params
->num_samples
);
1046 gen6_blorp_emit_state_base_address(brw
, params
);
1047 gen6_blorp_emit_vertices(brw
, params
);
1048 gen6_blorp_emit_urb_config(brw
, params
);
1049 if (params
->use_wm_prog
) {
1050 cc_blend_state_offset
= gen6_blorp_emit_blend_state(brw
, params
);
1051 cc_state_offset
= gen6_blorp_emit_cc_state(brw
, params
);
1053 depthstencil_offset
= gen6_blorp_emit_depth_stencil_state(brw
, params
);
1054 gen6_blorp_emit_cc_state_pointers(brw
, params
, cc_blend_state_offset
,
1055 depthstencil_offset
, cc_state_offset
);
1056 if (params
->use_wm_prog
) {
1057 uint32_t wm_surf_offset_renderbuffer
;
1058 uint32_t wm_surf_offset_texture
;
1059 uint32_t sampler_offset
;
1060 wm_push_const_offset
= gen6_blorp_emit_wm_constants(brw
, params
);
1061 wm_surf_offset_renderbuffer
=
1062 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->dst
,
1063 I915_GEM_DOMAIN_RENDER
,
1064 I915_GEM_DOMAIN_RENDER
);
1065 wm_surf_offset_texture
=
1066 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->src
,
1067 I915_GEM_DOMAIN_SAMPLER
, 0);
1069 gen6_blorp_emit_binding_table(brw
, params
,
1070 wm_surf_offset_renderbuffer
,
1071 wm_surf_offset_texture
);
1072 sampler_offset
= gen6_blorp_emit_sampler_state(brw
, params
);
1073 gen6_blorp_emit_sampler_state_pointers(brw
, params
, sampler_offset
);
1075 gen6_blorp_emit_vs_disable(brw
, params
);
1076 gen6_blorp_emit_gs_disable(brw
, params
);
1077 gen6_blorp_emit_clip_disable(brw
, params
);
1078 gen6_blorp_emit_sf_config(brw
, params
);
1079 if (params
->use_wm_prog
)
1080 gen6_blorp_emit_constant_ps(brw
, params
, wm_push_const_offset
);
1081 gen6_blorp_emit_wm_config(brw
, params
, prog_offset
, prog_data
);
1082 if (params
->use_wm_prog
)
1083 gen6_blorp_emit_binding_table_pointers(brw
, params
, wm_bind_bo_offset
);
1084 gen6_blorp_emit_viewport_state(brw
, params
);
1086 if (params
->depth
.mt
)
1087 gen6_blorp_emit_depth_stencil_config(brw
, params
);
1089 gen6_blorp_emit_depth_disable(brw
, params
);
1090 gen6_blorp_emit_clear_params(brw
, params
);
1091 gen6_blorp_emit_drawing_rectangle(brw
, params
);
1092 gen6_blorp_emit_primitive(brw
, params
);
1094 /* See comments above at first invocation of intel_flush() in
1095 * gen6_blorp_emit_batch_head().
1100 brw
->state
.dirty
.brw
= ~0;
1101 brw
->state
.dirty
.cache
= ~0;