2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
28 #include "intel_mipmap_tree.h"
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_state.h"
34 #include "brw_blorp.h"
35 #include "gen6_blorp.h"
38 * \name Constants for BLORP VBO
41 #define GEN6_BLORP_NUM_VERTICES 3
42 #define GEN6_BLORP_NUM_VUE_ELEMS 8
43 #define GEN6_BLORP_VBO_SIZE (GEN6_BLORP_NUM_VERTICES \
44 * GEN6_BLORP_NUM_VUE_ELEMS \
50 * Compute masks to determine how much of draw_x and draw_y should be
51 * performed using the fine adjustment of "depth coordinate offset X/Y"
52 * (dw5 of 3DSTATE_DEPTH_BUFFER). See the emit_depthbuffer() function for
56 gen6_blorp_compute_tile_masks(const brw_blorp_params
*params
,
57 uint32_t *tile_mask_x
, uint32_t *tile_mask_y
)
59 uint32_t depth_mask_x
, depth_mask_y
, hiz_mask_x
, hiz_mask_y
;
60 intel_region_get_tile_masks(params
->depth
.mt
->region
,
61 &depth_mask_x
, &depth_mask_y
);
62 intel_region_get_tile_masks(params
->depth
.mt
->hiz_mt
->region
,
63 &hiz_mask_x
, &hiz_mask_y
);
65 /* Each HiZ row represents 2 rows of pixels */
66 hiz_mask_y
= hiz_mask_y
<< 1 | 1;
68 *tile_mask_x
= depth_mask_x
| hiz_mask_x
;
69 *tile_mask_y
= depth_mask_y
| hiz_mask_y
;
74 gen6_blorp_emit_batch_head(struct brw_context
*brw
,
75 const brw_blorp_params
*params
)
77 struct gl_context
*ctx
= &brw
->intel
.ctx
;
78 struct intel_context
*intel
= &brw
->intel
;
80 /* To ensure that the batch contains only the resolve, flush the batch
81 * before beginning and after finishing emitting the resolve packets.
83 * Ideally, we would not need to flush for the resolve op. But, I suspect
84 * that it's unsafe for CMD_PIPELINE_SELECT to occur multiple times in
85 * a single batch, and there is no safe way to ensure that other than by
86 * fencing the resolve with flushes. Ideally, we would just detect if
87 * a batch is in progress and do the right thing, but that would require
88 * the ability to *safely* access brw_context::state::dirty::brw
89 * outside of the brw_upload_state() codepath.
93 /* CMD_PIPELINE_SELECT
95 * Select the 3D pipeline, as opposed to the media pipeline.
99 OUT_BATCH(brw
->CMD_PIPELINE_SELECT
<< 16);
103 gen6_emit_3dstate_multisample(brw
, params
->num_samples
);
104 gen6_emit_3dstate_sample_mask(brw
, params
->num_samples
);
106 /* CMD_STATE_BASE_ADDRESS
108 * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS:
109 * The following commands must be reissued following any change to the
111 * 3DSTATE_CC_POINTERS
112 * 3DSTATE_BINDING_TABLE_POINTERS
113 * 3DSTATE_SAMPLER_STATE_POINTERS
114 * 3DSTATE_VIEWPORT_STATE_POINTERS
115 * MEDIA_STATE_POINTERS
119 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
120 OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */
121 /* SurfaceStateBaseAddress */
122 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
123 /* DynamicStateBaseAddress */
124 OUT_RELOC(intel
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
125 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
126 OUT_BATCH(1); /* IndirectObjectBaseAddress */
127 if (params
->use_wm_prog
) {
128 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
129 1); /* Instruction base address: shader kernels */
131 OUT_BATCH(1); /* InstructionBaseAddress */
133 OUT_BATCH(1); /* GeneralStateUpperBound */
134 OUT_BATCH(1); /* DynamicStateUpperBound */
135 OUT_BATCH(1); /* IndirectObjectUpperBound*/
136 OUT_BATCH(1); /* InstructionAccessUpperBound */
142 gen6_blorp_emit_vertices(struct brw_context
*brw
,
143 const brw_blorp_params
*params
)
145 struct intel_context
*intel
= &brw
->intel
;
146 uint32_t vertex_offset
;
148 /* Setup VBO for the rectangle primitive..
150 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
151 * vertices. The vertices reside in screen space with DirectX coordinates
152 * (that is, (0, 0) is the upper left corner).
159 * Since the VS is disabled, the clipper loads each VUE directly from
160 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
161 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
162 * dw0: Reserved, MBZ.
163 * dw1: Render Target Array Index. The HiZ op does not use indexed
164 * vertices, so set the dword to 0.
165 * dw2: Viewport Index. The HiZ op disables viewport mapping and
166 * scissoring, so set the dword to 0.
167 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
168 * set the dword to 0.
169 * dw4: Vertex Position X.
170 * dw5: Vertex Position Y.
171 * dw6: Vertex Position Z.
172 * dw7: Vertex Position W.
174 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
175 * "Vertex URB Entry (VUE) Formats".
180 const float vertices
[GEN6_BLORP_VBO_SIZE
] = {
181 /* v0 */ 0, 0, 0, 0, params
->x0
, params
->y1
, 0, 1,
182 /* v1 */ 0, 0, 0, 0, params
->x1
, params
->y1
, 0, 1,
183 /* v2 */ 0, 0, 0, 0, params
->x0
, params
->y0
, 0, 1,
186 vertex_data
= (float *) brw_state_batch(brw
, AUB_TRACE_VERTEX_BUFFER
,
187 GEN6_BLORP_VBO_SIZE
, 32,
189 memcpy(vertex_data
, vertices
, GEN6_BLORP_VBO_SIZE
);
192 /* 3DSTATE_VERTEX_BUFFERS */
194 const int num_buffers
= 1;
195 const int batch_length
= 1 + 4 * num_buffers
;
197 uint32_t dw0
= GEN6_VB0_ACCESS_VERTEXDATA
|
198 (GEN6_BLORP_NUM_VUE_ELEMS
* sizeof(float)) << BRW_VB0_PITCH_SHIFT
;
201 dw0
|= GEN7_VB0_ADDRESS_MODIFYENABLE
;
203 BEGIN_BATCH(batch_length
);
204 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS
<< 16) | (batch_length
- 2));
207 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
210 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_VERTEX
, 0,
211 vertex_offset
+ GEN6_BLORP_VBO_SIZE
- 1);
216 /* 3DSTATE_VERTEX_ELEMENTS
218 * Fetch dwords 0 - 7 from each VUE. See the comments above where
219 * the vertex_bo is filled with data.
222 const int num_elements
= 2;
223 const int batch_length
= 1 + 2 * num_elements
;
225 BEGIN_BATCH(batch_length
);
226 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (batch_length
- 2));
228 OUT_BATCH(GEN6_VE0_VALID
|
229 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
230 0 << BRW_VE0_SRC_OFFSET_SHIFT
);
231 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
232 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
233 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
234 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
236 OUT_BATCH(GEN6_VE0_VALID
|
237 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
|
238 16 << BRW_VE0_SRC_OFFSET_SHIFT
);
239 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
|
240 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_1_SHIFT
|
241 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_2_SHIFT
|
242 BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_3_SHIFT
);
250 * Assign the entire URB to the VS. Even though the VS disabled, URB space
251 * is still needed because the clipper loads the VUE's from the URB. From
252 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
253 * Dword 1.15:0 "VS Number of URB Entries":
254 * This field is always used (even if VS Function Enable is DISABLED).
256 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
257 * safely ignore it because this batch contains only one draw call.
258 * Because of URB corruption caused by allocating a previous GS unit
259 * URB entry to the VS unit, software is required to send a “GS NULL
260 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
261 * plus a dummy DRAW call before any case where VS will be taking over
265 gen6_blorp_emit_urb_config(struct brw_context
*brw
,
266 const brw_blorp_params
*params
)
268 struct intel_context
*intel
= &brw
->intel
;
271 OUT_BATCH(_3DSTATE_URB
<< 16 | (3 - 2));
272 OUT_BATCH(brw
->urb
.max_vs_entries
<< GEN6_URB_VS_ENTRIES_SHIFT
);
280 gen6_blorp_emit_blend_state(struct brw_context
*brw
,
281 const brw_blorp_params
*params
)
283 uint32_t cc_blend_state_offset
;
285 struct gen6_blend_state
*blend
= (struct gen6_blend_state
*)
286 brw_state_batch(brw
, AUB_TRACE_BLEND_STATE
,
287 sizeof(struct gen6_blend_state
), 64,
288 &cc_blend_state_offset
);
290 memset(blend
, 0, sizeof(*blend
));
292 // TODO: handle other formats.
293 blend
->blend1
.pre_blend_clamp_enable
= 1;
294 blend
->blend1
.post_blend_clamp_enable
= 1;
295 blend
->blend1
.clamp_range
= BRW_RENDERTARGET_CLAMPRANGE_FORMAT
;
297 blend
->blend1
.write_disable_r
= false;
298 blend
->blend1
.write_disable_g
= false;
299 blend
->blend1
.write_disable_b
= false;
300 blend
->blend1
.write_disable_a
= false;
302 return cc_blend_state_offset
;
308 gen6_blorp_emit_cc_state(struct brw_context
*brw
,
309 const brw_blorp_params
*params
)
311 uint32_t cc_state_offset
;
313 struct gen6_color_calc_state
*cc
= (struct gen6_color_calc_state
*)
314 brw_state_batch(brw
, AUB_TRACE_CC_STATE
,
315 sizeof(gen6_color_calc_state
), 64,
317 memset(cc
, 0, sizeof(*cc
));
319 return cc_state_offset
;
324 * \param out_offset is relative to
325 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
328 gen6_blorp_emit_depth_stencil_state(struct brw_context
*brw
,
329 const brw_blorp_params
*params
)
331 uint32_t depthstencil_offset
;
333 struct gen6_depth_stencil_state
*state
;
334 state
= (struct gen6_depth_stencil_state
*)
335 brw_state_batch(brw
, AUB_TRACE_DEPTH_STENCIL_STATE
,
337 &depthstencil_offset
);
338 memset(state
, 0, sizeof(*state
));
340 /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
341 * - 7.5.3.1 Depth Buffer Clear
342 * - 7.5.3.2 Depth Buffer Resolve
343 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
345 state
->ds2
.depth_write_enable
= 1;
346 if (params
->hiz_op
== GEN6_HIZ_OP_DEPTH_RESOLVE
) {
347 state
->ds2
.depth_test_enable
= 1;
348 state
->ds2
.depth_test_func
= COMPAREFUNC_NEVER
;
351 return depthstencil_offset
;
355 /* 3DSTATE_CC_STATE_POINTERS
357 * The pointer offsets are relative to
358 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
360 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
363 gen6_blorp_emit_cc_state_pointers(struct brw_context
*brw
,
364 const brw_blorp_params
*params
,
365 uint32_t cc_blend_state_offset
,
366 uint32_t depthstencil_offset
,
367 uint32_t cc_state_offset
)
369 struct intel_context
*intel
= &brw
->intel
;
372 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (4 - 2));
373 OUT_BATCH(cc_blend_state_offset
| 1); /* BLEND_STATE offset */
374 OUT_BATCH(depthstencil_offset
| 1); /* DEPTH_STENCIL_STATE offset */
375 OUT_BATCH(cc_state_offset
| 1); /* COLOR_CALC_STATE offset */
380 /* WM push constants */
382 gen6_blorp_emit_wm_constants(struct brw_context
*brw
,
383 const brw_blorp_params
*params
)
385 uint32_t wm_push_const_offset
;
387 void *constants
= brw_state_batch(brw
, AUB_TRACE_WM_CONSTANTS
,
388 sizeof(params
->wm_push_consts
),
389 32, &wm_push_const_offset
);
390 memcpy(constants
, ¶ms
->wm_push_consts
,
391 sizeof(params
->wm_push_consts
));
393 return wm_push_const_offset
;
397 /* SURFACE_STATE for renderbuffer or texture surface (see
398 * brw_update_renderbuffer_surface and brw_update_texture_surface)
401 gen6_blorp_emit_surface_state(struct brw_context
*brw
,
402 const brw_blorp_params
*params
,
403 const brw_blorp_surface_info
*surface
,
404 uint32_t read_domains
, uint32_t write_domain
)
406 uint32_t wm_surf_offset
;
407 uint32_t width
, height
;
408 surface
->get_miplevel_dims(&width
, &height
);
409 if (surface
->num_samples
> 0) { /* TODO: seems clumsy */
413 if (surface
->map_stencil_as_y_tiled
) {
417 struct intel_region
*region
= surface
->mt
->region
;
419 /* TODO: handle other formats */
420 uint32_t format
= surface
->map_stencil_as_y_tiled
421 ? BRW_SURFACEFORMAT_R8_UNORM
: BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
423 uint32_t *surf
= (uint32_t *)
424 brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
427 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
428 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
429 BRW_SURFACE_CUBEFACE_ENABLES
|
430 format
<< BRW_SURFACE_FORMAT_SHIFT
);
433 surf
[1] = region
->bo
->offset
; /* No tile offsets needed */
435 surf
[2] = (0 << BRW_SURFACE_LOD_SHIFT
|
436 (width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
437 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
439 uint32_t tiling
= surface
->map_stencil_as_y_tiled
440 ? BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
441 : brw_get_surface_tiling_bits(region
->tiling
);
442 uint32_t pitch_bytes
= region
->pitch
* region
->cpp
;
443 if (surface
->map_stencil_as_y_tiled
)
446 0 << BRW_SURFACE_DEPTH_SHIFT
|
447 (pitch_bytes
- 1) << BRW_SURFACE_PITCH_SHIFT
);
449 surf
[4] = brw_get_surface_num_multisamples(surface
->num_samples
);
451 surf
[5] = (0 << BRW_SURFACE_X_OFFSET_SHIFT
|
452 0 << BRW_SURFACE_Y_OFFSET_SHIFT
|
453 (surface
->mt
->align_h
== 4 ?
454 BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
456 /* Emit relocation to surface contents */
457 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
460 surf
[1] - region
->bo
->offset
,
461 read_domains
, write_domain
);
463 return wm_surf_offset
;
467 /* BINDING_TABLE. See brw_wm_binding_table(). */
469 gen6_blorp_emit_binding_table(struct brw_context
*brw
,
470 const brw_blorp_params
*params
,
471 uint32_t wm_surf_offset_renderbuffer
,
472 uint32_t wm_surf_offset_texture
)
474 uint32_t wm_bind_bo_offset
;
475 uint32_t *bind
= (uint32_t *)
476 brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
478 BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
,
481 bind
[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
] =
482 wm_surf_offset_renderbuffer
;
483 bind
[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
] = wm_surf_offset_texture
;
485 return wm_bind_bo_offset
;
490 * SAMPLER_STATE. See brw_update_sampler_state().
493 gen6_blorp_emit_sampler_state(struct brw_context
*brw
,
494 const brw_blorp_params
*params
)
496 uint32_t sampler_offset
;
498 struct brw_sampler_state
*sampler
= (struct brw_sampler_state
*)
499 brw_state_batch(brw
, AUB_TRACE_SAMPLER_STATE
,
500 sizeof(struct brw_sampler_state
),
501 32, &sampler_offset
);
502 memset(sampler
, 0, sizeof(*sampler
));
504 sampler
->ss0
.min_filter
= BRW_MAPFILTER_LINEAR
;
505 sampler
->ss0
.mip_filter
= BRW_MIPFILTER_NONE
;
506 sampler
->ss0
.mag_filter
= BRW_MAPFILTER_LINEAR
;
508 sampler
->ss1
.r_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
509 sampler
->ss1
.s_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
510 sampler
->ss1
.t_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
512 sampler
->ss0
.min_mag_neq
= 1;
516 sampler
->ss0
.lod_bias
= 0;
518 sampler
->ss0
.lod_preclamp
= 1; /* OpenGL mode */
519 sampler
->ss0
.default_color_mode
= 0; /* OpenGL/DX10 mode */
521 /* Set BaseMipLevel, MaxLOD, MinLOD:
523 * XXX: I don't think that using firstLevel, lastLevel works,
524 * because we always setup the surface state as if firstLevel ==
525 * level zero. Probably have to subtract firstLevel from each of
528 sampler
->ss0
.base_level
= U_FIXED(0, 1);
530 sampler
->ss1
.max_lod
= U_FIXED(0, 6);
531 sampler
->ss1
.min_lod
= U_FIXED(0, 6);
533 sampler
->ss3
.non_normalized_coord
= 1;
535 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN
|
536 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN
|
537 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN
;
538 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG
|
539 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG
|
540 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG
;
542 return sampler_offset
;
547 * 3DSTATE_SAMPLER_STATE_POINTERS. See upload_sampler_state_pointers().
550 gen6_blorp_emit_sampler_state_pointers(struct brw_context
*brw
,
551 const brw_blorp_params
*params
,
552 uint32_t sampler_offset
)
554 struct intel_context
*intel
= &brw
->intel
;
557 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS
<< 16 |
558 VS_SAMPLER_STATE_CHANGE
|
559 GS_SAMPLER_STATE_CHANGE
|
560 PS_SAMPLER_STATE_CHANGE
|
562 OUT_BATCH(0); /* VS */
563 OUT_BATCH(0); /* GS */
564 OUT_BATCH(sampler_offset
);
571 * Disable vertex shader.
574 gen6_blorp_emit_vs_disable(struct brw_context
*brw
,
575 const brw_blorp_params
*params
)
577 struct intel_context
*intel
= &brw
->intel
;
579 if (intel
->gen
== 6) {
580 /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section
581 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
583 * [DevSNB] A pipeline flush must be programmed prior to a
584 * 3DSTATE_VS command that causes the VS Function Enable to
585 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
586 * command with CS stall bit set and a post sync operation.
588 intel_emit_post_sync_nonzero_flush(intel
);
592 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
604 * Disable the geometry shader.
607 gen6_blorp_emit_gs_disable(struct brw_context
*brw
,
608 const brw_blorp_params
*params
)
610 struct intel_context
*intel
= &brw
->intel
;
613 OUT_BATCH(_3DSTATE_GS
<< 16 | (7 - 2));
626 * Disable the clipper.
628 * The BLORP op emits a rectangle primitive, which requires clipping to
629 * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
630 * Section 1.3 "3D Primitives Overview":
632 * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
633 * Mode should be set to a value other than CLIPMODE_NORMAL.
635 * Also disable perspective divide. This doesn't change the clipper's
636 * output, but does spare a few electrons.
639 gen6_blorp_emit_clip_disable(struct brw_context
*brw
,
640 const brw_blorp_params
*params
)
642 struct intel_context
*intel
= &brw
->intel
;
645 OUT_BATCH(_3DSTATE_CLIP
<< 16 | (4 - 2));
647 OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE
);
655 * Disable ViewportTransformEnable (dw2.1)
657 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
658 * Primitives Overview":
659 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
660 * use of screen- space coordinates).
662 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
663 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
665 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
666 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
667 * SOLID: Any triangle or rectangle object found to be front-facing
668 * is rendered as a solid object. This setting is required when
669 * (rendering rectangle (RECTLIST) objects.
672 gen6_blorp_emit_sf_config(struct brw_context
*brw
,
673 const brw_blorp_params
*params
)
675 struct intel_context
*intel
= &brw
->intel
;
678 OUT_BATCH(_3DSTATE_SF
<< 16 | (20 - 2));
679 OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT
| /* only position */
680 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT
|
681 0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT
);
682 OUT_BATCH(0); /* dw2 */
683 OUT_BATCH(params
->num_samples
> 0 ? GEN6_SF_MSRAST_ON_PATTERN
: 0);
684 for (int i
= 0; i
< 16; ++i
)
691 * Enable or disable thread dispatch and set the HiZ op appropriately.
694 gen6_blorp_emit_wm_config(struct brw_context
*brw
,
695 const brw_blorp_params
*params
,
696 uint32_t prog_offset
,
697 brw_blorp_prog_data
*prog_data
)
699 struct intel_context
*intel
= &brw
->intel
;
700 uint32_t dw2
, dw4
, dw5
, dw6
;
702 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
703 * nonzero to prevent the GPU from hanging. See the valid ranges in the
704 * BSpec, Volume 2a.11 Windower, Section 3DSTATE_WM, Dword 5.25:31
705 * "Maximum Number Of Threads".
707 * To be safe (and to minimize extraneous code) we go ahead and fully
708 * configure the WM state whether or not there is a WM program.
711 dw2
= dw4
= dw5
= dw6
= 0;
712 switch (params
->hiz_op
) {
713 case GEN6_HIZ_OP_DEPTH_CLEAR
:
714 assert(!"not implemented");
715 dw4
|= GEN6_WM_DEPTH_CLEAR
;
717 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
718 dw4
|= GEN6_WM_DEPTH_RESOLVE
;
720 case GEN6_HIZ_OP_HIZ_RESOLVE
:
721 dw4
|= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE
;
723 case GEN6_HIZ_OP_NONE
:
729 dw4
|= GEN6_WM_STATISTICS_ENABLE
;
730 dw5
|= GEN6_WM_LINE_AA_WIDTH_1_0
;
731 dw5
|= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5
;
732 dw5
|= (brw
->max_wm_threads
- 1) << GEN6_WM_MAX_THREADS_SHIFT
;
733 dw6
|= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
; /* No interp */
734 dw6
|= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT
; /* No inputs from SF */
735 if (params
->use_wm_prog
) {
736 dw2
|= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT
; /* Up to 4 samplers */
737 dw4
|= prog_data
->first_curbe_grf
<< GEN6_WM_DISPATCH_START_GRF_SHIFT_0
;
738 dw5
|= GEN6_WM_16_DISPATCH_ENABLE
;
739 dw5
|= GEN6_WM_KILL_ENABLE
; /* TODO: temporarily smash on */
740 dw5
|= GEN6_WM_DISPATCH_ENABLE
; /* We are rendering */
743 if (params
->num_samples
> 0) {
744 dw6
|= GEN6_WM_MSRAST_ON_PATTERN
;
745 dw6
|= GEN6_WM_MSDISPMODE_PERPIXEL
;
747 dw6
|= GEN6_WM_MSRAST_OFF_PIXEL
;
748 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
752 OUT_BATCH(_3DSTATE_WM
<< 16 | (9 - 2));
753 OUT_BATCH(params
->use_wm_prog
? prog_offset
: 0);
755 OUT_BATCH(0); /* No scratch needed */
759 OUT_BATCH(0); /* No other programs */
760 OUT_BATCH(0); /* No other programs */
766 gen6_blorp_emit_constant_ps(struct brw_context
*brw
,
767 const brw_blorp_params
*params
,
768 uint32_t wm_push_const_offset
)
770 struct intel_context
*intel
= &brw
->intel
;
772 /* Make sure the push constants fill an exact integer number of
775 assert(sizeof(brw_blorp_wm_push_constants
) % 32 == 0);
777 /* There must be at least one register worth of push constant data. */
778 assert(BRW_BLORP_NUM_PUSH_CONST_REGS
> 0);
780 /* Enable push constant buffer 0. */
782 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 |
783 GEN6_CONSTANT_BUFFER_0_ENABLE
|
785 OUT_BATCH(wm_push_const_offset
+ (BRW_BLORP_NUM_PUSH_CONST_REGS
- 1));
794 * 3DSTATE_BINDING_TABLE_POINTERS
797 gen6_blorp_emit_binding_table_pointers(struct brw_context
*brw
,
798 const brw_blorp_params
*params
,
799 uint32_t wm_bind_bo_offset
)
801 struct intel_context
*intel
= &brw
->intel
;
804 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
805 GEN6_BINDING_TABLE_MODIFY_PS
|
807 OUT_BATCH(0); /* vs -- ignored */
808 OUT_BATCH(0); /* gs -- ignored */
809 OUT_BATCH(wm_bind_bo_offset
); /* wm/ps */
815 gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw
,
816 const brw_blorp_params
*params
)
818 struct intel_context
*intel
= &brw
->intel
;
819 uint32_t draw_x
, draw_y
;
820 uint32_t tile_mask_x
, tile_mask_y
;
822 gen6_blorp_compute_tile_masks(params
, &tile_mask_x
, &tile_mask_y
);
823 params
->depth
.get_draw_offsets(&draw_x
, &draw_y
);
825 /* 3DSTATE_DEPTH_BUFFER */
827 uint32_t width
, height
;
828 params
->depth
.get_miplevel_dims(&width
, &height
);
830 uint32_t tile_x
= draw_x
& tile_mask_x
;
831 uint32_t tile_y
= draw_y
& tile_mask_y
;
833 intel_region_get_aligned_offset(params
->depth
.mt
->region
,
834 draw_x
& ~tile_mask_x
,
835 draw_y
& ~tile_mask_y
);
837 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
838 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
839 * Coordinate Offset X/Y":
841 * "The 3 LSBs of both offsets must be zero to ensure correct
844 * We have no guarantee that tile_x and tile_y are correctly aligned,
845 * since they are determined by the mipmap layout, which is only aligned
848 * So, to avoid hanging the GPU, just smash the low order 3 bits of
849 * tile_x and tile_y to 0. This is a temporary workaround until we come
850 * up with a better solution.
855 intel_emit_post_sync_nonzero_flush(intel
);
856 intel_emit_depth_stall_flushes(intel
);
859 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
860 uint32_t pitch_bytes
=
861 params
->depth
.mt
->region
->pitch
* params
->depth
.mt
->region
->cpp
;
862 OUT_BATCH((pitch_bytes
- 1) |
863 params
->depth_format
<< 18 |
864 1 << 21 | /* separate stencil enable */
865 1 << 22 | /* hiz enable */
866 BRW_TILEWALK_YMAJOR
<< 26 |
867 1 << 27 | /* y-tiled */
868 BRW_SURFACE_2D
<< 29);
869 OUT_RELOC(params
->depth
.mt
->region
->bo
,
870 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
872 OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1 |
873 (width
+ tile_x
- 1) << 6 |
874 (height
+ tile_y
- 1) << 19);
882 /* 3DSTATE_HIER_DEPTH_BUFFER */
884 struct intel_region
*hiz_region
= params
->depth
.mt
->hiz_mt
->region
;
885 uint32_t hiz_offset
=
886 intel_region_get_aligned_offset(hiz_region
,
887 draw_x
& ~tile_mask_x
,
888 (draw_y
& ~tile_mask_y
) / 2);
891 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
892 OUT_BATCH(hiz_region
->pitch
* hiz_region
->cpp
- 1);
893 OUT_RELOC(hiz_region
->bo
,
894 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
899 /* 3DSTATE_STENCIL_BUFFER */
902 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
911 gen6_blorp_emit_depth_disable(struct brw_context
*brw
,
912 const brw_blorp_params
*params
)
914 struct intel_context
*intel
= &brw
->intel
;
917 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
918 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
919 (BRW_SURFACE_NULL
<< 29));
929 /* 3DSTATE_CLEAR_PARAMS
931 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
932 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
933 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
936 gen6_blorp_emit_clear_params(struct brw_context
*brw
,
937 const brw_blorp_params
*params
)
939 struct intel_context
*intel
= &brw
->intel
;
942 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 | (2 - 2));
948 /* 3DSTATE_DRAWING_RECTANGLE */
950 gen6_blorp_emit_drawing_rectangle(struct brw_context
*brw
,
951 const brw_blorp_params
*params
)
953 struct intel_context
*intel
= &brw
->intel
;
956 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
958 OUT_BATCH(((params
->x1
- 1) & 0xffff) |
959 ((params
->y1
- 1) << 16));
964 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
966 gen6_blorp_emit_viewport_state(struct brw_context
*brw
,
967 const brw_blorp_params
*params
)
969 struct intel_context
*intel
= &brw
->intel
;
970 struct brw_cc_viewport
*ccv
;
971 uint32_t cc_vp_offset
;
973 ccv
= (struct brw_cc_viewport
*)brw_state_batch(brw
, AUB_TRACE_CC_VP_STATE
,
977 ccv
->min_depth
= 0.0;
978 ccv
->max_depth
= 1.0;
981 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS
<< 16 | (4 - 2) |
982 GEN6_CC_VIEWPORT_MODIFY
);
983 OUT_BATCH(0); /* clip VP */
984 OUT_BATCH(0); /* SF VP */
985 OUT_BATCH(cc_vp_offset
);
992 gen6_blorp_emit_primitive(struct brw_context
*brw
,
993 const brw_blorp_params
*params
)
995 struct intel_context
*intel
= &brw
->intel
;
998 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
999 _3DPRIM_RECTLIST
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
1000 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
);
1001 OUT_BATCH(3); /* vertex count per instance */
1003 OUT_BATCH(1); /* instance count */
1011 * \brief Execute a blit or render pass operation.
1013 * To execute the operation, this function manually constructs and emits a
1014 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1015 * constructing and after emitting the batch.
1017 * This function alters no GL state.
1020 gen6_blorp_exec(struct intel_context
*intel
,
1021 const brw_blorp_params
*params
)
1023 struct gl_context
*ctx
= &intel
->ctx
;
1024 struct brw_context
*brw
= brw_context(ctx
);
1025 brw_blorp_prog_data
*prog_data
= NULL
;
1026 uint32_t cc_blend_state_offset
= 0;
1027 uint32_t cc_state_offset
= 0;
1028 uint32_t depthstencil_offset
;
1029 uint32_t wm_push_const_offset
= 0;
1030 uint32_t wm_bind_bo_offset
= 0;
1032 uint32_t prog_offset
= params
->get_wm_prog(brw
, &prog_data
);
1033 gen6_blorp_emit_batch_head(brw
, params
);
1034 gen6_blorp_emit_vertices(brw
, params
);
1035 gen6_blorp_emit_urb_config(brw
, params
);
1036 if (params
->use_wm_prog
) {
1037 cc_blend_state_offset
= gen6_blorp_emit_blend_state(brw
, params
);
1038 cc_state_offset
= gen6_blorp_emit_cc_state(brw
, params
);
1040 depthstencil_offset
= gen6_blorp_emit_depth_stencil_state(brw
, params
);
1041 gen6_blorp_emit_cc_state_pointers(brw
, params
, cc_blend_state_offset
,
1042 depthstencil_offset
, cc_state_offset
);
1043 if (params
->use_wm_prog
) {
1044 uint32_t wm_surf_offset_renderbuffer
;
1045 uint32_t wm_surf_offset_texture
;
1046 uint32_t sampler_offset
;
1047 wm_push_const_offset
= gen6_blorp_emit_wm_constants(brw
, params
);
1048 wm_surf_offset_renderbuffer
=
1049 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->dst
,
1050 I915_GEM_DOMAIN_RENDER
,
1051 I915_GEM_DOMAIN_RENDER
);
1052 wm_surf_offset_texture
=
1053 gen6_blorp_emit_surface_state(brw
, params
, ¶ms
->src
,
1054 I915_GEM_DOMAIN_SAMPLER
, 0);
1056 gen6_blorp_emit_binding_table(brw
, params
,
1057 wm_surf_offset_renderbuffer
,
1058 wm_surf_offset_texture
);
1059 sampler_offset
= gen6_blorp_emit_sampler_state(brw
, params
);
1060 gen6_blorp_emit_sampler_state_pointers(brw
, params
, sampler_offset
);
1062 gen6_blorp_emit_vs_disable(brw
, params
);
1063 gen6_blorp_emit_gs_disable(brw
, params
);
1064 gen6_blorp_emit_clip_disable(brw
, params
);
1065 gen6_blorp_emit_sf_config(brw
, params
);
1066 if (params
->use_wm_prog
)
1067 gen6_blorp_emit_constant_ps(brw
, params
, wm_push_const_offset
);
1068 gen6_blorp_emit_wm_config(brw
, params
, prog_offset
, prog_data
);
1069 if (params
->use_wm_prog
)
1070 gen6_blorp_emit_binding_table_pointers(brw
, params
, wm_bind_bo_offset
);
1071 gen6_blorp_emit_viewport_state(brw
, params
);
1073 if (params
->depth
.mt
)
1074 gen6_blorp_emit_depth_stencil_config(brw
, params
);
1076 gen6_blorp_emit_depth_disable(brw
, params
);
1077 gen6_blorp_emit_clear_params(brw
, params
);
1078 gen6_blorp_emit_drawing_rectangle(brw
, params
);
1079 gen6_blorp_emit_primitive(brw
, params
);
1081 /* See comments above at first invocation of intel_flush() in
1082 * gen6_blorp_emit_batch_head().
1087 brw
->state
.dirty
.brw
= ~0;
1088 brw
->state
.dirty
.cache
= ~0;