src/mesa/drivers/dri/i965/gen6_cc.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "intel_batchbuffer.h"
  33 #include "main/macros.h"
  34
  35 static void
  36 gen6_upload_blend_state(struct brw_context *brw)
  37 {
  38    struct gl_context *ctx = &brw->intel.ctx;
  39    struct gen6_blend_state *blend;
  40    int b;
  41    int nr_draw_buffers = ctx->DrawBuffer->_NumColorDrawBuffers;
  42    int size;
  43
  44    /* We need at least one BLEND_STATE written, because we might do
  45     * thread dispatch even if _NumColorDrawBuffers is 0 (for example
  46     * for computed depth or alpha test), which will do an FB write
  47     * with render target 0, which will reference BLEND_STATE[0] for
  48     * alpha test enable.
  49     */
  50    if (nr_draw_buffers == 0 && ctx->Color.AlphaEnabled)
  51       nr_draw_buffers = 1;
  52
  53    size = sizeof(*blend) * nr_draw_buffers;
  54    blend = brw_state_batch(brw, AUB_TRACE_BLEND_STATE,
  55                            size, 64, &brw->cc.blend_state_offset);
  56
  57    memset(blend, 0, size);
  58
  59    for (b = 0; b < nr_draw_buffers; b++) {
  60       /* _NEW_COLOR */
  61       if (ctx->Color.ColorLogicOpEnabled) {
  62          struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[b];
  63          /* _NEW_BUFFERS */
  64          /* Floating point RTs should have no effect from LogicOp,
  65           * except for disabling of blending
  66           */
  67          if (rb && _mesa_get_format_datatype(rb->Format) != GL_FLOAT) {
  68             blend[b].blend1.logic_op_enable = 1;
  69             blend[b].blend1.logic_op_func =
  70                intel_translate_logic_op(ctx->Color.LogicOp);
  71          }
  72       } else if (ctx->Color.BlendEnabled & (1 << b)) {
  73          GLenum eqRGB = ctx->Color.Blend[0].EquationRGB;
  74          GLenum eqA = ctx->Color.Blend[0].EquationA;
  75          GLenum srcRGB = ctx->Color.Blend[0].SrcRGB;
  76          GLenum dstRGB = ctx->Color.Blend[0].DstRGB;
  77          GLenum srcA = ctx->Color.Blend[0].SrcA;
  78          GLenum dstA = ctx->Color.Blend[0].DstA;
  79
  80          if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
  81             srcRGB = dstRGB = GL_ONE;
  82          }
  83
  84          if (eqA == GL_MIN || eqA == GL_MAX) {
  85             srcA = dstA = GL_ONE;
  86          }
  87
  88          blend[b].blend0.dest_blend_factor = brw_translate_blend_factor(dstRGB);
  89          blend[b].blend0.source_blend_factor = brw_translate_blend_factor(srcRGB);
  90          blend[b].blend0.blend_func = brw_translate_blend_equation(eqRGB);
  91
  92          blend[b].blend0.ia_dest_blend_factor = brw_translate_blend_factor(dstA);
  93          blend[b].blend0.ia_source_blend_factor = brw_translate_blend_factor(srcA);
  94          blend[b].blend0.ia_blend_func = brw_translate_blend_equation(eqA);
  95
  96          blend[b].blend0.blend_enable = 1;
  97          blend[b].blend0.ia_blend_enable = (srcA != srcRGB ||
  98                                          dstA != dstRGB ||
  99                                          eqA != eqRGB);
 100       }
 101
 102       /* See section 8.1.6 "Pre-Blend Color Clamping" of the
 103        * SandyBridge PRM Volume 2 Part 1 for HW requirements.
 104        *
 105        * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
 106        * clamping in the fragment shader.  For its clamping of
 107        * blending, the spec says:
 108        *
 109        *     "RESOLVED: For fixed-point color buffers, the inputs and
 110        *      the result of the blending equation are clamped.  For
 111        *      floating-point color buffers, no clamping occurs."
 112        *
 113        * So, generally, we want clamping to the render target's range.
 114        * And, good news, the hardware tables for both pre- and
 115        * post-blend color clamping are either ignored, or any are
 116        * allowed, or clamping is required but RT range clamping is a
 117        * valid option.
 118        */
 119       blend[b].blend1.pre_blend_clamp_enable = 1;
 120       blend[b].blend1.post_blend_clamp_enable = 1;
 121       blend[b].blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
 122
 123       /* _NEW_COLOR */
 124       if (ctx->Color.AlphaEnabled) {
 125          blend[b].blend1.alpha_test_enable = 1;
 126          blend[b].blend1.alpha_test_func =
 127             intel_translate_compare_func(ctx->Color.AlphaFunc);
 128
 129       }
 130
 131       /* _NEW_COLOR */
 132       if (ctx->Color.DitherFlag) {
 133          blend[b].blend1.dither_enable = 1;
 134          blend[b].blend1.y_dither_offset = 0;
 135          blend[b].blend1.x_dither_offset = 0;
 136       }
 137
 138       blend[b].blend1.write_disable_r = !ctx->Color.ColorMask[b][0];
 139       blend[b].blend1.write_disable_g = !ctx->Color.ColorMask[b][1];
 140       blend[b].blend1.write_disable_b = !ctx->Color.ColorMask[b][2];
 141       blend[b].blend1.write_disable_a = !ctx->Color.ColorMask[b][3];
 142    }
 143
 144    brw->state.dirty.cache |= CACHE_NEW_BLEND_STATE;
 145 }
 146
 147 const struct brw_tracked_state gen6_blend_state = {
 148    .dirty = {
 149       .mesa = (_NEW_COLOR |
 150                _NEW_BUFFERS),
 151       .brw = BRW_NEW_BATCH,
 152       .cache = 0,
 153    },
 154    .emit = gen6_upload_blend_state,
 155 };
 156
 157 static void
 158 gen6_upload_color_calc_state(struct brw_context *brw)
 159 {
 160    struct gl_context *ctx = &brw->intel.ctx;
 161    struct gen6_color_calc_state *cc;
 162
 163    cc = brw_state_batch(brw, AUB_TRACE_CC_STATE,
 164                         sizeof(*cc), 64, &brw->cc.state_offset);
 165    memset(cc, 0, sizeof(*cc));
 166
 167    /* _NEW_COLOR */
 168    cc->cc0.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
 169    UNCLAMPED_FLOAT_TO_UBYTE(cc->cc1.alpha_ref_fi.ui, ctx->Color.AlphaRef);
 170
 171    /* _NEW_STENCIL */
 172    cc->cc0.stencil_ref = ctx->Stencil.Ref[0];
 173    cc->cc0.bf_stencil_ref = ctx->Stencil.Ref[ctx->Stencil._BackFace];
 174
 175    /* _NEW_COLOR */
 176    cc->constant_r = ctx->Color.BlendColorUnclamped[0];
 177    cc->constant_g = ctx->Color.BlendColorUnclamped[1];
 178    cc->constant_b = ctx->Color.BlendColorUnclamped[2];
 179    cc->constant_a = ctx->Color.BlendColorUnclamped[3];
 180
 181    brw->state.dirty.cache |= CACHE_NEW_COLOR_CALC_STATE;
 182 }
 183
 184 const struct brw_tracked_state gen6_color_calc_state = {
 185    .dirty = {
 186       .mesa = _NEW_COLOR | _NEW_STENCIL,
 187       .brw = BRW_NEW_BATCH,
 188       .cache = 0,
 189    },
 190    .emit = gen6_upload_color_calc_state,
 191 };
 192
 193 static void upload_cc_state_pointers(struct brw_context *brw)
 194 {
 195    struct intel_context *intel = &brw->intel;
 196
 197    BEGIN_BATCH(4);
 198    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
 199    OUT_BATCH(brw->cc.blend_state_offset | 1);
 200    OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
 201    OUT_BATCH(brw->cc.state_offset | 1);
 202    ADVANCE_BATCH();
 203 }
 204
 205 const struct brw_tracked_state gen6_cc_state_pointers = {
 206    .dirty = {
 207       .mesa = 0,
 208       .brw = (BRW_NEW_BATCH |
 209               BRW_NEW_STATE_BASE_ADDRESS),
 210       .cache = (CACHE_NEW_BLEND_STATE |
 211                 CACHE_NEW_COLOR_CALC_STATE |
 212                 CACHE_NEW_DEPTH_STENCIL_STATE)
 213    },
 214    .emit = upload_cc_state_pointers,
 215 };