i965/gen6: Move the blend state to state streaming.
[mesa.git] / src / mesa / drivers / dri / i965 / gen6_cc.c
1 /*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
31 #include "brw_util.h"
32 #include "intel_batchbuffer.h"
33 #include "main/macros.h"
34
35 static void
36 prepare_blend_state(struct brw_context *brw)
37 {
38 struct gl_context *ctx = &brw->intel.ctx;
39 struct gen6_blend_state *blend;
40 int b;
41 int nr_draw_buffers = ctx->DrawBuffer->_NumColorDrawBuffers;
42 int size = sizeof(*blend) * nr_draw_buffers;
43
44 blend = brw_state_batch(brw, size, 64, &brw->cc.blend_state_offset);
45
46 memset(blend, 0, size);
47
48 for (b = 0; b < nr_draw_buffers; b++) {
49 /* _NEW_COLOR */
50 if (ctx->Color._LogicOpEnabled && ctx->Color.LogicOp != GL_COPY) {
51 blend[b].blend1.logic_op_enable = 1;
52 blend[b].blend1.logic_op_func =
53 intel_translate_logic_op(ctx->Color.LogicOp);
54 } else if (ctx->Color.BlendEnabled & (1 << b)) {
55 GLenum eqRGB = ctx->Color.Blend[0].EquationRGB;
56 GLenum eqA = ctx->Color.Blend[0].EquationA;
57 GLenum srcRGB = ctx->Color.Blend[0].SrcRGB;
58 GLenum dstRGB = ctx->Color.Blend[0].DstRGB;
59 GLenum srcA = ctx->Color.Blend[0].SrcA;
60 GLenum dstA = ctx->Color.Blend[0].DstA;
61
62 if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
63 srcRGB = dstRGB = GL_ONE;
64 }
65
66 if (eqA == GL_MIN || eqA == GL_MAX) {
67 srcA = dstA = GL_ONE;
68 }
69
70 blend[b].blend0.dest_blend_factor = brw_translate_blend_factor(dstRGB);
71 blend[b].blend0.source_blend_factor = brw_translate_blend_factor(srcRGB);
72 blend[b].blend0.blend_func = brw_translate_blend_equation(eqRGB);
73
74 blend[b].blend0.ia_dest_blend_factor = brw_translate_blend_factor(dstA);
75 blend[b].blend0.ia_source_blend_factor = brw_translate_blend_factor(srcA);
76 blend[b].blend0.ia_blend_func = brw_translate_blend_equation(eqA);
77
78 blend[b].blend0.blend_enable = 1;
79 blend[b].blend0.ia_blend_enable = (srcA != srcRGB ||
80 dstA != dstRGB ||
81 eqA != eqRGB);
82 }
83
84
85 /* _NEW_COLOR */
86 if (ctx->Color.AlphaEnabled) {
87 blend[b].blend1.alpha_test_enable = 1;
88 blend[b].blend1.alpha_test_func =
89 intel_translate_compare_func(ctx->Color.AlphaFunc);
90
91 }
92
93 /* _NEW_COLOR */
94 if (ctx->Color.DitherFlag) {
95 blend[b].blend1.dither_enable = 1;
96 blend[b].blend1.y_dither_offset = 0;
97 blend[b].blend1.x_dither_offset = 0;
98 }
99
100 blend[b].blend1.write_disable_r = !ctx->Color.ColorMask[b][0];
101 blend[b].blend1.write_disable_g = !ctx->Color.ColorMask[b][1];
102 blend[b].blend1.write_disable_b = !ctx->Color.ColorMask[b][2];
103 blend[b].blend1.write_disable_a = !ctx->Color.ColorMask[b][3];
104 }
105
106 brw->state.dirty.cache |= CACHE_NEW_BLEND_STATE;
107 }
108
109 const struct brw_tracked_state gen6_blend_state = {
110 .dirty = {
111 .mesa = _NEW_COLOR,
112 .brw = BRW_NEW_BATCH,
113 .cache = 0,
114 },
115 .prepare = prepare_blend_state,
116 };
117
118 static void
119 gen6_prepare_color_calc_state(struct brw_context *brw)
120 {
121 struct gl_context *ctx = &brw->intel.ctx;
122 struct gen6_color_calc_state *cc;
123
124 cc = brw_state_batch(brw, sizeof(*cc), 64, &brw->cc.state_offset);
125 memset(cc, 0, sizeof(*cc));
126
127 /* _NEW_COLOR */
128 cc->cc0.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
129 UNCLAMPED_FLOAT_TO_UBYTE(cc->cc1.alpha_ref_fi.ui, ctx->Color.AlphaRef);
130
131 /* _NEW_STENCIL */
132 cc->cc0.stencil_ref = ctx->Stencil.Ref[0];
133 cc->cc0.bf_stencil_ref = ctx->Stencil.Ref[ctx->Stencil._BackFace];
134
135 /* _NEW_COLOR */
136 cc->constant_r = ctx->Color.BlendColorUnclamped[0];
137 cc->constant_g = ctx->Color.BlendColorUnclamped[1];
138 cc->constant_b = ctx->Color.BlendColorUnclamped[2];
139 cc->constant_a = ctx->Color.BlendColorUnclamped[3];
140
141 brw->state.dirty.cache |= CACHE_NEW_COLOR_CALC_STATE;
142 }
143
144 const struct brw_tracked_state gen6_color_calc_state = {
145 .dirty = {
146 .mesa = _NEW_COLOR | _NEW_STENCIL,
147 .brw = BRW_NEW_BATCH,
148 .cache = 0,
149 },
150 .prepare = gen6_prepare_color_calc_state,
151 };
152
153 static void upload_cc_state_pointers(struct brw_context *brw)
154 {
155 struct intel_context *intel = &brw->intel;
156
157 BEGIN_BATCH(4);
158 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
159 OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
160 brw->cc.blend_state_offset | 1);
161 OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
162 OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
163 brw->cc.state_offset | 1);
164 ADVANCE_BATCH();
165 }
166
167
168 static void prepare_cc_state_pointers(struct brw_context *brw)
169 {
170 brw_add_validated_bo(brw, brw->cc.depth_stencil_state_bo);
171 }
172
173 const struct brw_tracked_state gen6_cc_state_pointers = {
174 .dirty = {
175 .mesa = 0,
176 .brw = BRW_NEW_BATCH,
177 .cache = (CACHE_NEW_BLEND_STATE |
178 CACHE_NEW_COLOR_CALC_STATE |
179 CACHE_NEW_DEPTH_STENCIL_STATE)
180 },
181 .prepare = prepare_cc_state_pointers,
182 .emit = upload_cc_state_pointers,
183 };