i965: Fix clears of layered framebuffers with mismatched layer counts.
[mesa.git] / src / mesa / drivers / dri / i965 / gen6_clip_state.c
1 /*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
31 #include "brw_util.h"
32 #include "intel_batchbuffer.h"
33 #include "main/fbobject.h"
34
35 static void
36 upload_clip_state(struct brw_context *brw)
37 {
38 struct gl_context *ctx = &brw->ctx;
39 /* BRW_NEW_META_IN_PROGRESS */
40 uint32_t dw1 = brw->meta_in_progress ? 0 : GEN6_CLIP_STATISTICS_ENABLE;
41 uint32_t dw2 = 0;
42
43 /* _NEW_BUFFERS */
44 struct gl_framebuffer *fb = ctx->DrawBuffer;
45
46 /* CACHE_NEW_WM_PROG */
47 if (brw->wm.prog_data->barycentric_interp_modes &
48 BRW_WM_NONPERSPECTIVE_BARYCENTRIC_BITS) {
49 dw2 |= GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE;
50 }
51
52 if (brw->gen >= 7) {
53 dw1 |= GEN7_CLIP_EARLY_CULL;
54
55 /* _NEW_POLYGON */
56 if ((ctx->Polygon.FrontFace == GL_CCW) ^ _mesa_is_user_fbo(fb))
57 dw1 |= GEN7_CLIP_WINDING_CCW;
58
59 if (ctx->Polygon.CullFlag) {
60 switch (ctx->Polygon.CullFaceMode) {
61 case GL_FRONT:
62 dw1 |= GEN7_CLIP_CULLMODE_FRONT;
63 break;
64 case GL_BACK:
65 dw1 |= GEN7_CLIP_CULLMODE_BACK;
66 break;
67 case GL_FRONT_AND_BACK:
68 dw1 |= GEN7_CLIP_CULLMODE_BOTH;
69 break;
70 default:
71 assert(!"Should not get here: invalid CullFlag");
72 break;
73 }
74 } else {
75 dw1 |= GEN7_CLIP_CULLMODE_NONE;
76 }
77 }
78
79 if (!ctx->Transform.DepthClamp)
80 dw2 |= GEN6_CLIP_Z_TEST;
81
82 /* _NEW_LIGHT */
83 if (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION) {
84 dw2 |=
85 (0 << GEN6_CLIP_TRI_PROVOKE_SHIFT) |
86 (1 << GEN6_CLIP_TRIFAN_PROVOKE_SHIFT) |
87 (0 << GEN6_CLIP_LINE_PROVOKE_SHIFT);
88 } else {
89 dw2 |=
90 (2 << GEN6_CLIP_TRI_PROVOKE_SHIFT) |
91 (2 << GEN6_CLIP_TRIFAN_PROVOKE_SHIFT) |
92 (1 << GEN6_CLIP_LINE_PROVOKE_SHIFT);
93 }
94
95 /* _NEW_TRANSFORM */
96 dw2 |= (ctx->Transform.ClipPlanesEnabled <<
97 GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT);
98
99 if (ctx->Viewport.X == 0 &&
100 ctx->Viewport.Y == 0 &&
101 ctx->Viewport.Width == fb->Width &&
102 ctx->Viewport.Height == fb->Height) {
103 dw2 |= GEN6_CLIP_GB_TEST;
104 }
105
106 /* BRW_NEW_RASTERIZER_DISCARD */
107 if (ctx->RasterDiscard) {
108 dw2 |= GEN6_CLIP_MODE_REJECT_ALL;
109 perf_debug("Rasterizer discard is currently implemented via the clipper; "
110 "%s be faster.", brw->gen >= 7 ? "using the SOL unit may" :
111 "having the GS not write primitives would likely");
112 }
113
114 BEGIN_BATCH(4);
115 OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2));
116 OUT_BATCH(dw1);
117 OUT_BATCH(GEN6_CLIP_ENABLE |
118 GEN6_CLIP_API_OGL |
119 GEN6_CLIP_MODE_NORMAL |
120 GEN6_CLIP_XY_TEST |
121 dw2);
122 OUT_BATCH(U_FIXED(0.125, 3) << GEN6_CLIP_MIN_POINT_WIDTH_SHIFT |
123 U_FIXED(255.875, 3) << GEN6_CLIP_MAX_POINT_WIDTH_SHIFT |
124 (fb->MaxNumLayers > 0 ? 0 : GEN6_CLIP_FORCE_ZERO_RTAINDEX));
125 ADVANCE_BATCH();
126 }
127
128 const struct brw_tracked_state gen6_clip_state = {
129 .dirty = {
130 .mesa = _NEW_TRANSFORM | _NEW_LIGHT | _NEW_BUFFERS,
131 .brw = BRW_NEW_CONTEXT |
132 BRW_NEW_META_IN_PROGRESS |
133 BRW_NEW_RASTERIZER_DISCARD,
134 .cache = CACHE_NEW_WM_PROG
135 },
136 .emit = upload_clip_state,
137 };
138
139 const struct brw_tracked_state gen7_clip_state = {
140 .dirty = {
141 .mesa = _NEW_BUFFERS | _NEW_LIGHT | _NEW_POLYGON | _NEW_TRANSFORM,
142 .brw = BRW_NEW_CONTEXT |
143 BRW_NEW_META_IN_PROGRESS |
144 BRW_NEW_RASTERIZER_DISCARD,
145 .cache = CACHE_NEW_WM_PROG
146 },
147 .emit = upload_clip_state,
148 };