src/mesa/drivers/dri/i965/gen6_depth_state.c

   1 /*
   2  * Copyright (c) 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24
  25 #include "intel_batchbuffer.h"
  26 #include "intel_fbo.h"
  27 #include "intel_mipmap_tree.h"
  28
  29 #include "brw_context.h"
  30 #include "brw_state.h"
  31 #include "brw_defines.h"
  32
  33 #include "main/mtypes.h"
  34 #include "main/fbobject.h"
  35 #include "main/glformats.h"
  36
  37 void
  38 gen6_emit_depth_stencil_hiz(struct brw_context *brw,
  39                             struct intel_mipmap_tree *depth_mt,
  40                             uint32_t depth_offset, uint32_t depthbuffer_format,
  41                             uint32_t depth_surface_type,
  42                             struct intel_mipmap_tree *stencil_mt,
  43                             bool hiz, bool separate_stencil,
  44                             uint32_t width, uint32_t height,
  45                             uint32_t tile_x, uint32_t tile_y)
  46 {
  47    struct gl_context *ctx = &brw->ctx;
  48    struct gl_framebuffer *fb = ctx->DrawBuffer;
  49    uint32_t surftype;
  50    unsigned int depth = 1;
  51    GLenum gl_target = GL_TEXTURE_2D;
  52    unsigned int lod;
  53    const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
  54    const struct intel_renderbuffer *irb = NULL;
  55    const struct gl_renderbuffer *rb = NULL;
  56
  57    /* Enable the hiz bit if we're doing separate stencil, because it and the
  58     * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
  59     * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
  60     *     [DevIL]: If this field is enabled, Hierarchical Depth Buffer
  61     *     Enable must also be enabled.
  62     *
  63     *     [DevGT]: This field must be set to the same value (enabled or
  64     *     disabled) as Hierarchical Depth Buffer Enable
  65     */
  66    bool enable_hiz_ss = hiz || separate_stencil;
  67
  68    brw_emit_depth_stall_flushes(brw);
  69
  70    irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
  71    if (!irb)
  72       irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
  73    rb = (struct gl_renderbuffer*) irb;
  74
  75    if (rb) {
  76       depth = MAX2(irb->layer_count, 1);
  77       if (rb->TexImage)
  78          gl_target = rb->TexImage->TexObject->Target;
  79    }
  80
  81    switch (gl_target) {
  82    case GL_TEXTURE_CUBE_MAP_ARRAY:
  83    case GL_TEXTURE_CUBE_MAP:
  84       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
  85        * situation, but experiments show that gl_Layer doesn't work when we do
  86        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
  87        * equivalent.
  88        */
  89       surftype = BRW_SURFACE_2D;
  90       depth *= 6;
  91       break;
  92    case GL_TEXTURE_3D:
  93       assert(mt);
  94       depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
  95                                   MAX2(mt->logical_depth0, 1);
  96       /* fallthrough */
  97    default:
  98       surftype = translate_tex_target(gl_target);
  99       break;
 100    }
 101
 102    const unsigned min_array_element = irb ? irb->mt_layer : 0;
 103
 104    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 105
 106    if (mt && mt->surf.size > 0) {
 107       width = mt->surf.logical_level0_px.width;
 108       height = mt->surf.logical_level0_px.height;
 109    } else if (mt) {
 110       width = mt->logical_width0;
 111       height = mt->logical_height0;
 112    }
 113
 114    BEGIN_BATCH(7);
 115    /* 3DSTATE_DEPTH_BUFFER dw0 */
 116    OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 117
 118    /* 3DSTATE_DEPTH_BUFFER dw1 */
 119    OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
 120              (depthbuffer_format << 18) |
 121              ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */
 122              ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
 123              (BRW_TILEWALK_YMAJOR << 26) |
 124              ((depth_mt ? depth_mt->tiling != I915_TILING_NONE : 1)
 125               << 27) |
 126              (surftype << 29));
 127
 128    /* 3DSTATE_DEPTH_BUFFER dw2 */
 129    if (depth_mt) {
 130       OUT_RELOC(depth_mt->bo,
 131                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 132                 0);
 133    } else {
 134       OUT_BATCH(0);
 135    }
 136
 137    /* 3DSTATE_DEPTH_BUFFER dw3 */
 138    OUT_BATCH(((width - 1) << 6) |
 139              ((height - 1) << 19) |
 140              lod << 2);
 141
 142    /* 3DSTATE_DEPTH_BUFFER dw4 */
 143    OUT_BATCH((depth - 1) << 21 |
 144              min_array_element << 10 |
 145              (depth - 1) << 1);
 146
 147    /* 3DSTATE_DEPTH_BUFFER dw5 */
 148    OUT_BATCH(0);
 149    assert(tile_x == 0 && tile_y == 0);
 150
 151    /* 3DSTATE_DEPTH_BUFFER dw6 */
 152    OUT_BATCH(0);
 153
 154    ADVANCE_BATCH();
 155
 156    if (hiz || separate_stencil) {
 157       /*
 158        * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
 159        * stencil enable' and 'hiz enable' bits were set. Therefore we must
 160        * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
 161        * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
 162        * failure to do so causes hangs on gen5 and a stall on gen6.
 163        */
 164
 165       /* Emit hiz buffer. */
 166       if (hiz) {
 167          assert(depth_mt);
 168
 169          uint32_t offset;
 170          isl_surf_get_image_offset_B_tile_sa(&depth_mt->hiz_buf->surf,
 171                                              lod, 0, 0, &offset, NULL, NULL);
 172
 173          BEGIN_BATCH(3);
 174          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 175          OUT_BATCH(depth_mt->hiz_buf->surf.row_pitch - 1);
 176          OUT_RELOC(depth_mt->hiz_buf->bo,
 177                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 178                    offset);
 179          ADVANCE_BATCH();
 180       } else {
 181          BEGIN_BATCH(3);
 182          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 183          OUT_BATCH(0);
 184          OUT_BATCH(0);
 185          ADVANCE_BATCH();
 186       }
 187
 188       /* Emit stencil buffer. */
 189       if (separate_stencil) {
 190          assert(stencil_mt->format == MESA_FORMAT_S_UINT8);
 191          assert(stencil_mt->surf.size > 0);
 192
 193          uint32_t offset;
 194          isl_surf_get_image_offset_B_tile_sa(&stencil_mt->surf,
 195                                              lod, 0, 0, &offset, NULL, NULL);
 196
 197          BEGIN_BATCH(3);
 198          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 199          OUT_BATCH(stencil_mt->surf.row_pitch - 1);
 200          OUT_RELOC(stencil_mt->bo,
 201                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 202                    offset);
 203          ADVANCE_BATCH();
 204       } else {
 205          BEGIN_BATCH(3);
 206          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 207          OUT_BATCH(0);
 208          OUT_BATCH(0);
 209          ADVANCE_BATCH();
 210       }
 211    }
 212
 213    /*
 214     * On Gen >= 6, emit clear params for safety. If using hiz, then clear
 215     * params must be emitted.
 216     *
 217     * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
 218     *     3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
 219     *     when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
 220     */
 221    BEGIN_BATCH(2);
 222    OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
 223              GEN5_DEPTH_CLEAR_VALID |
 224              (2 - 2));
 225    if (depth_mt) {
 226       OUT_BATCH(brw_convert_depth_value(depth_mt->format,
 227                                         depth_mt->fast_clear_color.f32[0]));
 228    } else {
 229       OUT_BATCH(0);
 230    }
 231    ADVANCE_BATCH();
 232 }