src/mesa/drivers/dri/i965/gen6_depth_state.c

   1 /*
   2  * Copyright (c) 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24
  25 #include "intel_batchbuffer.h"
  26 #include "intel_fbo.h"
  27 #include "intel_mipmap_tree.h"
  28
  29 #include "brw_context.h"
  30 #include "brw_state.h"
  31 #include "brw_defines.h"
  32
  33 #include "main/mtypes.h"
  34 #include "main/fbobject.h"
  35 #include "main/glformats.h"
  36
  37 void
  38 gen6_emit_depth_stencil_hiz(struct brw_context *brw,
  39                             struct intel_mipmap_tree *depth_mt,
  40                             uint32_t depth_offset, uint32_t depthbuffer_format,
  41                             uint32_t depth_surface_type,
  42                             struct intel_mipmap_tree *stencil_mt,
  43                             bool hiz, bool separate_stencil,
  44                             uint32_t width, uint32_t height,
  45                             uint32_t tile_x, uint32_t tile_y)
  46 {
  47    struct gl_context *ctx = &brw->ctx;
  48    struct gl_framebuffer *fb = ctx->DrawBuffer;
  49    uint32_t surftype;
  50    unsigned int depth = 1;
  51    GLenum gl_target = GL_TEXTURE_2D;
  52    unsigned int lod;
  53    const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
  54    const struct intel_renderbuffer *irb = NULL;
  55    const struct gl_renderbuffer *rb = NULL;
  56
  57    /* Enable the hiz bit if we're doing separate stencil, because it and the
  58     * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
  59     * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
  60     *     [DevIL]: If this field is enabled, Hierarchical Depth Buffer
  61     *     Enable must also be enabled.
  62     *
  63     *     [DevGT]: This field must be set to the same value (enabled or
  64     *     disabled) as Hierarchical Depth Buffer Enable
  65     */
  66    bool enable_hiz_ss = hiz || separate_stencil;
  67
  68
  69    /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
  70     * non-pipelined state that will need the PIPE_CONTROL workaround.
  71     */
  72    intel_emit_post_sync_nonzero_flush(brw);
  73    intel_emit_depth_stall_flushes(brw);
  74
  75    irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
  76    if (!irb)
  77       irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
  78    rb = (struct gl_renderbuffer*) irb;
  79
  80    if (rb) {
  81       depth = MAX2(rb->Depth, 1);
  82       if (rb->TexImage)
  83          gl_target = rb->TexImage->TexObject->Target;
  84    }
  85
  86    switch (gl_target) {
  87    case GL_TEXTURE_CUBE_MAP_ARRAY:
  88    case GL_TEXTURE_CUBE_MAP:
  89       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
  90        * situation, but experiments show that gl_Layer doesn't work when we do
  91        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
  92        * equivalent.
  93        */
  94       surftype = BRW_SURFACE_2D;
  95       depth *= 6;
  96       break;
  97    default:
  98       surftype = translate_tex_target(gl_target);
  99       break;
 100    }
 101
 102    const unsigned min_array_element = irb ? irb->mt_layer : 0;
 103
 104    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 105
 106    if (mt) {
 107       width = mt->logical_width0;
 108       height = mt->logical_height0;
 109    }
 110
 111    BEGIN_BATCH(7);
 112    /* 3DSTATE_DEPTH_BUFFER dw0 */
 113    OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 114
 115    /* 3DSTATE_DEPTH_BUFFER dw1 */
 116    OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
 117              (depthbuffer_format << 18) |
 118              ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */
 119              ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
 120              (BRW_TILEWALK_YMAJOR << 26) |
 121              ((depth_mt ? depth_mt->tiling != I915_TILING_NONE : 1)
 122               << 27) |
 123              (surftype << 29));
 124
 125    /* 3DSTATE_DEPTH_BUFFER dw2 */
 126    if (depth_mt) {
 127       OUT_RELOC(depth_mt->bo,
 128                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 129                 0);
 130    } else {
 131       OUT_BATCH(0);
 132    }
 133
 134    /* 3DSTATE_DEPTH_BUFFER dw3 */
 135    OUT_BATCH(((width - 1) << 6) |
 136              ((height - 1) << 19) |
 137              lod << 2);
 138
 139    /* 3DSTATE_DEPTH_BUFFER dw4 */
 140    OUT_BATCH((depth - 1) << 21 |
 141              min_array_element << 10 |
 142              (depth - 1) << 1);
 143
 144    /* 3DSTATE_DEPTH_BUFFER dw5 */
 145    OUT_BATCH(0);
 146    assert(tile_x == 0 && tile_y == 0);
 147
 148    /* 3DSTATE_DEPTH_BUFFER dw6 */
 149    OUT_BATCH(0);
 150
 151    ADVANCE_BATCH();
 152
 153    if (hiz || separate_stencil) {
 154       /*
 155        * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
 156        * stencil enable' and 'hiz enable' bits were set. Therefore we must
 157        * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
 158        * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
 159        * failure to do so causes hangs on gen5 and a stall on gen6.
 160        */
 161
 162       /* Emit hiz buffer. */
 163       if (hiz) {
 164          struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
 165          uint32_t offset = 0;
 166
 167          if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 168             offset = intel_miptree_get_aligned_offset(
 169                         hiz_mt,
 170                         hiz_mt->level[lod].level_x,
 171                         hiz_mt->level[lod].level_y,
 172                         false);
 173          }
 174
 175          BEGIN_BATCH(3);
 176          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 177          OUT_BATCH(hiz_mt->pitch - 1);
 178          OUT_RELOC(hiz_mt->bo,
 179                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 180                    offset);
 181          ADVANCE_BATCH();
 182       } else {
 183          BEGIN_BATCH(3);
 184          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 185          OUT_BATCH(0);
 186          OUT_BATCH(0);
 187          ADVANCE_BATCH();
 188       }
 189
 190       /* Emit stencil buffer. */
 191       if (separate_stencil) {
 192          uint32_t offset = 0;
 193
 194          if (stencil_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 195             if (stencil_mt->format == MESA_FORMAT_S_UINT8) {
 196                /* Note: we can't compute the stencil offset using
 197                 * intel_region_get_aligned_offset(), because stencil_region
 198                 * claims that the region is untiled even though it's W tiled.
 199                 */
 200                offset =
 201                   stencil_mt->level[lod].level_y * stencil_mt->pitch +
 202                   stencil_mt->level[lod].level_x * 64;
 203             } else {
 204                offset = intel_miptree_get_aligned_offset(
 205                            stencil_mt,
 206                            stencil_mt->level[lod].level_x,
 207                            stencil_mt->level[lod].level_y,
 208                            false);
 209             }
 210          }
 211
 212          BEGIN_BATCH(3);
 213          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 214          /* The stencil buffer has quirky pitch requirements.  From Vol 2a,
 215           * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
 216           *    The pitch must be set to 2x the value computed based on width, as
 217           *    the stencil buffer is stored with two rows interleaved.
 218           */
 219          OUT_BATCH(2 * stencil_mt->pitch - 1);
 220          OUT_RELOC(stencil_mt->bo,
 221                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 222                    offset);
 223          ADVANCE_BATCH();
 224       } else {
 225          BEGIN_BATCH(3);
 226          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 227          OUT_BATCH(0);
 228          OUT_BATCH(0);
 229          ADVANCE_BATCH();
 230       }
 231    }
 232
 233    /*
 234     * On Gen >= 6, emit clear params for safety. If using hiz, then clear
 235     * params must be emitted.
 236     *
 237     * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
 238     *     3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
 239     *     when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
 240     */
 241    intel_emit_post_sync_nonzero_flush(brw);
 242
 243    BEGIN_BATCH(2);
 244    OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
 245              GEN5_DEPTH_CLEAR_VALID |
 246              (2 - 2));
 247    OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
 248    ADVANCE_BATCH();
 249 }