src/mesa/drivers/dri/i965/gen6_depthstencil.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "intel_batchbuffer.h"
  29 #include "intel_fbo.h"
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 static void
  35 gen6_upload_depth_stencil_state(struct brw_context *brw)
  36 {
  37    struct gl_context *ctx = &brw->intel.ctx;
  38    struct intel_context *intel = &brw->intel;
  39    struct gen6_depth_stencil_state *ds;
  40    struct intel_renderbuffer *depth_irb;
  41
  42    /* _NEW_BUFFERS */
  43    depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
  44
  45    ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
  46                         sizeof(*ds), 64,
  47                         &brw->cc.depth_stencil_state_offset);
  48    memset(ds, 0, sizeof(*ds));
  49
  50    /* _NEW_STENCIL | _NEW_BUFFERS */
  51    if (ctx->Stencil._Enabled) {
  52       int back = ctx->Stencil._BackFace;
  53
  54       ds->ds0.stencil_enable = 1;
  55       ds->ds0.stencil_func =
  56          intel_translate_compare_func(ctx->Stencil.Function[0]);
  57       ds->ds0.stencil_fail_op =
  58          intel_translate_stencil_op(ctx->Stencil.FailFunc[0]);
  59       ds->ds0.stencil_pass_depth_fail_op =
  60          intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]);
  61       ds->ds0.stencil_pass_depth_pass_op =
  62          intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]);
  63       ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0];
  64       ds->ds1.stencil_test_mask = ctx->Stencil.ValueMask[0];
  65
  66       if (ctx->Stencil._TestTwoSide) {
  67          ds->ds0.bf_stencil_enable = 1;
  68          ds->ds0.bf_stencil_func =
  69             intel_translate_compare_func(ctx->Stencil.Function[back]);
  70          ds->ds0.bf_stencil_fail_op =
  71             intel_translate_stencil_op(ctx->Stencil.FailFunc[back]);
  72          ds->ds0.bf_stencil_pass_depth_fail_op =
  73             intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]);
  74          ds->ds0.bf_stencil_pass_depth_pass_op =
  75             intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]);
  76          ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
  77          ds->ds1.bf_stencil_test_mask = ctx->Stencil.ValueMask[back];
  78       }
  79
  80       ds->ds0.stencil_write_enable = ctx->Stencil._WriteEnabled;
  81    }
  82
  83    /* _NEW_DEPTH */
  84    if (ctx->Depth.Test && depth_irb) {
  85       ds->ds2.depth_test_enable = ctx->Depth.Test;
  86       ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func);
  87       ds->ds2.depth_write_enable = ctx->Depth.Mask;
  88    }
  89
  90    /* Point the GPU at the new indirect state. */
  91    if (intel->gen == 6) {
  92       BEGIN_BATCH(4);
  93       OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
  94       OUT_BATCH(0);
  95       OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
  96       OUT_BATCH(0);
  97       ADVANCE_BATCH();
  98    } else {
  99       BEGIN_BATCH(2);
 100       OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 101       OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
 102       ADVANCE_BATCH();
 103    }
 104 }
 105
 106 const struct brw_tracked_state gen6_depth_stencil_state = {
 107    .dirty = {
 108       .mesa = _NEW_DEPTH | _NEW_STENCIL | _NEW_BUFFERS,
 109       .brw  = BRW_NEW_BATCH | BRW_NEW_STATE_BASE_ADDRESS,
 110       .cache = 0,
 111    },
 112    .emit = gen6_upload_depth_stencil_state,
 113 };