src/mesa/drivers/dri/i965/gen6_depthstencil.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30
  31 static void
  32 gen6_upload_depth_stencil_state(struct brw_context *brw)
  33 {
  34    struct gl_context *ctx = &brw->intel.ctx;
  35    struct gen6_depth_stencil_state *ds;
  36
  37    ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
  38                         sizeof(*ds), 64,
  39                         &brw->cc.depth_stencil_state_offset);
  40    memset(ds, 0, sizeof(*ds));
  41
  42    /* _NEW_STENCIL */
  43    if (ctx->Stencil._Enabled) {
  44       int back = ctx->Stencil._BackFace;
  45
  46       ds->ds0.stencil_enable = 1;
  47       ds->ds0.stencil_func =
  48          intel_translate_compare_func(ctx->Stencil.Function[0]);
  49       ds->ds0.stencil_fail_op =
  50          intel_translate_stencil_op(ctx->Stencil.FailFunc[0]);
  51       ds->ds0.stencil_pass_depth_fail_op =
  52          intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]);
  53       ds->ds0.stencil_pass_depth_pass_op =
  54          intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]);
  55       ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0];
  56       ds->ds1.stencil_test_mask = ctx->Stencil.ValueMask[0];
  57
  58       if (ctx->Stencil._TestTwoSide) {
  59          ds->ds0.bf_stencil_enable = 1;
  60          ds->ds0.bf_stencil_func =
  61             intel_translate_compare_func(ctx->Stencil.Function[back]);
  62          ds->ds0.bf_stencil_fail_op =
  63             intel_translate_stencil_op(ctx->Stencil.FailFunc[back]);
  64          ds->ds0.bf_stencil_pass_depth_fail_op =
  65             intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]);
  66          ds->ds0.bf_stencil_pass_depth_pass_op =
  67             intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]);
  68          ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
  69          ds->ds1.bf_stencil_test_mask = ctx->Stencil.ValueMask[back];
  70       }
  71
  72       /* Not really sure about this:
  73        */
  74       if (ctx->Stencil.WriteMask[0] ||
  75           (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back]))
  76          ds->ds0.stencil_write_enable = 1;
  77    }
  78
  79    /* _NEW_DEPTH */
  80    if (ctx->Depth.Test || brw->hiz.op) {
  81       assert(brw->hiz.op != BRW_HIZ_OP_DEPTH_RESOLVE || ctx->Depth.Test);
  82       assert(brw->hiz.op != BRW_HIZ_OP_HIZ_RESOLVE   || !ctx->Depth.Test);
  83       assert(brw->hiz.op != BRW_HIZ_OP_DEPTH_CLEAR   || !ctx->Depth.Test);
  84
  85       ds->ds2.depth_test_enable = ctx->Depth.Test;
  86       ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func);
  87       ds->ds2.depth_write_enable = ctx->Depth.Mask;
  88    }
  89
  90    brw->state.dirty.cache |= CACHE_NEW_DEPTH_STENCIL_STATE;
  91 }
  92
  93 const struct brw_tracked_state gen6_depth_stencil_state = {
  94    .dirty = {
  95       .mesa = _NEW_DEPTH | _NEW_STENCIL,
  96       .brw  = (BRW_NEW_BATCH |
  97                BRW_NEW_HIZ),
  98       .cache = 0,
  99    },
 100    .emit = gen6_upload_depth_stencil_state,
 101 };