0b718c9a87f701acfcb4bcf7ac3d209ae891aaf4
[mesa.git] / src / mesa / drivers / dri / i965 / gen6_gs_state.c
1 /*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
31 #include "intel_batchbuffer.h"
32
33 static void
34 upload_gs_state_for_tf(struct brw_context *brw)
35 {
36 BEGIN_BATCH(7);
37 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
38 OUT_BATCH(brw->ff_gs.prog_offset);
39 OUT_BATCH(GEN6_GS_SPF_MODE | GEN6_GS_VECTOR_MASK_ENABLE);
40 OUT_BATCH(0); /* no scratch space */
41 OUT_BATCH((2 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
42 (brw->ff_gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT));
43 OUT_BATCH(((brw->max_gs_threads - 1) << GEN6_GS_MAX_THREADS_SHIFT) |
44 GEN6_GS_STATISTICS_ENABLE |
45 GEN6_GS_SO_STATISTICS_ENABLE |
46 GEN6_GS_RENDERING_ENABLE);
47 OUT_BATCH(GEN6_GS_SVBI_PAYLOAD_ENABLE |
48 GEN6_GS_SVBI_POSTINCREMENT_ENABLE |
49 (brw->ff_gs.prog_data->svbi_postincrement_value <<
50 GEN6_GS_SVBI_POSTINCREMENT_VALUE_SHIFT) |
51 GEN6_GS_ENABLE);
52 ADVANCE_BATCH();
53 }
54
55 static void
56 upload_gs_state(struct brw_context *brw)
57 {
58 /* BRW_NEW_GEOMETRY_PROGRAM */
59 bool active = brw->geometry_program;
60 /* CACHE_NEW_GS_PROG */
61 const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base;
62 const struct brw_stage_state *stage_state = &brw->gs.base;
63
64 if (active) {
65 /* FIXME: enable constant buffers */
66 BEGIN_BATCH(5);
67 OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (5 - 2));
68 OUT_BATCH(0);
69 OUT_BATCH(0);
70 OUT_BATCH(0);
71 OUT_BATCH(0);
72 ADVANCE_BATCH();
73
74 BEGIN_BATCH(7);
75 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
76 OUT_BATCH(stage_state->prog_offset);
77
78 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
79 * was previously done for gen6.
80 *
81 * TODO: test with both disabled to see if the HW is behaving
82 * as expected, like in gen7.
83 */
84 OUT_BATCH(GEN6_GS_SPF_MODE | GEN6_GS_VECTOR_MASK_ENABLE |
85 ((ALIGN(stage_state->sampler_count, 4)/4) <<
86 GEN6_GS_SAMPLER_COUNT_SHIFT) |
87 ((prog_data->base.binding_table.size_bytes / 4) <<
88 GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
89
90 if (prog_data->base.total_scratch) {
91 OUT_RELOC(stage_state->scratch_bo,
92 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
93 ffs(prog_data->base.total_scratch) - 11);
94 } else {
95 OUT_BATCH(0); /* no scratch space */
96 }
97
98 OUT_BATCH((prog_data->urb_read_length <<
99 GEN6_GS_URB_READ_LENGTH_SHIFT) |
100 (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) |
101 (prog_data->base.dispatch_grf_start_reg <<
102 GEN6_GS_DISPATCH_START_GRF_SHIFT));
103
104 OUT_BATCH(((brw->max_gs_threads - 1) << GEN6_GS_MAX_THREADS_SHIFT) |
105 GEN6_GS_STATISTICS_ENABLE |
106 GEN6_GS_SO_STATISTICS_ENABLE |
107 GEN6_GS_RENDERING_ENABLE);
108
109 /* FIXME: Enable SVBI payload only when TF is enable in SNB for
110 * user-provided GS.
111 */
112 if (0) {
113 /* GEN6_GS_REORDER is equivalent to GEN7_GS_REORDER_TRAILING
114 * in gen7. SNB and IVB specs are the same regarding the reordering of
115 * TRISTRIP/TRISTRIP_REV vertices and triangle orientation, so we do
116 * the same thing in both generations. For more details, see the
117 * comment in gen7_gs_state.c
118 */
119 OUT_BATCH(GEN6_GS_REORDER |
120 GEN6_GS_SVBI_PAYLOAD_ENABLE |
121 GEN6_GS_SVBI_POSTINCREMENT_ENABLE |
122 /* FIXME: prog_data->svbi_postincrement_value instead of 0 */
123 (0 << GEN6_GS_SVBI_POSTINCREMENT_VALUE_SHIFT) |
124 GEN6_GS_ENABLE);
125 } else {
126 OUT_BATCH(GEN6_GS_REORDER | GEN6_GS_ENABLE);
127 }
128 ADVANCE_BATCH();
129 } else {
130 /* Disable all the constant buffers. */
131 BEGIN_BATCH(5);
132 OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (5 - 2));
133 OUT_BATCH(0);
134 OUT_BATCH(0);
135 OUT_BATCH(0);
136 OUT_BATCH(0);
137 ADVANCE_BATCH();
138
139 if (brw->ff_gs.prog_active) {
140 /* In gen6, transform feedback for the VS stage is done with an ad-hoc GS
141 * program. This function provides the needed 3DSTATE_GS for this.
142 */
143 upload_gs_state_for_tf(brw);
144 } else {
145 /* No GS function required */
146 BEGIN_BATCH(7);
147 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
148 OUT_BATCH(0); /* prog_bo */
149 OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
150 (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
151 OUT_BATCH(0); /* scratch space base offset */
152 OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
153 (0 << GEN6_GS_URB_READ_LENGTH_SHIFT) |
154 (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
155 OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
156 GEN6_GS_STATISTICS_ENABLE |
157 GEN6_GS_RENDERING_ENABLE);
158 OUT_BATCH(0);
159 ADVANCE_BATCH();
160 }
161 }
162 brw->gs.enabled = active;
163 }
164
165 const struct brw_tracked_state gen6_gs_state = {
166 .dirty = {
167 .mesa = _NEW_TRANSFORM,
168 .brw = BRW_NEW_CONTEXT | BRW_NEW_PUSH_CONSTANT_ALLOCATION,
169 .cache = (CACHE_NEW_GS_PROG | CACHE_NEW_FF_GS_PROG)
170 },
171 .emit = upload_gs_state,
172 };