b8201a6767b63b3452a5c92cd82c37563d5ce5bd
[mesa.git] / src / mesa / drivers / dri / i965 / gen6_multisample_state.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "intel_batchbuffer.h"
25
26 #include "brw_context.h"
27 #include "brw_defines.h"
28
29
30 /**
31 * 3DSTATE_MULTISAMPLE
32 */
33 void
34 gen6_emit_3dstate_multisample(struct brw_context *brw,
35 unsigned num_samples)
36 {
37 struct intel_context *intel = &brw->intel;
38
39 uint32_t number_of_multisamples = 0;
40 uint32_t sample_positions_3210 = 0;
41 uint32_t sample_positions_7654 = 0;
42
43 switch (num_samples) {
44 case 0:
45 number_of_multisamples = MS_NUMSAMPLES_1;
46 break;
47 case 4:
48 number_of_multisamples = MS_NUMSAMPLES_4;
49 /* Sample positions:
50 * 2 6 a e
51 * 2 0
52 * 6 1
53 * a 2
54 * e 3
55 */
56 sample_positions_3210 = 0xae2ae662;
57 break;
58 case 8:
59 number_of_multisamples = MS_NUMSAMPLES_8;
60 /* Sample positions are based on a solution to the "8 queens" puzzle.
61 * Rationale: in a solution to the 8 queens puzzle, no two queens share
62 * a row, column, or diagonal. This is a desirable property for samples
63 * in a multisampling pattern, because it ensures that the samples are
64 * relatively uniformly distributed through the pixel.
65 *
66 * There are several solutions to the 8 queens puzzle (see
67 * http://en.wikipedia.org/wiki/Eight_queens_puzzle). This solution was
68 * chosen because it has a queen close to the center; this should
69 * improve the accuracy of centroid interpolation, since the hardware
70 * implements centroid interpolation by choosing the centermost sample
71 * that overlaps with the primitive being drawn.
72 *
73 * Note: from the Ivy Bridge PRM, Vol2 Part1 p304 (3DSTATE_MULTISAMPLE:
74 * Programming Notes):
75 *
76 * "When programming the sample offsets (for NUMSAMPLES_4 or _8 and
77 * MSRASTMODE_xxx_PATTERN), the order of the samples 0 to 3 (or 7
78 * for 8X) must have monotonically increasing distance from the
79 * pixel center. This is required to get the correct centroid
80 * computation in the device."
81 *
82 * Sample positions:
83 * 1 3 5 7 9 b d f
84 * 1 5
85 * 3 2
86 * 5 6
87 * 7 4
88 * 9 0
89 * b 3
90 * d 1
91 * f 7
92 */
93 sample_positions_3210 = 0xdbb39d79;
94 sample_positions_7654 = 0x3ff55117;
95 break;
96 default:
97 assert(!"Unrecognized num_samples in gen6_emit_3dstate_multisample");
98 break;
99 }
100
101 int len = intel->gen >= 7 ? 4 : 3;
102 BEGIN_BATCH(len);
103 OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2));
104 OUT_BATCH(MS_PIXEL_LOCATION_CENTER | number_of_multisamples);
105 OUT_BATCH(sample_positions_3210);
106 if (intel->gen >= 7)
107 OUT_BATCH(sample_positions_7654);
108 ADVANCE_BATCH();
109 }
110
111
112 /**
113 * 3DSTATE_SAMPLE_MASK
114 */
115 void
116 gen6_emit_3dstate_sample_mask(struct brw_context *brw,
117 unsigned num_samples, float coverage,
118 bool coverage_invert)
119 {
120 struct intel_context *intel = &brw->intel;
121
122 /* TODO: 8x MSAA not implemented */
123 assert(num_samples <= 4);
124
125 BEGIN_BATCH(2);
126 OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2));
127 if (num_samples > 0) {
128 int coverage_int = (int) (num_samples * coverage + 0.5);
129 uint32_t coverage_bits = (1 << coverage_int) - 1;
130 if (coverage_invert)
131 coverage_bits ^= (1 << num_samples) - 1;
132 OUT_BATCH(coverage_bits);
133 } else {
134 OUT_BATCH(1);
135 }
136 ADVANCE_BATCH();
137 }
138
139
140 static void upload_multisample_state(struct brw_context *brw)
141 {
142 struct intel_context *intel = &brw->intel;
143 struct gl_context *ctx = &intel->ctx;
144 float coverage = 1.0;
145 float coverage_invert = false;
146
147 /* _NEW_BUFFERS */
148 unsigned num_samples = ctx->DrawBuffer->Visual.samples;
149
150 /* _NEW_MULTISAMPLE */
151 if (ctx->Multisample._Enabled && ctx->Multisample.SampleCoverage) {
152 coverage = ctx->Multisample.SampleCoverageValue;
153 coverage_invert = ctx->Multisample.SampleCoverageInvert;
154 }
155
156 /* 3DSTATE_MULTISAMPLE is nonpipelined. */
157 intel_emit_post_sync_nonzero_flush(intel);
158
159 gen6_emit_3dstate_multisample(brw, num_samples);
160 gen6_emit_3dstate_sample_mask(brw, num_samples, coverage, coverage_invert);
161 }
162
163
164 const struct brw_tracked_state gen6_multisample_state = {
165 .dirty = {
166 .mesa = _NEW_BUFFERS |
167 _NEW_MULTISAMPLE,
168 .brw = BRW_NEW_CONTEXT,
169 .cache = 0
170 },
171 .emit = upload_multisample_state
172 };