i965/nir/vec4: Implement load_const intrinsic
[mesa.git] / src / mesa / drivers / dri / i965 / gen6_scissor_state.c
1 /*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
31 #include "intel_batchbuffer.h"
32 #include "main/fbobject.h"
33 #include "main/framebuffer.h"
34
35 static void
36 gen6_upload_scissor_state(struct brw_context *brw)
37 {
38 struct gl_context *ctx = &brw->ctx;
39 const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
40 struct gen6_scissor_rect *scissor;
41 uint32_t scissor_state_offset;
42 const unsigned int fb_width= _mesa_geometric_width(ctx->DrawBuffer);
43 const unsigned int fb_height = _mesa_geometric_height(ctx->DrawBuffer);
44
45 scissor = brw_state_batch(brw, AUB_TRACE_SCISSOR_STATE,
46 sizeof(*scissor) * ctx->Const.MaxViewports, 32,
47 &scissor_state_offset);
48
49 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
50
51 /* The scissor only needs to handle the intersection of drawable and
52 * scissor rect. Clipping to the boundaries of static shared buffers
53 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
54 *
55 * Note that the hardware's coordinates are inclusive, while Mesa's min is
56 * inclusive but max is exclusive.
57 */
58 for (unsigned i = 0; i < ctx->Const.MaxViewports; i++) {
59 int bbox[4];
60
61 bbox[0] = 0;
62 bbox[1] = fb_width;
63 bbox[2] = 0;
64 bbox[3] = fb_height;
65 _mesa_intersect_scissor_bounding_box(ctx, i, bbox);
66
67 if (bbox[0] == bbox[1] || bbox[2] == bbox[3]) {
68 /* If the scissor was out of bounds and got clamped to 0 width/height
69 * at the bounds, the subtraction of 1 from maximums could produce a
70 * negative number and thus not clip anything. Instead, just provide
71 * a min > max scissor inside the bounds, which produces the expected
72 * no rendering.
73 */
74 scissor[i].xmin = 1;
75 scissor[i].xmax = 0;
76 scissor[i].ymin = 1;
77 scissor[i].ymax = 0;
78 } else if (render_to_fbo) {
79 /* texmemory: Y=0=bottom */
80 scissor[i].xmin = bbox[0];
81 scissor[i].xmax = bbox[1] - 1;
82 scissor[i].ymin = bbox[2];
83 scissor[i].ymax = bbox[3] - 1;
84 }
85 else {
86 /* memory: Y=0=top */
87 scissor[i].xmin = bbox[0];
88 scissor[i].xmax = bbox[1] - 1;
89 scissor[i].ymin = fb_height - bbox[3];
90 scissor[i].ymax = fb_height - bbox[2] - 1;
91 }
92 }
93 BEGIN_BATCH(2);
94 OUT_BATCH(_3DSTATE_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
95 OUT_BATCH(scissor_state_offset);
96 ADVANCE_BATCH();
97 }
98
99 const struct brw_tracked_state gen6_scissor_state = {
100 .dirty = {
101 .mesa = _NEW_BUFFERS |
102 _NEW_SCISSOR |
103 _NEW_VIEWPORT,
104 .brw = BRW_NEW_BATCH,
105 },
106 .emit = gen6_upload_scissor_state,
107 };