src/mesa/drivers/dri/i965/gen6_scissor_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "intel_batchbuffer.h"
  32
  33 static void
  34 prepare_scissor_state(struct brw_context *brw)
  35 {
  36    struct gl_context *ctx = &brw->intel.ctx;
  37    const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
  38    struct gen6_scissor_rect scissor;
  39
  40    /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
  41
  42    /* The scissor only needs to handle the intersection of drawable and
  43     * scissor rect.  Clipping to the boundaries of static shared buffers
  44     * for front/back/depth is covered by looping over cliprects in brw_draw.c.
  45     *
  46     * Note that the hardware's coordinates are inclusive, while Mesa's min is
  47     * inclusive but max is exclusive.
  48     */
  49    if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax ||
  50        ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) {
  51       /* If the scissor was out of bounds and got clamped to 0
  52        * width/height at the bounds, the subtraction of 1 from
  53        * maximums could produce a negative number and thus not clip
  54        * anything.  Instead, just provide a min > max scissor inside
  55        * the bounds, which produces the expected no rendering.
  56        */
  57       scissor.xmin = 1;
  58       scissor.xmax = 0;
  59       scissor.ymin = 1;
  60       scissor.ymax = 0;
  61    } else if (render_to_fbo) {
  62       /* texmemory: Y=0=bottom */
  63       scissor.xmin = ctx->DrawBuffer->_Xmin;
  64       scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
  65       scissor.ymin = ctx->DrawBuffer->_Ymin;
  66       scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
  67    }
  68    else {
  69       /* memory: Y=0=top */
  70       scissor.xmin = ctx->DrawBuffer->_Xmin;
  71       scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
  72       scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
  73       scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
  74    }
  75
  76    drm_intel_bo_unreference(brw->sf.state_bo);
  77    brw->sf.state_bo = brw_cache_data(&brw->cache, BRW_SF_UNIT,
  78                                      &scissor, sizeof(scissor));
  79 }
  80
  81 const struct brw_tracked_state gen6_scissor_state = {
  82    .dirty = {
  83       .mesa = _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT,
  84       .brw = 0,
  85       .cache = 0,
  86    },
  87    .prepare = prepare_scissor_state,
  88 };
  89
  90 static void upload_scissor_state_pointers(struct brw_context *brw)
  91 {
  92    struct intel_context *intel = &brw->intel;
  93
  94    BEGIN_BATCH(2);
  95    OUT_BATCH(CMD_3D_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
  96    OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
  97    ADVANCE_BATCH();
  98
  99 }
 100
 101
 102 static void prepare_scissor_state_pointers(struct brw_context *brw)
 103 {
 104    brw_add_validated_bo(brw, brw->sf.state_bo);
 105 }
 106
 107 const struct brw_tracked_state gen6_scissor_state_pointers = {
 108    .dirty = {
 109       .mesa = 0,
 110       .brw = BRW_NEW_BATCH,
 111       .cache = CACHE_NEW_SF_UNIT
 112    },
 113    .prepare = prepare_scissor_state_pointers,
 114    .emit = upload_scissor_state_pointers,
 115 };