src/mesa/drivers/dri/i965/gen6_sf_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "main/macros.h"
  33 #include "intel_batchbuffer.h"
  34
  35 static void
  36 upload_sf_state(struct brw_context *brw)
  37 {
  38    struct intel_context *intel = &brw->intel;
  39    GLcontext *ctx = &intel->ctx;
  40    /* CACHE_NEW_VS_PROG */
  41    uint32_t num_inputs = brw_count_bits(brw->vs.prog_data->outputs_written);
  42    /* This should probably be FS inputs read */
  43    uint32_t num_outputs = brw_count_bits(brw->vs.prog_data->outputs_written);
  44    uint32_t dw1, dw2, dw3, dw4;
  45    int i;
  46    /* _NEW_BUFFER */
  47    GLboolean render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
  48
  49    dw1 =
  50       num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT |
  51       num_inputs << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
  52       3 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT;
  53    dw2 = GEN6_SF_VIEWPORT_TRANSFORM_ENABLE |
  54       GEN6_SF_STATISTICS_ENABLE;
  55    dw3 = 0;
  56    dw4 = 0;
  57
  58    /* _NEW_POLYGON */
  59    if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo)
  60       dw2 |= GEN6_SF_WINDING_CCW;
  61
  62    /* _NEW_SCISSOR */
  63    if (ctx->Scissor.Enabled)
  64       dw3 |= GEN6_SF_SCISSOR_ENABLE;
  65
  66    /* _NEW_POLYGON */
  67    if (ctx->Polygon.CullFlag) {
  68       switch (ctx->Polygon.CullFaceMode) {
  69       case GL_FRONT:
  70          dw3 |= GEN6_SF_CULL_BOTH;
  71          break;
  72       case GL_BACK:
  73          dw3 |= GEN6_SF_CULL_BACK;
  74          break;
  75       case GL_FRONT_AND_BACK:
  76          dw3 |= GEN6_SF_CULL_BOTH;
  77          break;
  78       default:
  79          assert(0);
  80          break;
  81       }
  82    } else {
  83       dw3 |= GEN6_SF_CULL_NONE;
  84    }
  85
  86    /* _NEW_LINE */
  87    dw3 |= U_FIXED(CLAMP(ctx->Line.Width, 0.0, 7.99), 7) <<
  88       GEN6_SF_LINE_WIDTH_SHIFT;
  89    if (ctx->Line.SmoothFlag) {
  90       dw3 |= GEN6_SF_LINE_AA_ENABLE;
  91       dw3 |= GEN6_SF_LINE_AA_MODE_TRUE;
  92       dw3 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;
  93    }
  94
  95    /* _NEW_POINT */
  96    if (ctx->Point._Attenuated)
  97       dw4 |= GEN6_SF_USE_STATE_POINT_WIDTH;
  98
  99    dw4 |= U_FIXED(CLAMP(ctx->Point.Size, 0.125, 225.875), 3) <<
 100       GEN6_SF_POINT_WIDTH_SHIFT;
 101    if (render_to_fbo)
 102       dw1 |= GEN6_SF_POINT_SPRITE_LOWERLEFT;
 103
 104    /* _NEW_LIGHT */
 105    if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
 106       dw4 |=
 107          (2 << GEN6_SF_TRI_PROVOKE_SHIFT) |
 108          (2 << GEN6_SF_TRIFAN_PROVOKE_SHIFT) |
 109          (1 << GEN6_SF_LINE_PROVOKE_SHIFT);
 110    } else {
 111       dw4 |=
 112          (1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT);
 113    }
 114
 115    BEGIN_BATCH(20);
 116    OUT_BATCH(CMD_3D_SF_STATE << 16 | (20 - 2));
 117    OUT_BATCH(dw1);
 118    OUT_BATCH(dw2);
 119    OUT_BATCH(dw3);
 120    OUT_BATCH(dw4);
 121    OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant.  copied from gen4 */
 122    OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
 123    OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
 124    for (i = 0; i < 8; i++) {
 125       /* attribute overrides */
 126       OUT_BATCH(0);
 127    }
 128    OUT_BATCH(0); /* point sprite texcoord bitmask */
 129    OUT_BATCH(0); /* constant interp bitmask */
 130    OUT_BATCH(0); /* wrapshortest enables 0-7 */
 131    OUT_BATCH(0); /* wrapshortest enables 8-15 */
 132    ADVANCE_BATCH();
 133
 134    intel_batchbuffer_emit_mi_flush(intel->batch);
 135 }
 136
 137 const struct brw_tracked_state gen6_sf_state = {
 138    .dirty = {
 139       .mesa  = (_NEW_LIGHT |
 140                 _NEW_POLYGON |
 141                 _NEW_LINE |
 142                 _NEW_SCISSOR |
 143                 _NEW_BUFFERS),
 144       .brw   = BRW_NEW_CONTEXT,
 145       .cache = CACHE_NEW_VS_PROG
 146    },
 147    .emit = upload_sf_state,
 148 };