src/mesa/drivers/dri/i965/gen6_sf_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "main/macros.h"
  33 #include "intel_batchbuffer.h"
  34
  35 static uint32_t
  36 get_attr_override(struct brw_context *brw, int attr)
  37 {
  38    uint32_t attr_override;
  39    int attr_index = 0, i;
  40
  41    /* Find the source index (0 = first attribute after the 4D position)
  42     * for this output attribute.  attr is currently a VERT_RESULT_* but should
  43     * be FRAG_ATTRIB_*.
  44     */
  45    for (i = 0; i < attr; i++) {
  46       if (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(i))
  47          attr_index++;
  48    }
  49    attr_override = attr_index;
  50
  51    return attr_index;
  52 }
  53
  54 static void
  55 upload_sf_state(struct brw_context *brw)
  56 {
  57    struct intel_context *intel = &brw->intel;
  58    GLcontext *ctx = &intel->ctx;
  59    /* CACHE_NEW_VS_PROG */
  60    uint32_t num_inputs = brw_count_bits(brw->vs.prog_data->outputs_written);
  61    /* This should probably be FS inputs read */
  62    uint32_t num_outputs = brw_count_bits(brw->vs.prog_data->outputs_written);
  63    uint32_t dw1, dw2, dw3, dw4;
  64    int i;
  65    /* _NEW_BUFFER */
  66    GLboolean render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
  67    int attr = 0;
  68
  69    dw1 =
  70       num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT |
  71       (num_inputs + 1) / 2 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
  72       3 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT;
  73    dw2 = GEN6_SF_VIEWPORT_TRANSFORM_ENABLE |
  74       GEN6_SF_STATISTICS_ENABLE;
  75    dw3 = 0;
  76    dw4 = 0;
  77
  78    /* _NEW_POLYGON */
  79    if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo)
  80       dw2 |= GEN6_SF_WINDING_CCW;
  81
  82    /* _NEW_SCISSOR */
  83    if (ctx->Scissor.Enabled)
  84       dw3 |= GEN6_SF_SCISSOR_ENABLE;
  85
  86    /* _NEW_POLYGON */
  87    if (ctx->Polygon.CullFlag) {
  88       switch (ctx->Polygon.CullFaceMode) {
  89       case GL_FRONT:
  90          dw3 |= GEN6_SF_CULL_BOTH;
  91          break;
  92       case GL_BACK:
  93          dw3 |= GEN6_SF_CULL_BACK;
  94          break;
  95       case GL_FRONT_AND_BACK:
  96          dw3 |= GEN6_SF_CULL_BOTH;
  97          break;
  98       default:
  99          assert(0);
 100          break;
 101       }
 102    } else {
 103       dw3 |= GEN6_SF_CULL_NONE;
 104    }
 105
 106    /* _NEW_LINE */
 107    dw3 |= U_FIXED(CLAMP(ctx->Line.Width, 0.0, 7.99), 7) <<
 108       GEN6_SF_LINE_WIDTH_SHIFT;
 109    if (ctx->Line.SmoothFlag) {
 110       dw3 |= GEN6_SF_LINE_AA_ENABLE;
 111       dw3 |= GEN6_SF_LINE_AA_MODE_TRUE;
 112       dw3 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;
 113    }
 114
 115    /* _NEW_POINT */
 116    if (ctx->Point._Attenuated)
 117       dw4 |= GEN6_SF_USE_STATE_POINT_WIDTH;
 118
 119    dw4 |= U_FIXED(CLAMP(ctx->Point.Size, 0.125, 225.875), 3) <<
 120       GEN6_SF_POINT_WIDTH_SHIFT;
 121    if (render_to_fbo)
 122       dw1 |= GEN6_SF_POINT_SPRITE_LOWERLEFT;
 123
 124    /* _NEW_LIGHT */
 125    if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
 126       dw4 |=
 127          (2 << GEN6_SF_TRI_PROVOKE_SHIFT) |
 128          (2 << GEN6_SF_TRIFAN_PROVOKE_SHIFT) |
 129          (1 << GEN6_SF_LINE_PROVOKE_SHIFT);
 130    } else {
 131       dw4 |=
 132          (1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT);
 133    }
 134
 135    BEGIN_BATCH(20);
 136    OUT_BATCH(CMD_3D_SF_STATE << 16 | (20 - 2));
 137    OUT_BATCH(dw1);
 138    OUT_BATCH(dw2);
 139    OUT_BATCH(dw3);
 140    OUT_BATCH(dw4);
 141    OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant.  copied from gen4 */
 142    OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
 143    OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
 144    for (i = 0; i < 8; i++) {
 145       uint32_t attr_overrides = 0;
 146
 147       /* These should be generating FS inputs read instead of VS
 148        * outputs written
 149        */
 150       for (; attr < 64; attr++) {
 151          if (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(attr)) {
 152             attr_overrides |= get_attr_override(brw, attr);
 153             attr++;
 154             break;
 155          }
 156       }
 157
 158       for (; attr < 64; attr++) {
 159          if (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(attr)) {
 160             attr_overrides |= get_attr_override(brw, attr) << 16;
 161             attr++;
 162             break;
 163          }
 164       }
 165       OUT_BATCH(attr_overrides);
 166    }
 167    OUT_BATCH(0); /* point sprite texcoord bitmask */
 168    OUT_BATCH(0); /* constant interp bitmask */
 169    OUT_BATCH(0); /* wrapshortest enables 0-7 */
 170    OUT_BATCH(0); /* wrapshortest enables 8-15 */
 171    ADVANCE_BATCH();
 172
 173    intel_batchbuffer_emit_mi_flush(intel->batch);
 174 }
 175
 176 const struct brw_tracked_state gen6_sf_state = {
 177    .dirty = {
 178       .mesa  = (_NEW_LIGHT |
 179                 _NEW_POLYGON |
 180                 _NEW_LINE |
 181                 _NEW_SCISSOR |
 182                 _NEW_BUFFERS),
 183       .brw   = BRW_NEW_CONTEXT,
 184       .cache = CACHE_NEW_VS_PROG
 185    },
 186    .emit = upload_sf_state,
 187 };