src/mesa/drivers/dri/i965/gen6_surface_state.c

   1 /*
   2  * Copyright (c) 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24
  25 #include "main/context.h"
  26 #include "main/blend.h"
  27 #include "main/mtypes.h"
  28 #include "main/samplerobj.h"
  29 #include "main/texformat.h"
  30 #include "program/prog_parameter.h"
  31
  32 #include "intel_mipmap_tree.h"
  33 #include "intel_batchbuffer.h"
  34 #include "intel_tex.h"
  35 #include "intel_fbo.h"
  36 #include "intel_buffer_objects.h"
  37
  38 #include "brw_context.h"
  39 #include "brw_state.h"
  40 #include "brw_defines.h"
  41 #include "brw_wm.h"
  42
  43 /**
  44  * Sets up a surface state structure to point at the given region.
  45  * While it is only used for the front/back buffer currently, it should be
  46  * usable for further buffers when doing ARB_draw_buffer support.
  47  */
  48 static void
  49 gen6_update_renderbuffer_surface(struct brw_context *brw,
  50                                  struct gl_renderbuffer *rb,
  51                                  bool layered,
  52                                  unsigned int unit)
  53 {
  54    struct gl_context *ctx = &brw->ctx;
  55    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
  56    struct intel_mipmap_tree *mt = irb->mt;
  57    uint32_t *surf;
  58    uint32_t format = 0;
  59    /* _NEW_BUFFERS */
  60    mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
  61    uint32_t surftype;
  62    int depth = MAX2(irb->layer_count, 1);
  63    const GLenum gl_target =
  64       rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
  65
  66    uint32_t surf_index =
  67       brw->wm.prog_data->binding_table.render_target_start + unit;
  68
  69    intel_miptree_used_for_rendering(irb->mt);
  70
  71    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
  72                           &brw->wm.base.surf_offset[surf_index]);
  73
  74    format = brw->render_target_format[rb_format];
  75    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
  76       _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
  77                     __FUNCTION__, _mesa_get_format_name(rb_format));
  78    }
  79
  80    switch (gl_target) {
  81    case GL_TEXTURE_CUBE_MAP_ARRAY:
  82    case GL_TEXTURE_CUBE_MAP:
  83       surftype = BRW_SURFACE_2D;
  84       depth *= 6;
  85       break;
  86    case GL_TEXTURE_3D:
  87       depth = MAX2(irb->mt->logical_depth0, 1);
  88       /* fallthrough */
  89    default:
  90       surftype = translate_tex_target(gl_target);
  91       break;
  92    }
  93
  94    const int min_array_element = layered ? 0 : irb->mt_layer;
  95
  96    surf[0] = SET_FIELD(surftype, BRW_SURFACE_TYPE) |
  97              SET_FIELD(format, BRW_SURFACE_FORMAT);
  98
  99    /* reloc */
 100    surf[1] = mt->bo->offset64;
 101
 102    surf[2] = SET_FIELD(mt->logical_width0 - 1, BRW_SURFACE_WIDTH) |
 103              SET_FIELD(mt->logical_height0 - 1, BRW_SURFACE_HEIGHT) |
 104              SET_FIELD(irb->mt_level - irb->mt->first_level, BRW_SURFACE_LOD);
 105
 106    surf[3] = brw_get_surface_tiling_bits(mt->tiling) |
 107              SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
 108              SET_FIELD(mt->pitch - 1, BRW_SURFACE_PITCH);
 109
 110    surf[4] = brw_get_surface_num_multisamples(mt->num_samples) |
 111              SET_FIELD(min_array_element, BRW_SURFACE_MIN_ARRAY_ELEMENT) |
 112              SET_FIELD(depth - 1, BRW_SURFACE_RENDER_TARGET_VIEW_EXTENT);
 113
 114    surf[5] = (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0);
 115
 116    drm_intel_bo_emit_reloc(brw->batch.bo,
 117                            brw->wm.base.surf_offset[surf_index] + 4,
 118                            mt->bo,
 119                            surf[1] - mt->bo->offset64,
 120                            I915_GEM_DOMAIN_RENDER,
 121                            I915_GEM_DOMAIN_RENDER);
 122 }
 123
 124 void
 125 gen6_init_vtable_surface_functions(struct brw_context *brw)
 126 {
 127    gen4_init_vtable_surface_functions(brw);
 128    brw->vtbl.update_renderbuffer_surface = gen6_update_renderbuffer_surface;
 129 }