2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include "main/macros.h"
29 #include "intel_batchbuffer.h"
30 #include "brw_context.h"
31 #include "brw_state.h"
32 #include "brw_defines.h"
35 prepare_urb( struct brw_context
*brw
)
37 brw
->urb
.nr_vs_entries
= 24;
39 brw
->urb
.nr_gs_entries
= 4;
41 brw
->urb
.nr_gs_entries
= 0;
42 /* CACHE_NEW_VS_PROG */
43 brw
->urb
.vs_size
= MIN2(brw
->vs
.prog_data
->urb_entry_size
, 1);
45 /* Check that the number of URB rows (8 floats each) allocated is less
48 assert((brw
->urb
.nr_vs_entries
+
49 brw
->urb
.nr_gs_entries
) * brw
->urb
.vs_size
* 8 < 64 * 1024);
53 upload_urb(struct brw_context
*brw
)
55 struct intel_context
*intel
= &brw
->intel
;
57 assert(brw
->urb
.nr_vs_entries
% 4 == 0);
58 assert(brw
->urb
.nr_gs_entries
% 4 == 0);
60 assert(!brw
->gs
.prog_bo
|| brw
->urb
.vs_size
< 5);
62 intel_batchbuffer_emit_mi_flush(intel
->batch
);
65 OUT_BATCH(CMD_URB
<< 16 | (3 - 2));
66 OUT_BATCH(((brw
->urb
.vs_size
- 1) << GEN6_URB_VS_SIZE_SHIFT
) |
67 ((brw
->urb
.nr_vs_entries
) << GEN6_URB_VS_ENTRIES_SHIFT
));
68 OUT_BATCH(((brw
->urb
.vs_size
- 1) << GEN6_URB_GS_SIZE_SHIFT
) |
69 ((brw
->urb
.nr_gs_entries
) << GEN6_URB_GS_ENTRIES_SHIFT
));
72 intel_batchbuffer_emit_mi_flush(intel
->batch
);
75 const struct brw_tracked_state gen6_urb
= {
78 .brw
= BRW_NEW_CONTEXT
,
79 .cache
= CACHE_NEW_VS_PROG
,
81 .prepare
= prepare_urb
,