2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
31 #include "intel_batchbuffer.h"
32 #include "main/macros.h"
34 /* The clip VP defines the guardband region where expensive clipping is skipped
35 * and fragments are allowed to be generated and clipped out cheaply by the SF.
37 * By setting it to NDC bounds of [-1,1], we don't do GB clipping. It's
38 * supposed to cause seams to become visible in apps due to shared edges taking
39 * different clip/no clip paths depending on whether the rest of the prim ends
40 * up in the guardband or not.
43 prepare_clip_vp(struct brw_context
*brw
)
45 struct brw_clipper_viewport vp
;
52 drm_intel_bo_unreference(brw
->clip
.vp_bo
);
53 brw
->clip
.vp_bo
= brw_cache_data(&brw
->cache
, BRW_CLIP_VP
,
58 const struct brw_tracked_state gen6_clip_vp
= {
60 .mesa
= _NEW_VIEWPORT
, /* XXX: not really, but we need nonzero */
64 .prepare
= prepare_clip_vp
,
68 prepare_sf_vp(struct brw_context
*brw
)
70 GLcontext
*ctx
= &brw
->intel
.ctx
;
71 const GLfloat depth_scale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
72 struct brw_sf_viewport sfv
;
73 GLfloat y_scale
, y_bias
;
74 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
75 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
77 memset(&sfv
, 0, sizeof(sfv
));
85 y_bias
= ctx
->DrawBuffer
->Height
;
89 sfv
.viewport
.m00
= v
[MAT_SX
];
90 sfv
.viewport
.m11
= v
[MAT_SY
] * y_scale
;
91 sfv
.viewport
.m22
= v
[MAT_SZ
] * depth_scale
;
92 sfv
.viewport
.m30
= v
[MAT_TX
];
93 sfv
.viewport
.m31
= v
[MAT_TY
] * y_scale
+ y_bias
;
94 sfv
.viewport
.m32
= v
[MAT_TZ
] * depth_scale
;
96 drm_intel_bo_unreference(brw
->sf
.vp_bo
);
97 brw
->sf
.vp_bo
= brw_cache_data(&brw
->cache
, BRW_SF_VP
,
102 const struct brw_tracked_state gen6_sf_vp
= {
104 .mesa
= _NEW_VIEWPORT
| _NEW_BUFFERS
,
108 .prepare
= prepare_sf_vp
,
112 prepare_cc_vp(struct brw_context
*brw
)
114 GLcontext
*ctx
= &brw
->intel
.ctx
;
115 struct brw_cc_viewport ccv
;
117 /* _NEW_TRANSOFORM */
118 if (ctx
->Transform
.DepthClamp
) {
120 ccv
.min_depth
= MIN2(ctx
->Viewport
.Near
, ctx
->Viewport
.Far
);
121 ccv
.max_depth
= MAX2(ctx
->Viewport
.Near
, ctx
->Viewport
.Far
);
127 drm_intel_bo_unreference(brw
->cc
.vp_bo
);
128 brw
->cc
.vp_bo
= brw_cache_data(&brw
->cache
, BRW_CC_VP
, &ccv
, sizeof(ccv
),
132 const struct brw_tracked_state gen6_cc_vp
= {
134 .mesa
= _NEW_VIEWPORT
| _NEW_TRANSFORM
,
138 .prepare
= prepare_cc_vp
,
141 static void prepare_viewport_state_pointers(struct brw_context
*brw
)
143 brw_add_validated_bo(brw
, brw
->sf
.state_bo
);
146 static void upload_viewport_state_pointers(struct brw_context
*brw
)
148 struct intel_context
*intel
= &brw
->intel
;
151 OUT_BATCH(CMD_VIEWPORT_STATE_POINTERS
<< 16 | (4 - 2) |
152 GEN6_CC_VIEWPORT_MODIFY
|
153 GEN6_SF_VIEWPORT_MODIFY
|
154 GEN6_CLIP_VIEWPORT_MODIFY
);
155 OUT_RELOC(brw
->clip
.vp_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
156 OUT_RELOC(brw
->sf
.vp_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
157 OUT_RELOC(brw
->cc
.vp_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
160 intel_batchbuffer_emit_mi_flush(intel
->batch
);
163 const struct brw_tracked_state gen6_viewport_state
= {
166 .brw
= BRW_NEW_BATCH
,
167 .cache
= (CACHE_NEW_CLIP_VP
|
171 .prepare
= prepare_viewport_state_pointers
,
172 .emit
= upload_viewport_state_pointers
,