2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
32 #include "intel_batchbuffer.h"
33 #include "main/macros.h"
34 #include "main/enums.h"
36 /* The clip VP defines the guardband region where expensive clipping is skipped
37 * and fragments are allowed to be generated and clipped out cheaply by the SF.
39 * By setting it to NDC bounds of [-1,1], we don't do GB clipping. It's
40 * supposed to cause seams to become visible in apps due to shared edges taking
41 * different clip/no clip paths depending on whether the rest of the prim ends
42 * up in the guardband or not.
45 prepare_clip_vp(struct brw_context
*brw
)
47 struct brw_clipper_viewport vp
;
54 drm_intel_bo_unreference(brw
->clip
.vp_bo
);
55 brw
->clip
.vp_bo
= brw_cache_data(&brw
->cache
, BRW_CLIP_VP
,
60 const struct brw_tracked_state gen6_clip_vp
= {
62 .mesa
= _NEW_VIEWPORT
, /* XXX: not really, but we need nonzero */
66 .prepare
= prepare_clip_vp
,
70 prepare_sf_vp(struct brw_context
*brw
)
72 GLcontext
*ctx
= &brw
->intel
.ctx
;
73 const GLfloat depth_scale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
74 struct brw_sf_viewport sfv
;
75 GLfloat y_scale
, y_bias
;
76 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
77 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
79 memset(&sfv
, 0, sizeof(sfv
));
87 y_bias
= ctx
->DrawBuffer
->Height
;
91 sfv
.viewport
.m00
= v
[MAT_SX
];
92 sfv
.viewport
.m11
= v
[MAT_SY
] * y_scale
;
93 sfv
.viewport
.m22
= v
[MAT_SZ
] * depth_scale
;
94 sfv
.viewport
.m30
= v
[MAT_TX
];
95 sfv
.viewport
.m31
= v
[MAT_TY
] * y_scale
+ y_bias
;
96 sfv
.viewport
.m32
= v
[MAT_TZ
] * depth_scale
;
98 drm_intel_bo_unreference(brw
->sf
.vp_bo
);
99 brw
->sf
.vp_bo
= brw_cache_data(&brw
->cache
, BRW_SF_VP
,
104 const struct brw_tracked_state gen6_sf_vp
= {
106 .mesa
= _NEW_VIEWPORT
| _NEW_BUFFERS
,
110 .prepare
= prepare_sf_vp
,
114 prepare_cc_vp(struct brw_context
*brw
)
116 GLcontext
*ctx
= &brw
->intel
.ctx
;
117 struct brw_cc_viewport ccv
;
119 /* _NEW_TRANSOFORM */
120 if (ctx
->Transform
.DepthClamp
) {
122 ccv
.min_depth
= MIN2(ctx
->Viewport
.Near
, ctx
->Viewport
.Far
);
123 ccv
.max_depth
= MAX2(ctx
->Viewport
.Near
, ctx
->Viewport
.Far
);
129 drm_intel_bo_unreference(brw
->cc
.vp_bo
);
130 brw
->cc
.vp_bo
= brw_cache_data(&brw
->cache
, BRW_CC_VP
, &ccv
, sizeof(ccv
),
134 const struct brw_tracked_state gen6_cc_vp
= {
136 .mesa
= _NEW_VIEWPORT
| _NEW_TRANSFORM
,
140 .prepare
= prepare_cc_vp
,
143 static void prepare_viewport_state_pointers(struct brw_context
*brw
)
145 brw_add_validated_bo(brw
, brw
->sf
.state_bo
);
148 static void upload_viewport_state_pointers(struct brw_context
*brw
)
150 struct intel_context
*intel
= &brw
->intel
;
153 OUT_BATCH(CMD_VIEWPORT_STATE_POINTERS
<< 16 | (4 - 2) |
154 GEN6_CC_VIEWPORT_MODIFY
|
155 GEN6_SF_VIEWPORT_MODIFY
|
156 GEN6_CLIP_VIEWPORT_MODIFY
);
157 OUT_RELOC(brw
->clip
.vp_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
158 OUT_RELOC(brw
->sf
.vp_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
159 OUT_RELOC(brw
->cc
.vp_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
162 intel_batchbuffer_emit_mi_flush(intel
->batch
);
165 const struct brw_tracked_state gen6_viewport_state
= {
168 .brw
= BRW_NEW_BATCH
,
169 .cache
= (CACHE_NEW_CLIP_VP
|
173 .prepare
= prepare_viewport_state_pointers
,
174 .emit
= upload_viewport_state_pointers
,