i965: Don't set a nonexistent enable bit in several SNB state pointers.
[mesa.git] / src / mesa / drivers / dri / i965 / gen6_viewport_state.c
1 /*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
31 #include "brw_util.h"
32 #include "intel_batchbuffer.h"
33 #include "main/macros.h"
34 #include "main/enums.h"
35
36 /* The clip VP defines the guardband region where expensive clipping is skipped
37 * and fragments are allowed to be generated and clipped out cheaply by the SF.
38 *
39 * By setting it to NDC bounds of [-1,1], we don't do GB clipping. It's
40 * supposed to cause seams to become visible in apps due to shared edges taking
41 * different clip/no clip paths depending on whether the rest of the prim ends
42 * up in the guardband or not.
43 */
44 static void
45 prepare_clip_vp(struct brw_context *brw)
46 {
47 struct brw_clipper_viewport vp;
48
49 vp.xmin = -1.0;
50 vp.xmax = 1.0;
51 vp.ymin = -1.0;
52 vp.ymax = 1.0;
53
54 drm_intel_bo_unreference(brw->clip.vp_bo);
55 brw->clip.vp_bo = brw_cache_data(&brw->cache, BRW_CLIP_VP,
56 &vp, sizeof(vp),
57 NULL, 0);
58 }
59
60 const struct brw_tracked_state gen6_clip_vp = {
61 .dirty = {
62 .mesa = _NEW_VIEWPORT, /* XXX: not really, but we need nonzero */
63 .brw = 0,
64 .cache = 0,
65 },
66 .prepare = prepare_clip_vp,
67 };
68
69 static void
70 prepare_sf_vp(struct brw_context *brw)
71 {
72 GLcontext *ctx = &brw->intel.ctx;
73 const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
74 struct brw_sf_viewport sfv;
75 GLfloat y_scale, y_bias;
76 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
77 const GLfloat *v = ctx->Viewport._WindowMap.m;
78
79 memset(&sfv, 0, sizeof(sfv));
80
81 /* _NEW_BUFFERS */
82 if (render_to_fbo) {
83 y_scale = 1.0;
84 y_bias = 0;
85 } else {
86 y_scale = -1.0;
87 y_bias = ctx->DrawBuffer->Height;
88 }
89
90 /* _NEW_VIEWPORT */
91 sfv.viewport.m00 = v[MAT_SX];
92 sfv.viewport.m11 = v[MAT_SY] * y_scale;
93 sfv.viewport.m22 = v[MAT_SZ] * depth_scale;
94 sfv.viewport.m30 = v[MAT_TX];
95 sfv.viewport.m31 = v[MAT_TY] * y_scale + y_bias;
96 sfv.viewport.m32 = v[MAT_TZ] * depth_scale;
97
98 drm_intel_bo_unreference(brw->sf.vp_bo);
99 brw->sf.vp_bo = brw_cache_data(&brw->cache, BRW_SF_VP,
100 &sfv, sizeof(sfv),
101 NULL, 0);
102 }
103
104 const struct brw_tracked_state gen6_sf_vp = {
105 .dirty = {
106 .mesa = _NEW_VIEWPORT | _NEW_BUFFERS,
107 .brw = 0,
108 .cache = 0,
109 },
110 .prepare = prepare_sf_vp,
111 };
112
113 static void
114 prepare_cc_vp(struct brw_context *brw)
115 {
116 GLcontext *ctx = &brw->intel.ctx;
117 struct brw_cc_viewport ccv;
118
119 /* _NEW_TRANSOFORM */
120 if (ctx->Transform.DepthClamp) {
121 /* _NEW_VIEWPORT */
122 ccv.min_depth = MIN2(ctx->Viewport.Near, ctx->Viewport.Far);
123 ccv.max_depth = MAX2(ctx->Viewport.Near, ctx->Viewport.Far);
124 } else {
125 ccv.min_depth = 0.0;
126 ccv.max_depth = 1.0;
127 }
128
129 drm_intel_bo_unreference(brw->cc.vp_bo);
130 brw->cc.vp_bo = brw_cache_data(&brw->cache, BRW_CC_VP, &ccv, sizeof(ccv),
131 NULL, 0);
132 }
133
134 const struct brw_tracked_state gen6_cc_vp = {
135 .dirty = {
136 .mesa = _NEW_VIEWPORT | _NEW_TRANSFORM,
137 .brw = 0,
138 .cache = 0,
139 },
140 .prepare = prepare_cc_vp,
141 };
142
143 static void prepare_viewport_state_pointers(struct brw_context *brw)
144 {
145 brw_add_validated_bo(brw, brw->sf.state_bo);
146 }
147
148 static void upload_viewport_state_pointers(struct brw_context *brw)
149 {
150 struct intel_context *intel = &brw->intel;
151
152 BEGIN_BATCH(4);
153 OUT_BATCH(CMD_VIEWPORT_STATE_POINTERS << 16 | (4 - 2) |
154 GEN6_CC_VIEWPORT_MODIFY |
155 GEN6_SF_VIEWPORT_MODIFY |
156 GEN6_CLIP_VIEWPORT_MODIFY);
157 OUT_RELOC(brw->clip.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
158 OUT_RELOC(brw->sf.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
159 OUT_RELOC(brw->cc.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
160 ADVANCE_BATCH();
161
162 intel_batchbuffer_emit_mi_flush(intel->batch);
163 }
164
165 const struct brw_tracked_state gen6_viewport_state = {
166 .dirty = {
167 .mesa = 0,
168 .brw = BRW_NEW_BATCH,
169 .cache = (CACHE_NEW_CLIP_VP |
170 CACHE_NEW_SF_VP |
171 CACHE_NEW_CC_VP)
172 },
173 .prepare = prepare_viewport_state_pointers,
174 .emit = upload_viewport_state_pointers,
175 };