2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
32 #include "program/prog_parameter.h"
33 #include "program/prog_statevars.h"
34 #include "intel_batchbuffer.h"
37 gen6_prepare_vs_push_constants(struct brw_context
*brw
)
39 struct intel_context
*intel
= &brw
->intel
;
40 struct gl_context
*ctx
= &intel
->ctx
;
41 /* _BRW_NEW_VERTEX_PROGRAM */
42 const struct brw_vertex_program
*vp
=
43 brw_vertex_program_const(brw
->vertex_program
);
44 unsigned int nr_params
= brw
->vs
.prog_data
->nr_params
/ 4;
45 bool uses_clip_distance
= vp
->program
.UsesClipDistance
;
47 if (brw
->vertex_program
->IsNVProgram
)
48 _mesa_load_tracked_matrices(ctx
);
50 /* Updates the ParamaterValues[i] pointers for all parameters of the
51 * basic type of PROGRAM_STATE_VAR.
53 /* XXX: Should this happen somewhere before to get our state flag set? */
54 _mesa_load_state_parameters(ctx
, vp
->program
.Base
.Parameters
);
56 /* CACHE_NEW_VS_PROG | _NEW_TRANSFORM */
57 if (brw
->vs
.prog_data
->nr_params
== 0 && !ctx
->Transform
.ClipPlanesEnabled
) {
58 brw
->vs
.push_const_size
= 0;
60 int params_uploaded
= 0;
64 param
= brw_state_batch(brw
, AUB_TRACE_VS_CONSTANTS
,
65 (MAX_CLIP_PLANES
+ nr_params
) *
67 32, &brw
->vs
.push_const_offset
);
69 if (brw
->vs
.prog_data
->uses_new_param_layout
) {
70 for (i
= 0; i
< brw
->vs
.prog_data
->nr_params
; i
++) {
71 *param
= *brw
->vs
.prog_data
->param
[i
];
74 params_uploaded
+= brw
->vs
.prog_data
->nr_params
/ 4;
76 /* This should be loaded like any other param, but it's ad-hoc
77 * until we redo the VS backend.
79 if (ctx
->Transform
.ClipPlanesEnabled
!= 0 && !uses_clip_distance
) {
80 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
81 int num_userclip_plane_consts
82 = _mesa_logbase2(ctx
->Transform
.ClipPlanesEnabled
) + 1;
83 int num_floats
= 4 * num_userclip_plane_consts
;
84 memcpy(param
, clip_planes
, num_floats
* sizeof(float));
86 params_uploaded
+= num_userclip_plane_consts
;
89 /* Align to a reg for convenience for brw_vs_emit.c */
90 if (params_uploaded
& 1) {
95 for (i
= 0; i
< vp
->program
.Base
.Parameters
->NumParameters
; i
++) {
96 if (brw
->vs
.constant_map
[i
] != -1) {
97 memcpy(param
+ brw
->vs
.constant_map
[i
] * 4,
98 vp
->program
.Base
.Parameters
->ParameterValues
[i
],
106 printf("VS constant buffer:\n");
107 for (i
= 0; i
< params_uploaded
; i
++) {
108 float *buf
= param
+ i
* 4;
109 printf("%d: %f %f %f %f\n",
110 i
, buf
[0], buf
[1], buf
[2], buf
[3]);
114 brw
->vs
.push_const_size
= (params_uploaded
+ 1) / 2;
115 /* We can only push 32 registers of constants at a time. */
116 assert(brw
->vs
.push_const_size
<= 32);
120 const struct brw_tracked_state gen6_vs_constants
= {
122 .mesa
= _NEW_TRANSFORM
| _NEW_PROGRAM_CONSTANTS
,
123 .brw
= (BRW_NEW_BATCH
|
124 BRW_NEW_VERTEX_PROGRAM
),
125 .cache
= CACHE_NEW_VS_PROG
,
127 .prepare
= gen6_prepare_vs_push_constants
,
131 upload_vs_state(struct brw_context
*brw
)
133 struct intel_context
*intel
= &brw
->intel
;
135 if (brw
->vs
.push_const_size
== 0) {
136 /* Disable the push constant buffers. */
138 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 | (5 - 2));
146 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 |
147 GEN6_CONSTANT_BUFFER_0_ENABLE
|
149 /* Pointer to the VS constant buffer. Covered by the set of
150 * state flags from gen6_prepare_wm_constants
152 OUT_BATCH(brw
->vs
.push_const_offset
+
153 brw
->vs
.push_const_size
- 1);
161 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
162 OUT_BATCH(brw
->vs
.prog_offset
);
163 OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT
) |
164 GEN6_VS_FLOATING_POINT_MODE_ALT
|
165 (brw
->vs
.nr_surfaces
<< GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT
));
167 if (brw
->vs
.prog_data
->total_scratch
) {
168 OUT_RELOC(brw
->vs
.scratch_bo
,
169 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
170 ffs(brw
->vs
.prog_data
->total_scratch
) - 11);
175 OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT
) |
176 (brw
->vs
.prog_data
->urb_read_length
<< GEN6_VS_URB_READ_LENGTH_SHIFT
) |
177 (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT
));
179 OUT_BATCH(((brw
->max_vs_threads
- 1) << GEN6_VS_MAX_THREADS_SHIFT
) |
180 GEN6_VS_STATISTICS_ENABLE
|
184 /* Based on my reading of the simulator, the VS constants don't get
185 * pulled into the VS FF unit until an appropriate pipeline flush
186 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
187 * references to them into a little FIFO. The flushes are common,
188 * but don't reliably happen between this and a 3DPRIMITIVE, causing
189 * the primitive to use the wrong constants. Then the FIFO
190 * containing the constant setup gets added to again on the next
191 * constants change, and eventually when a flush does happen the
192 * unit is overwhelmed by constant changes and dies.
194 * To avoid this, send a PIPE_CONTROL down the line that will
195 * update the unit immediately loading the constants. The flush
196 * type bits here were those set by the STATE_BASE_ADDRESS whose
197 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
198 * bug reports that led to this workaround, and may be more than
199 * what is strictly required to avoid the issue.
201 intel_emit_post_sync_nonzero_flush(intel
);
204 OUT_BATCH(_3DSTATE_PIPE_CONTROL
);
205 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
|
206 PIPE_CONTROL_INSTRUCTION_FLUSH
|
207 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
208 OUT_BATCH(0); /* address */
209 OUT_BATCH(0); /* write data */
213 const struct brw_tracked_state gen6_vs_state
= {
215 .mesa
= _NEW_TRANSFORM
| _NEW_PROGRAM_CONSTANTS
,
216 .brw
= (BRW_NEW_NR_VS_SURFACES
|
219 BRW_NEW_VERTEX_PROGRAM
|
221 .cache
= CACHE_NEW_VS_PROG
223 .emit
= upload_vs_state
,