2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
32 #include "program/prog_parameter.h"
33 #include "program/prog_statevars.h"
34 #include "intel_batchbuffer.h"
35 #include "glsl/glsl_parser_extras.h"
38 * Creates a streamed BO containing the push constants for the VS or GS on
41 * Push constants are constant values (such as GLSL uniforms) that are
42 * pre-loaded into a shader stage's register space at thread spawn time.
44 * Not all GLSL uniforms will be uploaded as push constants: The hardware has
45 * a limitation of 32 or 64 EU registers (256 or 512 floats) per stage to be
46 * uploaded as push constants, while GL 4.4 requires at least 1024 components
47 * to be usable for the VS. Plus, currently we always use pull constants
48 * instead of push constants when doing variable-index array access.
50 * See brw_curbe.c for the equivalent gen4/5 code.
53 gen6_upload_push_constants(struct brw_context
*brw
,
54 const struct gl_program
*prog
,
55 const struct brw_stage_prog_data
*prog_data
,
56 struct brw_stage_state
*stage_state
,
57 enum aub_state_struct_type type
)
59 struct gl_context
*ctx
= &brw
->ctx
;
61 /* Updates the ParamaterValues[i] pointers for all parameters of the
62 * basic type of PROGRAM_STATE_VAR.
64 /* XXX: Should this happen somewhere before to get our state flag set? */
65 _mesa_load_state_parameters(ctx
, prog
->Parameters
);
67 if (prog_data
->nr_params
== 0) {
68 stage_state
->push_const_size
= 0;
70 gl_constant_value
*param
;
73 param
= brw_state_batch(brw
, type
,
74 prog_data
->nr_params
* sizeof(gl_constant_value
),
75 32, &stage_state
->push_const_offset
);
77 STATIC_ASSERT(sizeof(gl_constant_value
) == sizeof(float));
79 /* _NEW_PROGRAM_CONSTANTS
81 * Also _NEW_TRANSFORM -- we may reference clip planes other than as a
82 * side effect of dereferencing uniforms, so _NEW_PROGRAM_CONSTANTS
83 * wouldn't be set for them.
85 for (i
= 0; i
< prog_data
->nr_params
; i
++) {
86 param
[i
] = *prog_data
->param
[i
];
90 fprintf(stderr
, "%s constants:\n",
91 _mesa_shader_stage_to_string(stage_state
->stage
));
92 for (i
= 0; i
< prog_data
->nr_params
; i
++) {
94 fprintf(stderr
, "g%d: ",
95 prog_data
->dispatch_grf_start_reg
+ i
/ 8);
96 fprintf(stderr
, "%8f ", param
[i
].f
);
98 fprintf(stderr
, "\n");
101 fprintf(stderr
, "\n");
102 fprintf(stderr
, "\n");
105 stage_state
->push_const_size
= ALIGN(prog_data
->nr_params
, 8) / 8;
106 /* We can only push 32 registers of constants at a time. */
108 /* From the SNB PRM (vol2, part 1, section 3.2.1.4: 3DSTATE_CONSTANT_VS:
110 * "The sum of all four read length fields (each incremented to
111 * represent the actual read length) must be less than or equal to
114 * From the IVB PRM (vol2, part 1, section 3.2.1.3: 3DSTATE_CONSTANT_VS:
116 * "The sum of all four read length fields must be less than or
117 * equal to the size of 64"
119 * The other shader stages all match the VS's limits.
121 assert(stage_state
->push_const_size
<= 32);
126 gen6_upload_vs_push_constants(struct brw_context
*brw
)
128 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
130 /* _BRW_NEW_VERTEX_PROGRAM */
131 const struct brw_vertex_program
*vp
=
132 brw_vertex_program_const(brw
->vertex_program
);
133 /* CACHE_NEW_VS_PROG */
134 const struct brw_stage_prog_data
*prog_data
= &brw
->vs
.prog_data
->base
.base
;
136 gen6_upload_push_constants(brw
, &vp
->program
.Base
, prog_data
,
137 stage_state
, AUB_TRACE_VS_CONSTANTS
);
140 if (brw
->gen
== 7 && !brw
->is_haswell
&& !brw
->is_baytrail
)
141 gen7_emit_vs_workaround_flush(brw
);
143 gen7_upload_constant_state(brw
, stage_state
, true /* active */,
144 _3DSTATE_CONSTANT_VS
);
148 const struct brw_tracked_state gen6_vs_push_constants
= {
150 .mesa
= _NEW_TRANSFORM
| _NEW_PROGRAM_CONSTANTS
,
151 .brw
= (BRW_NEW_BATCH
|
152 BRW_NEW_VERTEX_PROGRAM
|
153 BRW_NEW_PUSH_CONSTANT_ALLOCATION
),
154 .cache
= CACHE_NEW_VS_PROG
,
156 .emit
= gen6_upload_vs_push_constants
,
160 upload_vs_state(struct brw_context
*brw
)
162 struct gl_context
*ctx
= &brw
->ctx
;
163 const struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
164 uint32_t floating_point_mode
= 0;
166 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
167 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
169 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
170 * command that causes the VS Function Enable to toggle. Pipeline
171 * flush can be executed by sending a PIPE_CONTROL command with CS
172 * stall bit set and a post sync operation.
174 * Although we don't disable the VS during normal drawing, BLORP sometimes
175 * disables it. To be safe, do the flush here just in case.
177 intel_emit_post_sync_nonzero_flush(brw
);
179 if (stage_state
->push_const_size
== 0) {
180 /* Disable the push constant buffers. */
182 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 | (5 - 2));
190 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 |
191 GEN6_CONSTANT_BUFFER_0_ENABLE
|
193 /* Pointer to the VS constant buffer. Covered by the set of
194 * state flags from gen6_upload_vs_constants
196 OUT_BATCH(stage_state
->push_const_offset
+
197 stage_state
->push_const_size
- 1);
204 /* Use ALT floating point mode for ARB vertex programs, because they
207 if (ctx
->_Shader
->CurrentProgram
[MESA_SHADER_VERTEX
] == NULL
)
208 floating_point_mode
= GEN6_VS_FLOATING_POINT_MODE_ALT
;
211 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
212 OUT_BATCH(stage_state
->prog_offset
);
213 OUT_BATCH(floating_point_mode
|
214 ((ALIGN(stage_state
->sampler_count
, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT
) |
215 ((brw
->vs
.prog_data
->base
.base
.binding_table
.size_bytes
/ 4) <<
216 GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT
));
218 if (brw
->vs
.prog_data
->base
.total_scratch
) {
219 OUT_RELOC(stage_state
->scratch_bo
,
220 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
221 ffs(brw
->vs
.prog_data
->base
.total_scratch
) - 11);
226 OUT_BATCH((brw
->vs
.prog_data
->base
.base
.dispatch_grf_start_reg
<<
227 GEN6_VS_DISPATCH_START_GRF_SHIFT
) |
228 (brw
->vs
.prog_data
->base
.urb_read_length
<< GEN6_VS_URB_READ_LENGTH_SHIFT
) |
229 (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT
));
231 OUT_BATCH(((brw
->max_vs_threads
- 1) << GEN6_VS_MAX_THREADS_SHIFT
) |
232 GEN6_VS_STATISTICS_ENABLE
|
236 /* Based on my reading of the simulator, the VS constants don't get
237 * pulled into the VS FF unit until an appropriate pipeline flush
238 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
239 * references to them into a little FIFO. The flushes are common,
240 * but don't reliably happen between this and a 3DPRIMITIVE, causing
241 * the primitive to use the wrong constants. Then the FIFO
242 * containing the constant setup gets added to again on the next
243 * constants change, and eventually when a flush does happen the
244 * unit is overwhelmed by constant changes and dies.
246 * To avoid this, send a PIPE_CONTROL down the line that will
247 * update the unit immediately loading the constants. The flush
248 * type bits here were those set by the STATE_BASE_ADDRESS whose
249 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
250 * bug reports that led to this workaround, and may be more than
251 * what is strictly required to avoid the issue.
253 intel_emit_post_sync_nonzero_flush(brw
);
254 brw_emit_pipe_control_flush(brw
,
255 PIPE_CONTROL_DEPTH_STALL
|
256 PIPE_CONTROL_INSTRUCTION_FLUSH
|
257 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
260 const struct brw_tracked_state gen6_vs_state
= {
262 .mesa
= _NEW_TRANSFORM
| _NEW_PROGRAM_CONSTANTS
,
263 .brw
= (BRW_NEW_CONTEXT
|
264 BRW_NEW_VERTEX_PROGRAM
|
266 BRW_NEW_PUSH_CONSTANT_ALLOCATION
),
267 .cache
= CACHE_NEW_VS_PROG
269 .emit
= upload_vs_state
,