2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
32 #include "program/prog_parameter.h"
33 #include "program/prog_statevars.h"
34 #include "intel_batchbuffer.h"
35 #include "glsl/glsl_parser_extras.h"
38 * Creates a streamed BO containing the push constants for the VS or GS on
41 * Push constants are constant values (such as GLSL uniforms) that are
42 * pre-loaded into a shader stage's register space at thread spawn time.
44 * Not all GLSL uniforms will be uploaded as push constants: The hardware has
45 * a limitation of 32 or 64 EU registers (256 or 512 floats) per stage to be
46 * uploaded as push constants, while GL 4.4 requires at least 1024 components
47 * to be usable for the VS. Plus, currently we always use pull constants
48 * instead of push constants when doing variable-index array access.
50 * See brw_curbe.c for the equivalent gen4/5 code.
53 gen6_upload_push_constants(struct brw_context
*brw
,
54 const struct gl_program
*prog
,
55 const struct brw_stage_prog_data
*prog_data
,
56 struct brw_stage_state
*stage_state
,
57 enum aub_state_struct_type type
)
59 struct gl_context
*ctx
= &brw
->ctx
;
61 /* Updates the ParamaterValues[i] pointers for all parameters of the
62 * basic type of PROGRAM_STATE_VAR.
64 /* XXX: Should this happen somewhere before to get our state flag set? */
65 _mesa_load_state_parameters(ctx
, prog
->Parameters
);
67 if (prog_data
->nr_params
== 0) {
68 stage_state
->push_const_size
= 0;
73 param
= brw_state_batch(brw
, type
,
74 prog_data
->nr_params
* sizeof(float),
75 32, &stage_state
->push_const_offset
);
77 /* _NEW_PROGRAM_CONSTANTS
79 * Also _NEW_TRANSFORM -- we may reference clip planes other than as a
80 * side effect of dereferencing uniforms, so _NEW_PROGRAM_CONSTANTS
81 * wouldn't be set for them.
83 for (i
= 0; i
< prog_data
->nr_params
; i
++) {
84 param
[i
] = *prog_data
->param
[i
];
88 fprintf(stderr
, "%s constants:\n",
89 _mesa_shader_stage_to_string(stage_state
->stage
));
90 for (i
= 0; i
< prog_data
->nr_params
; i
++) {
92 fprintf(stderr
, "g%d: ",
93 prog_data
->dispatch_grf_start_reg
+ i
/ 8);
94 fprintf(stderr
, "%8f ", param
[i
]);
96 fprintf(stderr
, "\n");
99 fprintf(stderr
, "\n");
100 fprintf(stderr
, "\n");
103 stage_state
->push_const_size
= ALIGN(prog_data
->nr_params
, 8) / 8;
104 /* We can only push 32 registers of constants at a time. */
106 /* From the SNB PRM (vol2, part 1, section 3.2.1.4: 3DSTATE_CONSTANT_VS:
108 * "The sum of all four read length fields (each incremented to
109 * represent the actual read length) must be less than or equal to
112 * From the IVB PRM (vol2, part 1, section 3.2.1.3: 3DSTATE_CONSTANT_VS:
114 * "The sum of all four read length fields must be less than or
115 * equal to the size of 64"
117 * The other shader stages all match the VS's limits.
119 assert(stage_state
->push_const_size
<= 32);
124 gen6_upload_vs_push_constants(struct brw_context
*brw
)
126 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
128 /* _BRW_NEW_VERTEX_PROGRAM */
129 const struct brw_vertex_program
*vp
=
130 brw_vertex_program_const(brw
->vertex_program
);
131 /* CACHE_NEW_VS_PROG */
132 const struct brw_stage_prog_data
*prog_data
= &brw
->vs
.prog_data
->base
.base
;
134 gen6_upload_push_constants(brw
, &vp
->program
.Base
, prog_data
,
135 stage_state
, AUB_TRACE_VS_CONSTANTS
);
138 if (brw
->gen
== 7 && !brw
->is_haswell
&& !brw
->is_baytrail
)
139 gen7_emit_vs_workaround_flush(brw
);
141 gen7_upload_constant_state(brw
, stage_state
, true /* active */,
142 _3DSTATE_CONSTANT_VS
);
146 const struct brw_tracked_state gen6_vs_push_constants
= {
148 .mesa
= _NEW_TRANSFORM
| _NEW_PROGRAM_CONSTANTS
,
149 .brw
= (BRW_NEW_BATCH
|
150 BRW_NEW_VERTEX_PROGRAM
|
151 BRW_NEW_PUSH_CONSTANT_ALLOCATION
),
152 .cache
= CACHE_NEW_VS_PROG
,
154 .emit
= gen6_upload_vs_push_constants
,
158 upload_vs_state(struct brw_context
*brw
)
160 struct gl_context
*ctx
= &brw
->ctx
;
161 const struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
162 uint32_t floating_point_mode
= 0;
164 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
165 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
167 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
168 * command that causes the VS Function Enable to toggle. Pipeline
169 * flush can be executed by sending a PIPE_CONTROL command with CS
170 * stall bit set and a post sync operation.
172 * Although we don't disable the VS during normal drawing, BLORP sometimes
173 * disables it. To be safe, do the flush here just in case.
175 intel_emit_post_sync_nonzero_flush(brw
);
177 if (stage_state
->push_const_size
== 0) {
178 /* Disable the push constant buffers. */
180 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 | (5 - 2));
188 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 |
189 GEN6_CONSTANT_BUFFER_0_ENABLE
|
191 /* Pointer to the VS constant buffer. Covered by the set of
192 * state flags from gen6_upload_vs_constants
194 OUT_BATCH(stage_state
->push_const_offset
+
195 stage_state
->push_const_size
- 1);
202 /* Use ALT floating point mode for ARB vertex programs, because they
205 if (ctx
->_Shader
->CurrentProgram
[MESA_SHADER_VERTEX
] == NULL
)
206 floating_point_mode
= GEN6_VS_FLOATING_POINT_MODE_ALT
;
209 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
210 OUT_BATCH(stage_state
->prog_offset
);
211 OUT_BATCH(floating_point_mode
|
212 ((ALIGN(stage_state
->sampler_count
, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT
) |
213 ((brw
->vs
.prog_data
->base
.base
.binding_table
.size_bytes
/ 4) <<
214 GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT
));
216 if (brw
->vs
.prog_data
->base
.total_scratch
) {
217 OUT_RELOC(stage_state
->scratch_bo
,
218 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
219 ffs(brw
->vs
.prog_data
->base
.total_scratch
) - 11);
224 OUT_BATCH((brw
->vs
.prog_data
->base
.base
.dispatch_grf_start_reg
<<
225 GEN6_VS_DISPATCH_START_GRF_SHIFT
) |
226 (brw
->vs
.prog_data
->base
.urb_read_length
<< GEN6_VS_URB_READ_LENGTH_SHIFT
) |
227 (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT
));
229 OUT_BATCH(((brw
->max_vs_threads
- 1) << GEN6_VS_MAX_THREADS_SHIFT
) |
230 GEN6_VS_STATISTICS_ENABLE
|
234 /* Based on my reading of the simulator, the VS constants don't get
235 * pulled into the VS FF unit until an appropriate pipeline flush
236 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
237 * references to them into a little FIFO. The flushes are common,
238 * but don't reliably happen between this and a 3DPRIMITIVE, causing
239 * the primitive to use the wrong constants. Then the FIFO
240 * containing the constant setup gets added to again on the next
241 * constants change, and eventually when a flush does happen the
242 * unit is overwhelmed by constant changes and dies.
244 * To avoid this, send a PIPE_CONTROL down the line that will
245 * update the unit immediately loading the constants. The flush
246 * type bits here were those set by the STATE_BASE_ADDRESS whose
247 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
248 * bug reports that led to this workaround, and may be more than
249 * what is strictly required to avoid the issue.
251 intel_emit_post_sync_nonzero_flush(brw
);
252 brw_emit_pipe_control_flush(brw
,
253 PIPE_CONTROL_DEPTH_STALL
|
254 PIPE_CONTROL_INSTRUCTION_FLUSH
|
255 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
258 const struct brw_tracked_state gen6_vs_state
= {
260 .mesa
= _NEW_TRANSFORM
| _NEW_PROGRAM_CONSTANTS
,
261 .brw
= (BRW_NEW_CONTEXT
|
262 BRW_NEW_VERTEX_PROGRAM
|
264 BRW_NEW_PUSH_CONSTANT_ALLOCATION
),
265 .cache
= CACHE_NEW_VS_PROG
267 .emit
= upload_vs_state
,