src/mesa/drivers/dri/i965/gen6_vs_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "program/prog_parameter.h"
  33 #include "program/prog_statevars.h"
  34 #include "intel_batchbuffer.h"
  35
  36 void
  37 gen6_upload_vec4_push_constants(struct brw_context *brw,
  38                                 const struct gl_program *prog,
  39                                 const struct brw_vec4_prog_data *prog_data,
  40                                 struct brw_stage_state *stage_state,
  41                                 enum state_struct_type type)
  42 {
  43    struct gl_context *ctx = &brw->ctx;
  44
  45    /* Updates the ParamaterValues[i] pointers for all parameters of the
  46     * basic type of PROGRAM_STATE_VAR.
  47     */
  48    /* XXX: Should this happen somewhere before to get our state flag set? */
  49    _mesa_load_state_parameters(ctx, prog->Parameters);
  50
  51    if (prog_data->base.nr_params == 0) {
  52       stage_state->push_const_size = 0;
  53    } else {
  54       int params_uploaded;
  55       float *param;
  56       int i;
  57
  58       param = brw_state_batch(brw, type,
  59                               prog_data->base.nr_params * sizeof(float),
  60                               32, &stage_state->push_const_offset);
  61
  62       /* _NEW_PROGRAM_CONSTANTS
  63        *
  64        * Also _NEW_TRANSFORM -- we may reference clip planes other than as a
  65        * side effect of dereferencing uniforms, so _NEW_PROGRAM_CONSTANTS
  66        * wouldn't be set for them.
  67       */
  68       for (i = 0; i < prog_data->base.nr_params; i++) {
  69          param[i] = *prog_data->base.param[i];
  70       }
  71       params_uploaded = prog_data->base.nr_params / 4;
  72
  73       if (0) {
  74          fprintf(stderr, "Constant buffer:\n");
  75          for (i = 0; i < params_uploaded; i++) {
  76             float *buf = param + i * 4;
  77             fprintf(stderr, "%d: %f %f %f %f\n",
  78                     i, buf[0], buf[1], buf[2], buf[3]);
  79          }
  80       }
  81
  82       stage_state->push_const_size = (params_uploaded + 1) / 2;
  83       /* We can only push 32 registers of constants at a time. */
  84       assert(stage_state->push_const_size <= 32);
  85    }
  86 }
  87
  88 static void
  89 gen6_upload_vs_push_constants(struct brw_context *brw)
  90 {
  91    struct brw_stage_state *stage_state = &brw->vs.base;
  92
  93    /* _BRW_NEW_VERTEX_PROGRAM */
  94    const struct brw_vertex_program *vp =
  95       brw_vertex_program_const(brw->vertex_program);
  96    /* CACHE_NEW_VS_PROG */
  97    const struct brw_vec4_prog_data *prog_data = &brw->vs.prog_data->base;
  98
  99    gen6_upload_vec4_push_constants(brw, &vp->program.Base, prog_data,
 100                                    stage_state, AUB_TRACE_VS_CONSTANTS);
 101
 102    if (brw->gen >= 7) {
 103       if (brw->gen == 7 && !brw->is_haswell)
 104          gen7_emit_vs_workaround_flush(brw);
 105
 106       gen7_upload_constant_state(brw, stage_state, true /* active */,
 107                                  _3DSTATE_CONSTANT_VS);
 108    }
 109 }
 110
 111 const struct brw_tracked_state gen6_vs_push_constants = {
 112    .dirty = {
 113       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
 114       .brw   = (BRW_NEW_BATCH |
 115                 BRW_NEW_VERTEX_PROGRAM |
 116                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 117       .cache = CACHE_NEW_VS_PROG,
 118    },
 119    .emit = gen6_upload_vs_push_constants,
 120 };
 121
 122 static void
 123 upload_vs_state(struct brw_context *brw)
 124 {
 125    struct gl_context *ctx = &brw->ctx;
 126    const struct brw_stage_state *stage_state = &brw->vs.base;
 127    uint32_t floating_point_mode = 0;
 128
 129    /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
 130     * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
 131     *
 132     *   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
 133     *   command that causes the VS Function Enable to toggle. Pipeline
 134     *   flush can be executed by sending a PIPE_CONTROL command with CS
 135     *   stall bit set and a post sync operation.
 136     *
 137     * Although we don't disable the VS during normal drawing, BLORP sometimes
 138     * disables it.  To be safe, do the flush here just in case.
 139     */
 140    intel_emit_post_sync_nonzero_flush(brw);
 141
 142    if (stage_state->push_const_size == 0) {
 143       /* Disable the push constant buffers. */
 144       BEGIN_BATCH(5);
 145       OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
 146       OUT_BATCH(0);
 147       OUT_BATCH(0);
 148       OUT_BATCH(0);
 149       OUT_BATCH(0);
 150       ADVANCE_BATCH();
 151    } else {
 152       BEGIN_BATCH(5);
 153       OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
 154                 GEN6_CONSTANT_BUFFER_0_ENABLE |
 155                 (5 - 2));
 156       /* Pointer to the VS constant buffer.  Covered by the set of
 157        * state flags from gen6_upload_vs_constants
 158        */
 159       OUT_BATCH(stage_state->push_const_offset +
 160                 stage_state->push_const_size - 1);
 161       OUT_BATCH(0);
 162       OUT_BATCH(0);
 163       OUT_BATCH(0);
 164       ADVANCE_BATCH();
 165    }
 166
 167    /* Use ALT floating point mode for ARB vertex programs, because they
 168     * require 0^0 == 1.
 169     */
 170    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX] == NULL)
 171       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
 172
 173    BEGIN_BATCH(6);
 174    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 175    OUT_BATCH(stage_state->prog_offset);
 176    OUT_BATCH(floating_point_mode |
 177              ((ALIGN(stage_state->sampler_count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT) |
 178              ((brw->vs.prog_data->base.base.binding_table.size_bytes / 4) <<
 179               GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 180
 181    if (brw->vs.prog_data->base.total_scratch) {
 182       OUT_RELOC(stage_state->scratch_bo,
 183                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 184                 ffs(brw->vs.prog_data->base.total_scratch) - 11);
 185    } else {
 186       OUT_BATCH(0);
 187    }
 188
 189    OUT_BATCH((brw->vs.prog_data->base.dispatch_grf_start_reg <<
 190               GEN6_VS_DISPATCH_START_GRF_SHIFT) |
 191              (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
 192              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 193
 194    OUT_BATCH(((brw->max_vs_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
 195              GEN6_VS_STATISTICS_ENABLE |
 196              GEN6_VS_ENABLE);
 197    ADVANCE_BATCH();
 198
 199    /* Based on my reading of the simulator, the VS constants don't get
 200     * pulled into the VS FF unit until an appropriate pipeline flush
 201     * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
 202     * references to them into a little FIFO.  The flushes are common,
 203     * but don't reliably happen between this and a 3DPRIMITIVE, causing
 204     * the primitive to use the wrong constants.  Then the FIFO
 205     * containing the constant setup gets added to again on the next
 206     * constants change, and eventually when a flush does happen the
 207     * unit is overwhelmed by constant changes and dies.
 208     *
 209     * To avoid this, send a PIPE_CONTROL down the line that will
 210     * update the unit immediately loading the constants.  The flush
 211     * type bits here were those set by the STATE_BASE_ADDRESS whose
 212     * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
 213     * bug reports that led to this workaround, and may be more than
 214     * what is strictly required to avoid the issue.
 215     */
 216    intel_emit_post_sync_nonzero_flush(brw);
 217    brw_emit_pipe_control_flush(brw,
 218                                PIPE_CONTROL_DEPTH_STALL |
 219                                PIPE_CONTROL_INSTRUCTION_FLUSH |
 220                                PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 221 }
 222
 223 const struct brw_tracked_state gen6_vs_state = {
 224    .dirty = {
 225       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
 226       .brw   = (BRW_NEW_CONTEXT |
 227                 BRW_NEW_VERTEX_PROGRAM |
 228                 BRW_NEW_BATCH |
 229                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 230       .cache = CACHE_NEW_VS_PROG
 231    },
 232    .emit = upload_vs_state,
 233 };