a10cec318d647f8f7a77049f3ea40995d30d1f3a
[mesa.git] / src / mesa / drivers / dri / i965 / gen6_vs_state.c
1 /*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
31 #include "brw_util.h"
32 #include "program/prog_parameter.h"
33 #include "program/prog_statevars.h"
34 #include "intel_batchbuffer.h"
35
36 static void
37 upload_vs_state(struct brw_context *brw)
38 {
39 struct intel_context *intel = &brw->intel;
40 struct gl_context *ctx = &intel->ctx;
41 const struct brw_vertex_program *vp =
42 brw_vertex_program_const(brw->vertex_program);
43 unsigned int nr_params = brw->vs.prog_data->nr_params / 4;
44 drm_intel_bo *constant_bo;
45 int i;
46
47 if (brw->vs.prog_data->nr_params == 0 && !ctx->Transform.ClipPlanesEnabled) {
48 /* Disable the push constant buffers. */
49 BEGIN_BATCH(5);
50 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
51 OUT_BATCH(0);
52 OUT_BATCH(0);
53 OUT_BATCH(0);
54 OUT_BATCH(0);
55 ADVANCE_BATCH();
56 } else {
57 int params_uploaded = 0, param_regs;
58 float *param;
59
60 if (brw->vertex_program->IsNVProgram)
61 _mesa_load_tracked_matrices(ctx);
62
63 /* Updates the ParamaterValues[i] pointers for all parameters of the
64 * basic type of PROGRAM_STATE_VAR.
65 */
66 _mesa_load_state_parameters(ctx, vp->program.Base.Parameters);
67
68 constant_bo = drm_intel_bo_alloc(intel->bufmgr, "VS constant_bo",
69 (MAX_CLIP_PLANES + nr_params) *
70 4 * sizeof(float),
71 4096);
72 drm_intel_gem_bo_map_gtt(constant_bo);
73 param = constant_bo->virtual;
74
75 /* This should be loaded like any other param, but it's ad-hoc
76 * until we redo the VS backend.
77 */
78 for (i = 0; i < MAX_CLIP_PLANES; i++) {
79 if (ctx->Transform.ClipPlanesEnabled & (1 << i)) {
80 memcpy(param, ctx->Transform._ClipUserPlane[i], 4 * sizeof(float));
81 param += 4;
82 params_uploaded++;
83 }
84 }
85 /* Align to a reg for convenience for brw_vs_emit.c */
86 if (params_uploaded & 1) {
87 param += 4;
88 params_uploaded++;
89 }
90
91 for (i = 0; i < vp->program.Base.Parameters->NumParameters; i++) {
92 if (brw->vs.constant_map[i] != -1) {
93 memcpy(param + brw->vs.constant_map[i] * 4,
94 vp->program.Base.Parameters->ParameterValues[i],
95 4 * sizeof(float));
96 params_uploaded++;
97 }
98 }
99
100 if (0) {
101 printf("VS constant buffer:\n");
102 for (i = 0; i < params_uploaded; i++) {
103 float *buf = (float *)constant_bo->virtual + i * 4;
104 printf("%d: %f %f %f %f\n",
105 i, buf[0], buf[1], buf[2], buf[3]);
106 }
107 }
108
109 drm_intel_gem_bo_unmap_gtt(constant_bo);
110
111 param_regs = (params_uploaded + 1) / 2;
112 assert(param_regs <= 32);
113
114 BEGIN_BATCH(5);
115 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
116 GEN6_CONSTANT_BUFFER_0_ENABLE |
117 (5 - 2));
118 OUT_RELOC(constant_bo,
119 I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
120 param_regs - 1);
121 OUT_BATCH(0);
122 OUT_BATCH(0);
123 OUT_BATCH(0);
124 ADVANCE_BATCH();
125
126 drm_intel_bo_unreference(constant_bo);
127 }
128
129 BEGIN_BATCH(6);
130 OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
131 OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
132 OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
133 GEN6_VS_FLOATING_POINT_MODE_ALT |
134 (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
135 OUT_BATCH(0); /* scratch space base offset */
136 OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
137 (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
138 (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
139
140 OUT_BATCH(((brw->vs_max_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
141 GEN6_VS_STATISTICS_ENABLE |
142 GEN6_VS_ENABLE);
143 ADVANCE_BATCH();
144 }
145
146 const struct brw_tracked_state gen6_vs_state = {
147 .dirty = {
148 .mesa = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
149 .brw = (BRW_NEW_CURBE_OFFSETS |
150 BRW_NEW_NR_VS_SURFACES |
151 BRW_NEW_URB_FENCE |
152 BRW_NEW_CONTEXT),
153 .cache = CACHE_NEW_VS_PROG
154 },
155 .emit = upload_vs_state,
156 };