src/mesa/drivers/dri/i965/gen6_vs_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "program/prog_parameter.h"
  33 #include "program/prog_statevars.h"
  34 #include "intel_batchbuffer.h"
  35
  36 static void
  37 gen6_upload_vs_push_constants(struct brw_context *brw)
  38 {
  39    struct intel_context *intel = &brw->intel;
  40    struct gl_context *ctx = &intel->ctx;
  41    /* _BRW_NEW_VERTEX_PROGRAM */
  42    const struct brw_vertex_program *vp =
  43       brw_vertex_program_const(brw->vertex_program);
  44
  45    /* Updates the ParamaterValues[i] pointers for all parameters of the
  46     * basic type of PROGRAM_STATE_VAR.
  47     */
  48    /* XXX: Should this happen somewhere before to get our state flag set? */
  49    _mesa_load_state_parameters(ctx, vp->program.Base.Parameters);
  50
  51    /* CACHE_NEW_VS_PROG */
  52    if (brw->vs.prog_data->base.nr_params == 0) {
  53       brw->vs.push_const_size = 0;
  54    } else {
  55       int params_uploaded;
  56       float *param;
  57       int i;
  58
  59       param = brw_state_batch(brw, AUB_TRACE_VS_CONSTANTS,
  60                               brw->vs.prog_data->base.nr_params * sizeof(float),
  61                               32, &brw->vs.push_const_offset);
  62
  63       /* _NEW_PROGRAM_CONSTANTS
  64        *
  65        * Also _NEW_TRANSFORM -- we may reference clip planes other than as a
  66        * side effect of dereferencing uniforms, so _NEW_PROGRAM_CONSTANTS
  67        * wouldn't be set for them.
  68       */
  69       for (i = 0; i < brw->vs.prog_data->base.nr_params; i++) {
  70          param[i] = *brw->vs.prog_data->base.param[i];
  71       }
  72       params_uploaded = brw->vs.prog_data->base.nr_params / 4;
  73
  74       if (0) {
  75          printf("VS constant buffer:\n");
  76          for (i = 0; i < params_uploaded; i++) {
  77             float *buf = param + i * 4;
  78             printf("%d: %f %f %f %f\n",
  79                    i, buf[0], buf[1], buf[2], buf[3]);
  80          }
  81       }
  82
  83       brw->vs.push_const_size = (params_uploaded + 1) / 2;
  84       /* We can only push 32 registers of constants at a time. */
  85       assert(brw->vs.push_const_size <= 32);
  86    }
  87 }
  88
  89 const struct brw_tracked_state gen6_vs_push_constants = {
  90    .dirty = {
  91       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
  92       .brw   = (BRW_NEW_BATCH |
  93                 BRW_NEW_VERTEX_PROGRAM),
  94       .cache = CACHE_NEW_VS_PROG,
  95    },
  96    .emit = gen6_upload_vs_push_constants,
  97 };
  98
  99 static void
 100 upload_vs_state(struct brw_context *brw)
 101 {
 102    struct intel_context *intel = &brw->intel;
 103    uint32_t floating_point_mode = 0;
 104
 105    /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section
 106     * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
 107     *   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
 108     *   command that causes the VS Function Enable to toggle. Pipeline
 109     *   flush can be executed by sending a PIPE_CONTROL command with CS
 110     *   stall bit set and a post sync operation.
 111     */
 112    intel_emit_post_sync_nonzero_flush(intel);
 113
 114    if (brw->vs.push_const_size == 0) {
 115       /* Disable the push constant buffers. */
 116       BEGIN_BATCH(5);
 117       OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
 118       OUT_BATCH(0);
 119       OUT_BATCH(0);
 120       OUT_BATCH(0);
 121       OUT_BATCH(0);
 122       ADVANCE_BATCH();
 123    } else {
 124       BEGIN_BATCH(5);
 125       OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
 126                 GEN6_CONSTANT_BUFFER_0_ENABLE |
 127                 (5 - 2));
 128       /* Pointer to the VS constant buffer.  Covered by the set of
 129        * state flags from gen6_upload_vs_constants
 130        */
 131       OUT_BATCH(brw->vs.push_const_offset +
 132                 brw->vs.push_const_size - 1);
 133       OUT_BATCH(0);
 134       OUT_BATCH(0);
 135       OUT_BATCH(0);
 136       ADVANCE_BATCH();
 137    }
 138
 139    /* Use ALT floating point mode for ARB vertex programs, because they
 140     * require 0^0 == 1.
 141     */
 142    if (intel->ctx.Shader.CurrentVertexProgram == NULL)
 143       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
 144
 145    BEGIN_BATCH(6);
 146    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 147    OUT_BATCH(brw->vs.prog_offset);
 148    OUT_BATCH(floating_point_mode |
 149              ((ALIGN(brw->sampler.count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT));
 150
 151    if (brw->vs.prog_data->base.total_scratch) {
 152       OUT_RELOC(brw->vs.scratch_bo,
 153                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 154                 ffs(brw->vs.prog_data->base.total_scratch) - 11);
 155    } else {
 156       OUT_BATCH(0);
 157    }
 158
 159    OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
 160              (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
 161              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 162
 163    OUT_BATCH(((brw->max_vs_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
 164              GEN6_VS_STATISTICS_ENABLE |
 165              GEN6_VS_ENABLE);
 166    ADVANCE_BATCH();
 167
 168    /* Based on my reading of the simulator, the VS constants don't get
 169     * pulled into the VS FF unit until an appropriate pipeline flush
 170     * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
 171     * references to them into a little FIFO.  The flushes are common,
 172     * but don't reliably happen between this and a 3DPRIMITIVE, causing
 173     * the primitive to use the wrong constants.  Then the FIFO
 174     * containing the constant setup gets added to again on the next
 175     * constants change, and eventually when a flush does happen the
 176     * unit is overwhelmed by constant changes and dies.
 177     *
 178     * To avoid this, send a PIPE_CONTROL down the line that will
 179     * update the unit immediately loading the constants.  The flush
 180     * type bits here were those set by the STATE_BASE_ADDRESS whose
 181     * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
 182     * bug reports that led to this workaround, and may be more than
 183     * what is strictly required to avoid the issue.
 184     */
 185    intel_emit_post_sync_nonzero_flush(intel);
 186
 187    BEGIN_BATCH(4);
 188    OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
 189    OUT_BATCH(PIPE_CONTROL_DEPTH_STALL |
 190              PIPE_CONTROL_INSTRUCTION_FLUSH |
 191              PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 192    OUT_BATCH(0); /* address */
 193    OUT_BATCH(0); /* write data */
 194    ADVANCE_BATCH();
 195 }
 196
 197 const struct brw_tracked_state gen6_vs_state = {
 198    .dirty = {
 199       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
 200       .brw   = (BRW_NEW_CONTEXT |
 201                 BRW_NEW_VERTEX_PROGRAM |
 202                 BRW_NEW_BATCH),
 203       .cache = CACHE_NEW_VS_PROG | CACHE_NEW_SAMPLER
 204    },
 205    .emit = upload_vs_state,
 206 };