src/mesa/drivers/dri/i965/gen6_vs_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "program/prog_parameter.h"
  33 #include "program/prog_statevars.h"
  34 #include "intel_batchbuffer.h"
  35
  36 static void
  37 gen6_upload_vs_push_constants(struct brw_context *brw)
  38 {
  39    struct brw_stage_state *stage_state = &brw->vs.base;
  40
  41    /* _BRW_NEW_VERTEX_PROGRAM */
  42    const struct brw_vertex_program *vp =
  43       brw_vertex_program_const(brw->vertex_program);
  44    /* BRW_NEW_VS_PROG_DATA */
  45    const struct brw_stage_prog_data *prog_data = &brw->vs.prog_data->base.base;
  46
  47    gen6_upload_push_constants(brw, &vp->program.Base, prog_data,
  48                               stage_state, AUB_TRACE_VS_CONSTANTS);
  49
  50    if (brw->gen >= 7) {
  51       if (brw->gen == 7 && !brw->is_haswell && !brw->is_baytrail)
  52          gen7_emit_vs_workaround_flush(brw);
  53
  54       gen7_upload_constant_state(brw, stage_state, true /* active */,
  55                                  _3DSTATE_CONSTANT_VS);
  56    }
  57 }
  58
  59 const struct brw_tracked_state gen6_vs_push_constants = {
  60    .dirty = {
  61       .mesa  = _NEW_PROGRAM_CONSTANTS |
  62                _NEW_TRANSFORM,
  63       .brw   = BRW_NEW_BATCH |
  64                BRW_NEW_PUSH_CONSTANT_ALLOCATION |
  65                BRW_NEW_VERTEX_PROGRAM |
  66                BRW_NEW_VS_PROG_DATA,
  67    },
  68    .emit = gen6_upload_vs_push_constants,
  69 };
  70
  71 static void
  72 upload_vs_state(struct brw_context *brw)
  73 {
  74    const struct brw_stage_state *stage_state = &brw->vs.base;
  75    uint32_t floating_point_mode = 0;
  76
  77    /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
  78     * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
  79     *
  80     *   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
  81     *   command that causes the VS Function Enable to toggle. Pipeline
  82     *   flush can be executed by sending a PIPE_CONTROL command with CS
  83     *   stall bit set and a post sync operation.
  84     *
  85     * We've already done such a flush at the start of state upload, so we
  86     * don't need to do another one here.
  87     */
  88
  89    if (stage_state->push_const_size == 0) {
  90       /* Disable the push constant buffers. */
  91       BEGIN_BATCH(5);
  92       OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
  93       OUT_BATCH(0);
  94       OUT_BATCH(0);
  95       OUT_BATCH(0);
  96       OUT_BATCH(0);
  97       ADVANCE_BATCH();
  98    } else {
  99       BEGIN_BATCH(5);
 100       OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
 101                 GEN6_CONSTANT_BUFFER_0_ENABLE |
 102                 (5 - 2));
 103       /* Pointer to the VS constant buffer.  Covered by the set of
 104        * state flags from gen6_upload_vs_constants
 105        */
 106       OUT_BATCH(stage_state->push_const_offset +
 107                 stage_state->push_const_size - 1);
 108       OUT_BATCH(0);
 109       OUT_BATCH(0);
 110       OUT_BATCH(0);
 111       ADVANCE_BATCH();
 112    }
 113
 114    if (brw->vs.prog_data->base.base.use_alt_mode)
 115       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
 116
 117    BEGIN_BATCH(6);
 118    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 119    OUT_BATCH(stage_state->prog_offset);
 120    OUT_BATCH(floating_point_mode |
 121              ((ALIGN(stage_state->sampler_count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT) |
 122              ((brw->vs.prog_data->base.base.binding_table.size_bytes / 4) <<
 123               GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 124
 125    if (brw->vs.prog_data->base.base.total_scratch) {
 126       OUT_RELOC(stage_state->scratch_bo,
 127                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 128                 ffs(brw->vs.prog_data->base.base.total_scratch) - 11);
 129    } else {
 130       OUT_BATCH(0);
 131    }
 132
 133    OUT_BATCH((brw->vs.prog_data->base.base.dispatch_grf_start_reg <<
 134               GEN6_VS_DISPATCH_START_GRF_SHIFT) |
 135              (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
 136              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 137
 138    OUT_BATCH(((brw->max_vs_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
 139              GEN6_VS_STATISTICS_ENABLE |
 140              GEN6_VS_ENABLE);
 141    ADVANCE_BATCH();
 142
 143    /* Based on my reading of the simulator, the VS constants don't get
 144     * pulled into the VS FF unit until an appropriate pipeline flush
 145     * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
 146     * references to them into a little FIFO.  The flushes are common,
 147     * but don't reliably happen between this and a 3DPRIMITIVE, causing
 148     * the primitive to use the wrong constants.  Then the FIFO
 149     * containing the constant setup gets added to again on the next
 150     * constants change, and eventually when a flush does happen the
 151     * unit is overwhelmed by constant changes and dies.
 152     *
 153     * To avoid this, send a PIPE_CONTROL down the line that will
 154     * update the unit immediately loading the constants.  The flush
 155     * type bits here were those set by the STATE_BASE_ADDRESS whose
 156     * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
 157     * bug reports that led to this workaround, and may be more than
 158     * what is strictly required to avoid the issue.
 159     */
 160    brw_emit_pipe_control_flush(brw,
 161                                PIPE_CONTROL_DEPTH_STALL |
 162                                PIPE_CONTROL_INSTRUCTION_INVALIDATE |
 163                                PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 164 }
 165
 166 const struct brw_tracked_state gen6_vs_state = {
 167    .dirty = {
 168       .mesa  = _NEW_PROGRAM_CONSTANTS |
 169                _NEW_TRANSFORM,
 170       .brw   = BRW_NEW_BATCH |
 171                BRW_NEW_CONTEXT |
 172                BRW_NEW_PUSH_CONSTANT_ALLOCATION |
 173                BRW_NEW_VERTEX_PROGRAM |
 174                BRW_NEW_VS_PROG_DATA,
 175    },
 176    .emit = upload_vs_state,
 177 };