src/mesa/drivers/dri/i965/gen6_vs_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "program/prog_parameter.h"
  33 #include "program/prog_statevars.h"
  34 #include "intel_batchbuffer.h"
  35
  36 static void
  37 gen6_prepare_vs_push_constants(struct brw_context *brw)
  38 {
  39    struct intel_context *intel = &brw->intel;
  40    struct gl_context *ctx = &intel->ctx;
  41    /* _BRW_NEW_VERTEX_PROGRAM */
  42    const struct brw_vertex_program *vp =
  43       brw_vertex_program_const(brw->vertex_program);
  44    unsigned int nr_params = brw->vs.prog_data->nr_params / 4;
  45
  46    if (brw->vertex_program->IsNVProgram)
  47       _mesa_load_tracked_matrices(ctx);
  48
  49    /* Updates the ParamaterValues[i] pointers for all parameters of the
  50     * basic type of PROGRAM_STATE_VAR.
  51     */
  52    /* XXX: Should this happen somewhere before to get our state flag set? */
  53    _mesa_load_state_parameters(ctx, vp->program.Base.Parameters);
  54
  55    /* CACHE_NEW_VS_PROG | _NEW_TRANSFORM */
  56    if (brw->vs.prog_data->nr_params == 0 && !ctx->Transform.ClipPlanesEnabled) {
  57       brw->vs.push_const_size = 0;
  58    } else {
  59       int params_uploaded = 0;
  60       float *param;
  61       int i;
  62
  63       param = brw_state_batch(brw, AUB_TRACE_VS_CONSTANTS,
  64                               (MAX_CLIP_PLANES + nr_params) *
  65                               4 * sizeof(float),
  66                               32, &brw->vs.push_const_offset);
  67
  68       /* This should be loaded like any other param, but it's ad-hoc
  69        * until we redo the VS backend.
  70        */
  71       for (i = 0; i < MAX_CLIP_PLANES; i++) {
  72          if (ctx->Transform.ClipPlanesEnabled & (1 << i)) {
  73             memcpy(param, ctx->Transform._ClipUserPlane[i], 4 * sizeof(float));
  74             param += 4;
  75             params_uploaded++;
  76          }
  77       }
  78       /* Align to a reg for convenience for brw_vs_emit.c */
  79       if (params_uploaded & 1) {
  80          param += 4;
  81          params_uploaded++;
  82       }
  83
  84       if (brw->vs.prog_data->uses_new_param_layout) {
  85          for (i = 0; i < brw->vs.prog_data->nr_params; i++) {
  86             *param = *brw->vs.prog_data->param[i];
  87             param++;
  88          }
  89          params_uploaded += brw->vs.prog_data->nr_params / 4;
  90       } else {
  91          for (i = 0; i < vp->program.Base.Parameters->NumParameters; i++) {
  92             if (brw->vs.constant_map[i] != -1) {
  93                memcpy(param + brw->vs.constant_map[i] * 4,
  94                       vp->program.Base.Parameters->ParameterValues[i],
  95                       4 * sizeof(float));
  96                params_uploaded++;
  97             }
  98          }
  99       }
 100
 101       if (0) {
 102          printf("VS constant buffer:\n");
 103          for (i = 0; i < params_uploaded; i++) {
 104             float *buf = param + i * 4;
 105             printf("%d: %f %f %f %f\n",
 106                    i, buf[0], buf[1], buf[2], buf[3]);
 107          }
 108       }
 109
 110       brw->vs.push_const_size = (params_uploaded + 1) / 2;
 111       /* We can only push 32 registers of constants at a time. */
 112       assert(brw->vs.push_const_size <= 32);
 113    }
 114 }
 115
 116 const struct brw_tracked_state gen6_vs_constants = {
 117    .dirty = {
 118       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
 119       .brw   = (BRW_NEW_BATCH |
 120                 BRW_NEW_VERTEX_PROGRAM),
 121       .cache = CACHE_NEW_VS_PROG,
 122    },
 123    .prepare = gen6_prepare_vs_push_constants,
 124 };
 125
 126 static void
 127 upload_vs_state(struct brw_context *brw)
 128 {
 129    struct intel_context *intel = &brw->intel;
 130
 131    if (brw->vs.push_const_size == 0) {
 132       /* Disable the push constant buffers. */
 133       BEGIN_BATCH(5);
 134       OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
 135       OUT_BATCH(0);
 136       OUT_BATCH(0);
 137       OUT_BATCH(0);
 138       OUT_BATCH(0);
 139       ADVANCE_BATCH();
 140    } else {
 141       BEGIN_BATCH(5);
 142       OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
 143                 GEN6_CONSTANT_BUFFER_0_ENABLE |
 144                 (5 - 2));
 145       /* Pointer to the VS constant buffer.  Covered by the set of
 146        * state flags from gen6_prepare_wm_constants
 147        */
 148       OUT_BATCH(brw->vs.push_const_offset +
 149                 brw->vs.push_const_size - 1);
 150       OUT_BATCH(0);
 151       OUT_BATCH(0);
 152       OUT_BATCH(0);
 153       ADVANCE_BATCH();
 154    }
 155
 156    BEGIN_BATCH(6);
 157    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 158    OUT_BATCH(brw->vs.prog_offset);
 159    OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
 160              GEN6_VS_FLOATING_POINT_MODE_ALT |
 161              (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 162
 163    if (brw->vs.prog_data->total_scratch) {
 164       OUT_RELOC(brw->vs.scratch_bo,
 165                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 166                 ffs(brw->vs.prog_data->total_scratch) - 11);
 167    } else {
 168       OUT_BATCH(0);
 169    }
 170
 171    OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
 172              (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
 173              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 174
 175    OUT_BATCH(((brw->vs_max_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
 176              GEN6_VS_STATISTICS_ENABLE |
 177              GEN6_VS_ENABLE);
 178    ADVANCE_BATCH();
 179
 180    /* Based on my reading of the simulator, the VS constants don't get
 181     * pulled into the VS FF unit until an appropriate pipeline flush
 182     * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
 183     * references to them into a little FIFO.  The flushes are common,
 184     * but don't reliably happen between this and a 3DPRIMITIVE, causing
 185     * the primitive to use the wrong constants.  Then the FIFO
 186     * containing the constant setup gets added to again on the next
 187     * constants change, and eventually when a flush does happen the
 188     * unit is overwhelmed by constant changes and dies.
 189     *
 190     * To avoid this, send a PIPE_CONTROL down the line that will
 191     * update the unit immediately loading the constants.  The flush
 192     * type bits here were those set by the STATE_BASE_ADDRESS whose
 193     * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
 194     * bug reports that led to this workaround, and may be more than
 195     * what is strictly required to avoid the issue.
 196     */
 197    BEGIN_BATCH(4);
 198    OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 199    OUT_BATCH(PIPE_CONTROL_DEPTH_STALL |
 200              PIPE_CONTROL_INSTRUCTION_FLUSH |
 201              PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 202    OUT_BATCH(0); /* address */
 203    OUT_BATCH(0); /* write data */
 204    ADVANCE_BATCH();
 205 }
 206
 207 const struct brw_tracked_state gen6_vs_state = {
 208    .dirty = {
 209       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
 210       .brw   = (BRW_NEW_NR_VS_SURFACES |
 211                 BRW_NEW_URB_FENCE |
 212                 BRW_NEW_CONTEXT |
 213                 BRW_NEW_VERTEX_PROGRAM |
 214                 BRW_NEW_BATCH),
 215       .cache = CACHE_NEW_VS_PROG
 216    },
 217    .emit = upload_vs_state,
 218 };