src/mesa/drivers/dri/i965/gen6_vs_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "main/macros.h"
  33 #include "main/enums.h"
  34 #include "shader/prog_parameter.h"
  35 #include "shader/prog_statevars.h"
  36 #include "intel_batchbuffer.h"
  37
  38 static void
  39 upload_vs_state(struct brw_context *brw)
  40 {
  41    struct intel_context *intel = &brw->intel;
  42    GLcontext *ctx = &intel->ctx;
  43    const struct brw_vertex_program *vp =
  44       brw_vertex_program_const(brw->vertex_program);
  45    unsigned int nr_params = vp->program.Base.Parameters->NumParameters;
  46    drm_intel_bo *constant_bo;
  47    int i;
  48
  49    if (vp->use_const_buffer || nr_params == 0) {
  50       /* Disable the push constant buffers. */
  51       BEGIN_BATCH(5);
  52       OUT_BATCH(CMD_3D_CONSTANT_VS_STATE << 16 | (5 - 2));
  53       OUT_BATCH(0);
  54       OUT_BATCH(0);
  55       OUT_BATCH(0);
  56       OUT_BATCH(0);
  57       ADVANCE_BATCH();
  58    } else {
  59       if (brw->vertex_program->IsNVProgram)
  60          _mesa_load_tracked_matrices(ctx);
  61
  62       /* Updates the ParamaterValues[i] pointers for all parameters of the
  63        * basic type of PROGRAM_STATE_VAR.
  64        */
  65       _mesa_load_state_parameters(ctx, vp->program.Base.Parameters);
  66
  67       constant_bo = drm_intel_bo_alloc(intel->bufmgr, "VS constant_bo",
  68                                        nr_params * 4 * sizeof(float),
  69                                        4096);
  70       intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
  71       for (i = 0; i < nr_params; i++) {
  72          memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
  73                 vp->program.Base.Parameters->ParameterValues[i],
  74                 4 * sizeof(float));
  75       }
  76       intel_bo_unmap_gtt_preferred(intel, constant_bo);
  77
  78       BEGIN_BATCH(5);
  79       OUT_BATCH(CMD_3D_CONSTANT_VS_STATE << 16 |
  80                 GEN6_CONSTANT_BUFFER_0_ENABLE |
  81                 (5 - 2));
  82       OUT_RELOC(constant_bo,
  83                 I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
  84                 ALIGN(nr_params, 2) / 2 - 1);
  85       OUT_BATCH(0);
  86       OUT_BATCH(0);
  87       OUT_BATCH(0);
  88       ADVANCE_BATCH();
  89
  90       drm_intel_bo_unreference(constant_bo);
  91    }
  92
  93    intel_batchbuffer_emit_mi_flush(intel->batch);
  94
  95    BEGIN_BATCH(6);
  96    OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
  97    OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
  98    OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
  99              (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 100    OUT_BATCH(0); /* scratch space base offset */
 101    OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
 102              (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
 103              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 104    OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
 105              GEN6_VS_STATISTICS_ENABLE);
 106    ADVANCE_BATCH();
 107
 108    intel_batchbuffer_emit_mi_flush(intel->batch);
 109 }
 110
 111 const struct brw_tracked_state gen6_vs_state = {
 112    .dirty = {
 113       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
 114       .brw   = (BRW_NEW_CURBE_OFFSETS |
 115                 BRW_NEW_NR_VS_SURFACES |
 116                 BRW_NEW_URB_FENCE |
 117                 BRW_NEW_CONTEXT),
 118       .cache = CACHE_NEW_VS_PROG
 119    },
 120    .emit = upload_vs_state,
 121 };