2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
33 #include "program/program.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_statevars.h"
36 #include "intel_batchbuffer.h"
39 gen6_upload_wm_push_constants(struct brw_context
*brw
)
41 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
42 /* BRW_NEW_FRAGMENT_PROGRAM */
43 const struct brw_fragment_program
*fp
=
44 brw_fragment_program_const(brw
->fragment_program
);
45 /* BRW_NEW_FS_PROG_DATA */
46 const struct brw_wm_prog_data
*prog_data
= brw
->wm
.prog_data
;
48 gen6_upload_push_constants(brw
, &fp
->program
.Base
, &prog_data
->base
,
49 stage_state
, AUB_TRACE_WM_CONSTANTS
);
52 gen7_upload_constant_state(brw
, &brw
->wm
.base
, true,
53 _3DSTATE_CONSTANT_PS
);
57 const struct brw_tracked_state gen6_wm_push_constants
= {
59 .mesa
= _NEW_PROGRAM_CONSTANTS
,
60 .brw
= BRW_NEW_BATCH
|
61 BRW_NEW_FRAGMENT_PROGRAM
|
62 BRW_NEW_FS_PROG_DATA
|
63 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
65 .emit
= gen6_upload_wm_push_constants
,
69 upload_wm_state(struct brw_context
*brw
)
71 struct gl_context
*ctx
= &brw
->ctx
;
72 /* BRW_NEW_FRAGMENT_PROGRAM */
73 const struct brw_fragment_program
*fp
=
74 brw_fragment_program_const(brw
->fragment_program
);
75 /* BRW_NEW_FS_PROG_DATA */
76 const struct brw_wm_prog_data
*prog_data
= brw
->wm
.prog_data
;
77 uint32_t dw2
, dw4
, dw5
, dw6
, ksp0
, ksp2
;
80 bool multisampled_fbo
= ctx
->DrawBuffer
->Visual
.samples
> 1;
82 /* We can't fold this into gen6_upload_wm_push_constants(), because
83 * according to the SNB PRM, vol 2 part 1 section 7.2.2
84 * (3DSTATE_CONSTANT_PS [DevSNB]):
86 * "[DevSNB]: This packet must be followed by WM_STATE."
88 if (prog_data
->base
.nr_params
== 0) {
89 /* Disable the push constant buffers. */
91 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 | (5 - 2));
99 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 |
100 GEN6_CONSTANT_BUFFER_0_ENABLE
|
102 /* Pointer to the WM constant buffer. Covered by the set of
103 * state flags from gen6_upload_wm_push_constants.
105 OUT_BATCH(brw
->wm
.base
.push_const_offset
+
106 brw
->wm
.base
.push_const_size
- 1);
113 dw2
= dw4
= dw5
= dw6
= ksp2
= 0;
114 dw4
|= GEN6_WM_STATISTICS_ENABLE
;
115 dw5
|= GEN6_WM_LINE_AA_WIDTH_1_0
;
116 dw5
|= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5
;
118 if (prog_data
->base
.use_alt_mode
)
119 dw2
|= GEN6_WM_FLOATING_POINT_MODE_ALT
;
121 dw2
|= (ALIGN(brw
->wm
.base
.sampler_count
, 4) / 4) <<
122 GEN6_WM_SAMPLER_COUNT_SHIFT
;
124 dw2
|= ((prog_data
->base
.binding_table
.size_bytes
/ 4) <<
125 GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT
);
127 dw5
|= (brw
->max_wm_threads
- 1) << GEN6_WM_MAX_THREADS_SHIFT
;
129 /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
130 * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
131 * is successfully compiled. In majority of the cases that bring us
132 * better performance than 'SIMD8 only' dispatch.
134 int min_inv_per_frag
=
135 _mesa_get_min_invocations_per_fragment(ctx
, brw
->fragment_program
, false);
136 assert(min_inv_per_frag
>= 1);
138 if (prog_data
->prog_offset_16
|| prog_data
->no_8
) {
139 dw5
|= GEN6_WM_16_DISPATCH_ENABLE
;
141 if (!prog_data
->no_8
&& min_inv_per_frag
== 1) {
142 dw5
|= GEN6_WM_8_DISPATCH_ENABLE
;
143 dw4
|= (prog_data
->base
.dispatch_grf_start_reg
<<
144 GEN6_WM_DISPATCH_START_GRF_SHIFT_0
);
145 dw4
|= (prog_data
->dispatch_grf_start_reg_16
<<
146 GEN6_WM_DISPATCH_START_GRF_SHIFT_2
);
147 ksp0
= brw
->wm
.base
.prog_offset
;
148 ksp2
= brw
->wm
.base
.prog_offset
+ prog_data
->prog_offset_16
;
150 dw4
|= (prog_data
->dispatch_grf_start_reg_16
<<
151 GEN6_WM_DISPATCH_START_GRF_SHIFT_0
);
152 ksp0
= brw
->wm
.base
.prog_offset
+ prog_data
->prog_offset_16
;
156 dw5
|= GEN6_WM_8_DISPATCH_ENABLE
;
157 dw4
|= (prog_data
->base
.dispatch_grf_start_reg
<<
158 GEN6_WM_DISPATCH_START_GRF_SHIFT_0
);
159 ksp0
= brw
->wm
.base
.prog_offset
;
162 /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
163 if (prog_data
->dual_src_blend
&&
164 (ctx
->Color
.BlendEnabled
& 1) &&
165 ctx
->Color
.Blend
[0]._UsesDualSrc
) {
166 dw5
|= GEN6_WM_DUAL_SOURCE_BLEND_ENABLE
;
170 if (ctx
->Line
.StippleFlag
)
171 dw5
|= GEN6_WM_LINE_STIPPLE_ENABLE
;
174 if (ctx
->Polygon
.StippleFlag
)
175 dw5
|= GEN6_WM_POLYGON_STIPPLE_ENABLE
;
177 /* BRW_NEW_FRAGMENT_PROGRAM */
178 if (fp
->program
.Base
.InputsRead
& VARYING_BIT_POS
)
179 dw5
|= GEN6_WM_USES_SOURCE_DEPTH
| GEN6_WM_USES_SOURCE_W
;
180 if (fp
->program
.Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
181 dw5
|= GEN6_WM_COMPUTED_DEPTH
;
182 dw6
|= prog_data
->barycentric_interp_modes
<<
183 GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
;
185 /* _NEW_COLOR, _NEW_MULTISAMPLE */
186 if (prog_data
->uses_kill
|| ctx
->Color
.AlphaEnabled
||
187 ctx
->Multisample
.SampleAlphaToCoverage
||
188 prog_data
->uses_omask
)
189 dw5
|= GEN6_WM_KILL_ENABLE
;
191 /* _NEW_BUFFERS | _NEW_COLOR */
192 if (brw_color_buffer_write_enabled(brw
) ||
193 dw5
& (GEN6_WM_KILL_ENABLE
| GEN6_WM_COMPUTED_DEPTH
)) {
194 dw5
|= GEN6_WM_DISPATCH_ENABLE
;
197 /* From the SNB PRM, volume 2 part 1, page 278:
198 * "This bit is inserted in the PS payload header and made available to
199 * the DataPort (either via the message header or via header bypass) to
200 * indicate that oMask data (one or two phases) is included in Render
201 * Target Write messages. If present, the oMask data is used to mask off
204 if (prog_data
->uses_omask
)
205 dw5
|= GEN6_WM_OMASK_TO_RENDER_TARGET
;
207 dw6
|= prog_data
->num_varying_inputs
<<
208 GEN6_WM_NUM_SF_OUTPUTS_SHIFT
;
209 if (multisampled_fbo
) {
210 /* _NEW_MULTISAMPLE */
211 if (ctx
->Multisample
.Enabled
)
212 dw6
|= GEN6_WM_MSRAST_ON_PATTERN
;
214 dw6
|= GEN6_WM_MSRAST_OFF_PIXEL
;
216 if (min_inv_per_frag
> 1)
217 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
219 dw6
|= GEN6_WM_MSDISPMODE_PERPIXEL
;
221 /* From the Sandy Bridge PRM, Vol 2 part 1, 7.7.1 ("Pixel Grouping
222 * (Dispatch Size) Control"), p.334:
224 * Note: in the table below, the Valid column indicates which
225 * products that combination is supported on. Combinations of
226 * dispatch enables not listed in the table are not available on
229 * A: Valid on all products
231 * B: Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader
234 * D: Valid on all products, except when in non-1x PERSAMPLE mode
235 * (applies to [DevSNB+] only). Not valid on [DevSNB] if 4x
236 * PERPIXEL mode with pixel shader computed depth.
238 * E: Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader
241 * F: Valid on all products, except not valid on [DevSNB] if 4x
242 * PERPIXEL mode with pixel shader computed depth.
244 * In the table that follows, the only entry with "A" in the Valid
245 * column is the entry where only 8 pixel dispatch is enabled.
246 * Therefore, when we are in PERPIXEL mode with pixel shader computed
247 * depth, we need to disable SIMD16 dispatch.
249 if (dw5
& GEN6_WM_COMPUTED_DEPTH
)
250 dw5
&= ~GEN6_WM_16_DISPATCH_ENABLE
;
253 dw6
|= GEN6_WM_MSRAST_OFF_PIXEL
;
254 dw6
|= GEN6_WM_MSDISPMODE_PERSAMPLE
;
257 /* From the SNB PRM, volume 2 part 1, page 281:
258 * "If the PS kernel does not need the Position XY Offsets
259 * to compute a Position XY value, then this field should be
260 * programmed to POSOFFSET_NONE."
262 * "SW Recommendation: If the PS kernel needs the Position Offsets
263 * to compute a Position XY value, this field should match Position
264 * ZW Interpolation Mode to ensure a consistent position.xyzw
266 * We only require XY sample offsets. So, this recommendation doesn't
267 * look useful at the moment. We might need this in future.
269 if (prog_data
->uses_pos_offset
)
270 dw6
|= GEN6_WM_POSOFFSET_SAMPLE
;
272 dw6
|= GEN6_WM_POSOFFSET_NONE
;
275 OUT_BATCH(_3DSTATE_WM
<< 16 | (9 - 2));
278 if (prog_data
->base
.total_scratch
) {
279 OUT_RELOC(brw
->wm
.base
.scratch_bo
,
280 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
281 ffs(prog_data
->base
.total_scratch
) - 11);
288 OUT_BATCH(0); /* kernel 1 pointer */
293 const struct brw_tracked_state gen6_wm_state
= {
295 .mesa
= _NEW_BUFFERS
|
300 _NEW_PROGRAM_CONSTANTS
,
301 .brw
= BRW_NEW_BATCH
|
302 BRW_NEW_FRAGMENT_PROGRAM
|
303 BRW_NEW_FS_PROG_DATA
|
304 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
306 .emit
= upload_wm_state
,