src/mesa/drivers/dri/i965/gen6_wm_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "brw_wm.h"
  33 #include "program/program.h"
  34 #include "program/prog_parameter.h"
  35 #include "program/prog_statevars.h"
  36 #include "main/framebuffer.h"
  37 #include "intel_batchbuffer.h"
  38
  39 static void
  40 gen6_upload_wm_push_constants(struct brw_context *brw)
  41 {
  42    struct brw_stage_state *stage_state = &brw->wm.base;
  43    /* BRW_NEW_FRAGMENT_PROGRAM */
  44    const struct brw_fragment_program *fp =
  45       brw_fragment_program_const(brw->fragment_program);
  46    /* BRW_NEW_FS_PROG_DATA */
  47    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  48
  49    gen6_upload_push_constants(brw, &fp->program.Base, &prog_data->base,
  50                               stage_state, AUB_TRACE_WM_CONSTANTS);
  51
  52    if (brw->gen >= 7) {
  53       gen7_upload_constant_state(brw, &brw->wm.base, true,
  54                                  _3DSTATE_CONSTANT_PS);
  55    }
  56 }
  57
  58 const struct brw_tracked_state gen6_wm_push_constants = {
  59    .dirty = {
  60       .mesa  = _NEW_PROGRAM_CONSTANTS,
  61       .brw   = BRW_NEW_BATCH |
  62                BRW_NEW_FRAGMENT_PROGRAM |
  63                BRW_NEW_FS_PROG_DATA |
  64                BRW_NEW_PUSH_CONSTANT_ALLOCATION,
  65    },
  66    .emit = gen6_upload_wm_push_constants,
  67 };
  68
  69 void
  70 gen6_upload_wm_state(struct brw_context *brw,
  71                      const struct brw_fragment_program *fp,
  72                      const struct brw_wm_prog_data *prog_data,
  73                      const struct brw_stage_state *stage_state,
  74                      bool multisampled_fbo, int min_inv_per_frag,
  75                      bool dual_source_blend_enable, bool kill_enable,
  76                      bool color_buffer_write_enable, bool msaa_enabled,
  77                      bool line_stipple_enable, bool polygon_stipple_enable,
  78                      bool statistic_enable)
  79 {
  80    uint32_t dw2, dw4, dw5, dw6, ksp0, ksp2;
  81
  82    /* We can't fold this into gen6_upload_wm_push_constants(), because
  83     * according to the SNB PRM, vol 2 part 1 section 7.2.2
  84     * (3DSTATE_CONSTANT_PS [DevSNB]):
  85     *
  86     *     "[DevSNB]: This packet must be followed by WM_STATE."
  87     */
  88    if (prog_data->base.nr_params == 0) {
  89       /* Disable the push constant buffers. */
  90       BEGIN_BATCH(5);
  91       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
  92       OUT_BATCH(0);
  93       OUT_BATCH(0);
  94       OUT_BATCH(0);
  95       OUT_BATCH(0);
  96       ADVANCE_BATCH();
  97    } else {
  98       BEGIN_BATCH(5);
  99       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 100                 GEN6_CONSTANT_BUFFER_0_ENABLE |
 101                 (5 - 2));
 102       /* Pointer to the WM constant buffer.  Covered by the set of
 103        * state flags from gen6_upload_wm_push_constants.
 104        */
 105       OUT_BATCH(stage_state->push_const_offset +
 106                 stage_state->push_const_size - 1);
 107       OUT_BATCH(0);
 108       OUT_BATCH(0);
 109       OUT_BATCH(0);
 110       ADVANCE_BATCH();
 111    }
 112
 113    dw2 = dw4 = dw5 = dw6 = ksp2 = 0;
 114
 115    if (statistic_enable)
 116       dw4 |= GEN6_WM_STATISTICS_ENABLE;
 117
 118    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
 119    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
 120
 121    if (prog_data->base.use_alt_mode)
 122       dw2 |= GEN6_WM_FLOATING_POINT_MODE_ALT;
 123
 124    dw2 |= (ALIGN(stage_state->sampler_count, 4) / 4) <<
 125            GEN6_WM_SAMPLER_COUNT_SHIFT;
 126
 127    dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
 128            GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 129
 130    dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 131
 132    assert(min_inv_per_frag >= 1);
 133
 134    if (prog_data->prog_offset_16 || prog_data->no_8) {
 135       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
 136
 137       if (!prog_data->no_8 && min_inv_per_frag == 1) {
 138          dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
 139          dw4 |= (prog_data->base.dispatch_grf_start_reg <<
 140                  GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 141          dw4 |= (prog_data->dispatch_grf_start_reg_16 <<
 142                  GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
 143          ksp0 = stage_state->prog_offset;
 144          ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
 145       } else {
 146          dw4 |= (prog_data->dispatch_grf_start_reg_16 <<
 147                 GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 148          ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
 149       }
 150    }
 151    else {
 152       dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
 153       dw4 |= (prog_data->base.dispatch_grf_start_reg <<
 154               GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 155       ksp0 = stage_state->prog_offset;
 156    }
 157
 158    if (dual_source_blend_enable)
 159       dw5 |= GEN6_WM_DUAL_SOURCE_BLEND_ENABLE;
 160
 161    if (line_stipple_enable)
 162       dw5 |= GEN6_WM_LINE_STIPPLE_ENABLE;
 163
 164    if (polygon_stipple_enable)
 165       dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
 166
 167    /* BRW_NEW_FRAGMENT_PROGRAM */
 168    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
 169       dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
 170    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 171       dw5 |= GEN6_WM_COMPUTED_DEPTH;
 172    dw6 |= prog_data->barycentric_interp_modes <<
 173       GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 174
 175    if (kill_enable)
 176       dw5 |= GEN6_WM_KILL_ENABLE;
 177
 178    if (color_buffer_write_enable ||
 179        dw5 & (GEN6_WM_KILL_ENABLE | GEN6_WM_COMPUTED_DEPTH))
 180       dw5 |= GEN6_WM_DISPATCH_ENABLE;
 181
 182    /* From the SNB PRM, volume 2 part 1, page 278:
 183     * "This bit is inserted in the PS payload header and made available to
 184     * the DataPort (either via the message header or via header bypass) to
 185     * indicate that oMask data (one or two phases) is included in Render
 186     * Target Write messages. If present, the oMask data is used to mask off
 187     * samples."
 188     */
 189     if (prog_data->uses_omask)
 190       dw5 |= GEN6_WM_OMASK_TO_RENDER_TARGET;
 191
 192    dw6 |= prog_data->num_varying_inputs <<
 193       GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
 194    if (multisampled_fbo) {
 195       if (msaa_enabled)
 196          dw6 |= GEN6_WM_MSRAST_ON_PATTERN;
 197       else
 198          dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
 199
 200       if (min_inv_per_frag > 1)
 201          dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
 202       else {
 203          dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL;
 204
 205          /* From the Sandy Bridge PRM, Vol 2 part 1, 7.7.1 ("Pixel Grouping
 206           * (Dispatch Size) Control"), p.334:
 207           *
 208           *     Note: in the table below, the Valid column indicates which
 209           *     products that combination is supported on. Combinations of
 210           *     dispatch enables not listed in the table are not available on
 211           *     any product.
 212           *
 213           *     A: Valid on all products
 214           *
 215           *     B: Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader
 216           *     computed depth.
 217           *
 218           *     D: Valid on all products, except when in non-1x PERSAMPLE mode
 219           *     (applies to [DevSNB+] only). Not valid on [DevSNB] if 4x
 220           *     PERPIXEL mode with pixel shader computed depth.
 221           *
 222           *     E: Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader
 223           *     computed depth.
 224           *
 225           *     F: Valid on all products, except not valid on [DevSNB] if 4x
 226           *     PERPIXEL mode with pixel shader computed depth.
 227           *
 228           * In the table that follows, the only entry with "A" in the Valid
 229           * column is the entry where only 8 pixel dispatch is enabled.
 230           * Therefore, when we are in PERPIXEL mode with pixel shader computed
 231           * depth, we need to disable SIMD16 dispatch.
 232           */
 233          if (dw5 & GEN6_WM_COMPUTED_DEPTH)
 234             dw5 &= ~GEN6_WM_16_DISPATCH_ENABLE;
 235       }
 236    } else {
 237       dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
 238       dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
 239    }
 240
 241    /* From the SNB PRM, volume 2 part 1, page 281:
 242     * "If the PS kernel does not need the Position XY Offsets
 243     * to compute a Position XY value, then this field should be
 244     * programmed to POSOFFSET_NONE."
 245     *
 246     * "SW Recommendation: If the PS kernel needs the Position Offsets
 247     * to compute a Position XY value, this field should match Position
 248     * ZW Interpolation Mode to ensure a consistent position.xyzw
 249     * computation."
 250     * We only require XY sample offsets. So, this recommendation doesn't
 251     * look useful at the moment. We might need this in future.
 252     */
 253    if (prog_data->uses_pos_offset)
 254       dw6 |= GEN6_WM_POSOFFSET_SAMPLE;
 255    else
 256       dw6 |= GEN6_WM_POSOFFSET_NONE;
 257
 258    BEGIN_BATCH(9);
 259    OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
 260    OUT_BATCH(ksp0);
 261    OUT_BATCH(dw2);
 262    if (prog_data->base.total_scratch) {
 263       OUT_RELOC(stage_state->scratch_bo,
 264                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 265                 ffs(prog_data->base.total_scratch) - 11);
 266    } else {
 267       OUT_BATCH(0);
 268    }
 269    OUT_BATCH(dw4);
 270    OUT_BATCH(dw5);
 271    OUT_BATCH(dw6);
 272    OUT_BATCH(0); /* kernel 1 pointer */
 273    OUT_BATCH(ksp2);
 274    ADVANCE_BATCH();
 275 }
 276
 277 static void
 278 upload_wm_state(struct brw_context *brw)
 279 {
 280    struct gl_context *ctx = &brw->ctx;
 281    /* BRW_NEW_FRAGMENT_PROGRAM */
 282    const struct brw_fragment_program *fp =
 283       brw_fragment_program_const(brw->fragment_program);
 284    /* BRW_NEW_FS_PROG_DATA */
 285    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 286
 287    /* _NEW_BUFFERS */
 288    const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1;
 289
 290    /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 291     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 292     * is successfully compiled. In majority of the cases that bring us
 293     * better performance than 'SIMD8 only' dispatch.
 294     */
 295    const int min_inv_per_frag = _mesa_get_min_invocations_per_fragment(
 296                                    ctx, brw->fragment_program, false);
 297
 298    /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
 299    const bool dual_src_blend_enable = prog_data->dual_src_blend &&
 300                                       (ctx->Color.BlendEnabled & 1) &&
 301                                       ctx->Color.Blend[0]._UsesDualSrc;
 302
 303    /* _NEW_COLOR, _NEW_MULTISAMPLE */
 304    const bool kill_enable = prog_data->uses_kill || ctx->Color.AlphaEnabled ||
 305                             ctx->Multisample.SampleAlphaToCoverage ||
 306                             prog_data->uses_omask;
 307
 308    /* Rendering against the gl-context is always taken into account. */
 309    const bool statistic_enable = true;
 310
 311    /* _NEW_LINE | _NEW_POLYGON | _NEW_BUFFERS | _NEW_COLOR |
 312     * _NEW_MULTISAMPLE
 313     */
 314    gen6_upload_wm_state(brw, fp, prog_data, &brw->wm.base,
 315                         multisampled_fbo, min_inv_per_frag,
 316                         dual_src_blend_enable, kill_enable,
 317                         brw_color_buffer_write_enabled(brw),
 318                         ctx->Multisample.Enabled,
 319                         ctx->Line.StippleFlag, ctx->Polygon.StippleFlag,
 320                         statistic_enable);
 321 }
 322
 323 const struct brw_tracked_state gen6_wm_state = {
 324    .dirty = {
 325       .mesa  = _NEW_BUFFERS |
 326                _NEW_COLOR |
 327                _NEW_LINE |
 328                _NEW_MULTISAMPLE |
 329                _NEW_POLYGON |
 330                _NEW_PROGRAM_CONSTANTS,
 331       .brw   = BRW_NEW_BATCH |
 332                BRW_NEW_FRAGMENT_PROGRAM |
 333                BRW_NEW_FS_PROG_DATA |
 334                BRW_NEW_PUSH_CONSTANT_ALLOCATION,
 335    },
 336    .emit = upload_wm_state,
 337 };