src/mesa/drivers/dri/i965/gen6_wm_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "program/prog_parameter.h"
  33 #include "program/prog_statevars.h"
  34 #include "intel_batchbuffer.h"
  35
  36 static void
  37 prepare_wm_constants(struct brw_context *brw)
  38 {
  39    struct intel_context *intel = &brw->intel;
  40    GLcontext *ctx = &intel->ctx;
  41    const struct brw_fragment_program *fp =
  42       brw_fragment_program_const(brw->fragment_program);
  43
  44    drm_intel_bo_unreference(brw->wm.push_const_bo);
  45    brw->wm.push_const_bo = NULL;
  46
  47    /* Updates the ParamaterValues[i] pointers for all parameters of the
  48     * basic type of PROGRAM_STATE_VAR.
  49     */
  50    /* XXX: Should this happen somewhere before to get our state flag set? */
  51    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
  52
  53    if (brw->wm.prog_data->nr_params != 0) {
  54       float *constants;
  55       unsigned int i;
  56
  57       brw->wm.push_const_bo = drm_intel_bo_alloc(intel->bufmgr,
  58                                                  "WM constant_bo",
  59                                                  brw->wm.prog_data->nr_params *
  60                                                  sizeof(float),
  61                                                  4096);
  62       drm_intel_gem_bo_map_gtt(brw->wm.push_const_bo);
  63       constants = brw->wm.push_const_bo->virtual;
  64       for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
  65          constants[i] = *brw->wm.prog_data->param[i];
  66       }
  67       drm_intel_gem_bo_unmap_gtt(brw->wm.push_const_bo);
  68    }
  69 }
  70
  71 const struct brw_tracked_state gen6_wm_constants = {
  72    .dirty = {
  73       .mesa  = _NEW_PROGRAM_CONSTANTS,
  74       .brw   = 0,
  75       .cache = 0,
  76    },
  77    .prepare = prepare_wm_constants,
  78 };
  79
  80 static void
  81 upload_wm_state(struct brw_context *brw)
  82 {
  83    struct intel_context *intel = &brw->intel;
  84    GLcontext *ctx = &intel->ctx;
  85    const struct brw_fragment_program *fp =
  86       brw_fragment_program_const(brw->fragment_program);
  87    uint32_t dw2, dw4, dw5, dw6;
  88
  89    if (fp->use_const_buffer || brw->wm.prog_data->nr_params == 0) {
  90       /* Disable the push constant buffers. */
  91       BEGIN_BATCH(5);
  92       OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2));
  93       OUT_BATCH(0);
  94       OUT_BATCH(0);
  95       OUT_BATCH(0);
  96       OUT_BATCH(0);
  97       ADVANCE_BATCH();
  98    } else {
  99       BEGIN_BATCH(5);
 100       OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 |
 101                 GEN6_CONSTANT_BUFFER_0_ENABLE |
 102                 (5 - 2));
 103       OUT_RELOC(brw->wm.push_const_bo,
 104                 I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
 105                 ALIGN(brw->wm.prog_data->nr_params, 8) / 8 - 1);
 106       OUT_BATCH(0);
 107       OUT_BATCH(0);
 108       OUT_BATCH(0);
 109       ADVANCE_BATCH();
 110    }
 111
 112    intel_batchbuffer_emit_mi_flush(intel->batch);
 113
 114    dw2 = dw4 = dw5 = dw6 = 0;
 115    dw4 |= GEN6_WM_STATISTICS_ENABLE;
 116    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
 117    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
 118
 119    /* BRW_NEW_NR_SURFACES */
 120    dw2 |= brw->wm.nr_surfaces << GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT;
 121
 122    /* CACHE_NEW_SAMPLER */
 123    dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN6_WM_SAMPLER_COUNT_SHIFT;
 124    dw4 |= (brw->wm.prog_data->first_curbe_grf <<
 125            GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 126
 127    dw5 |= (40 - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 128    dw5 |= GEN6_WM_DISPATCH_ENABLE;
 129
 130    /* BRW_NEW_FRAGMENT_PROGRAM */
 131    if (fp->isGLSL)
 132       dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
 133    else
 134       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
 135
 136    /* _NEW_LINE */
 137    if (ctx->Line.StippleFlag)
 138       dw5 |= GEN6_WM_LINE_STIPPLE_ENABLE;
 139
 140    /* _NEW_POLYGONSTIPPLE */
 141    if (ctx->Polygon.StippleFlag)
 142       dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
 143
 144    /* BRW_NEW_FRAGMENT_PROGRAM */
 145    if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
 146       dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
 147    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 148       dw5 |= GEN6_WM_COMPUTED_DEPTH;
 149
 150    /* _NEW_COLOR */
 151    if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
 152       dw5 |= GEN6_WM_KILL_ENABLE;
 153
 154    dw6 |= GEN6_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
 155
 156    dw6 |= brw_count_bits(brw->fragment_program->Base.InputsRead) <<
 157       GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
 158
 159    BEGIN_BATCH(9);
 160    OUT_BATCH(CMD_3D_WM_STATE << 16 | (9 - 2));
 161    OUT_RELOC(brw->wm.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 162    OUT_BATCH(dw2);
 163    OUT_BATCH(0); /* scratch space base offset */
 164    OUT_BATCH(dw4);
 165    OUT_BATCH(dw5);
 166    OUT_BATCH(dw6);
 167    OUT_BATCH(0); /* kernel 1 pointer */
 168    OUT_BATCH(0); /* kernel 2 pointer */
 169    ADVANCE_BATCH();
 170
 171    intel_batchbuffer_emit_mi_flush(intel->batch);
 172 }
 173
 174 const struct brw_tracked_state gen6_wm_state = {
 175    .dirty = {
 176       .mesa  = _NEW_LINE | _NEW_POLYGONSTIPPLE | _NEW_COLOR,
 177       .brw   = (BRW_NEW_CURBE_OFFSETS |
 178                 BRW_NEW_FRAGMENT_PROGRAM |
 179                 BRW_NEW_NR_WM_SURFACES |
 180                 BRW_NEW_URB_FENCE |
 181                 BRW_NEW_BATCH),
 182       .cache = CACHE_NEW_SAMPLER
 183    },
 184    .emit = upload_wm_state,
 185 };